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https://github.com/DavidBuchanan314/6502-emu.git
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Added decimal mode for ADC and SBC
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parent
a25ad398e8
commit
20d6e48c9f
28
6502.c
28
6502.c
@ -64,7 +64,13 @@ static inline void take_branch()
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static void inst_ADC()
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static void inst_ADC()
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{
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{
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uint8_t operand = * read_ptr();
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uint8_t operand = * read_ptr();
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int tmp = A + operand + (SR.bits.carry & 1);
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unsigned int tmp = A + operand + (SR.bits.carry & 1);
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if (SR.bits.decimal) {
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tmp = (A & 0x0f) + (operand & 0x0f) + (SR.bits.carry & 1);
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if (tmp >= 10) tmp = (tmp - 10) | 0x10;
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tmp += (A & 0xf0) + (operand & 0xf0);
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if (tmp > 0x9f) tmp += 0x60;
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}
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SR.bits.carry = tmp > 0xFF;
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SR.bits.carry = tmp > 0xFF;
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SR.bits.overflow = ((A^tmp)&(operand^tmp)&0x80) != 0;
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SR.bits.overflow = ((A^tmp)&(operand^tmp)&0x80) != 0;
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A = tmp & 0xFF;
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A = tmp & 0xFF;
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@ -403,11 +409,21 @@ static void inst_RTS()
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static void inst_SBC()
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static void inst_SBC()
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{
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{
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uint8_t operand = ~(* read_ptr()); // identical to ACD with the operand inverted
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uint8_t operand = * read_ptr();
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int tmp = A + operand + (SR.bits.carry & 1);
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unsigned int tmp, lo, hi;
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SR.bits.carry = tmp > 0xFF;
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tmp = A - operand - 1 + (SR.bits.carry & 1);
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SR.bits.overflow = ((A^tmp)&(operand^tmp)&0x80) != 0;
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SR.bits.overflow = ((A^tmp)&(A^operand)&0x80) != 0;
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A = tmp & 0xFF;
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if (SR.bits.decimal) {
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lo = (A & 0x0f) - (operand & 0x0f) - 1 + SR.bits.carry;
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hi = (A >> 4) - (operand >> 4);
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if (lo & 0x10) lo -= 6, hi--;
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if (hi & 0x10) hi -= 6;
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A = (hi << 4) | (lo & 0x0f);
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}
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else {
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A = tmp & 0xFF;
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}
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SR.bits.carry = tmp < 0x100;
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N_flag(A);
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N_flag(A);
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Z_flag(A);
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Z_flag(A);
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}
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}
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