merge old and new dsl

This commit is contained in:
Mark Canlas 2020-08-16 00:58:25 -04:00
parent c9977eb6ad
commit 101c08094f
4 changed files with 37 additions and 2 deletions

View File

@ -17,7 +17,12 @@ class AsmDocumentContext {
sealed trait TopLevelAsmDocumentFragment
sealed trait AsmBlockFragment extends TopLevelAsmDocumentFragment
case class AsmFragment(xs: List[Statement]) extends TopLevelAsmDocumentFragment {
def printOut(): Unit = {
xs.map(_.toAsm)
.foreach(println)
}
}
case class DefinitionGroup(comment: String, xs: List[Definition[_]]) extends TopLevelAsmDocumentFragment

View File

@ -126,4 +126,7 @@ class AssemblyContext {
def triplets: List[(String, Option[String], Option[String])] =
xs.map(_.toTriplet).toList
def toFragment: AsmFragment =
AsmFragment(xs.toList)
}

View File

@ -10,6 +10,16 @@ package object dsl {
ctx.toDoc
}
def asm(f: AssemblyContext => Unit)(implicit ctx: AsmDocumentContext): Unit = {
val asmCtx: AssemblyContext =
new AssemblyContext
f(asmCtx)
ctx
.push(asmCtx.toFragment)
}
def group[A](s: String)(f: DefinitionGroupContext => A)(implicit ctx: AsmDocumentContext): A = {
val g: DefinitionGroupContext =
new DefinitionGroupContext

View File

@ -33,9 +33,26 @@ class Easy6502Spec extends AnyFlatSpec with should.Matchers {
val doc =
asmDoc { implicit ctx =>
enum[Color]
asm { implicit a =>
val scr =
IndexedAddressCollection[Color](0x0200, "screen")
scr.write(0, Color.White)
scr.write(1, Color.Green)
scr.write(2, Color.Orange)
}
}
println(doc)
doc
.xs
.foreach {
case DefinitionGroup(c, xs) =>
println(c)
xs.foreach(println)
case a: AsmFragment =>
a.printOut()
}
}
def withAssemblyContext(f: AssemblyContext => Unit): AssemblyContext = {