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fix lda
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parent
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@ -93,8 +93,8 @@ class CPU {
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def A: registers.A.type =
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registers.A
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def A_=[A : Operand](x: A)(implicit ctx: AssemblyContext, ev: Operand[A]): Unit =
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ctx.push(LDA, "set A to value " + ev.toString(x))
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def A_=[A](x: A)(implicit ctx: AssemblyContext, ev: Operand[A]): Unit =
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ctx.push(LDA, x, "set A to value " + ev.toString(x))
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def A_=(reg: registers.DestinationA)(implicit ctx: AssemblyContext): Unit =
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reg match {
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