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trim types; use cats

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This commit is contained in:
Mark Canlas 2020-08-12 21:10:19 -04:00
parent e432132328
commit e5a2830be6
3 changed files with 20 additions and 9 deletions
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1
build.sbt
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@ -6,3 +6,4 @@ lazy val root =
libraryDependencies += "org.scalatest" %% "scalatest" % "3.2.1" % "test",
scalafmtOnCompile := true
)
.withCats

8
project/ProjectPlugin.scala
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@ -7,4 +7,12 @@ object ProjectPlugin extends AutoPlugin {
override lazy val projectSettings = Seq(
scalaVersion := "2.13.3"
)
object autoImport {
implicit class ProjectOps(p: Project) {
def withCats: Project =
p
.settings(libraryDependencies += "org.typelevel" %% "cats-core" % "2.2.0-RC2")
}
}
}

20
src/main/scala/com/htmlism/MatchOpcodes.scala
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@ -1,5 +1,7 @@
package com.htmlism
import cats.implicits._
import java.io.PrintWriter
object MatchOpcodes {
@ -222,41 +224,41 @@ object MatchOpcodes {
n match {
case BitPattern(aaabbb, cc) =>
cc match {
case 0 => (c00 _).tupled(aaabbb)
case 1 => (c01 _).tupled(aaabbb)
case 2 => (c10 _).tupled(aaabbb)
case 0 => (c00 _).tupled(aaabbb).some
case 1 => (c01 _).tupled(aaabbb).some
case 2 => (c10 _).tupled(aaabbb).some
case 3 => None
}
}
}
def c01(aaa: Int, bbb: Int): Option[(Instruction, AddressingMode)] = {
def c01(aaa: Int, bbb: Int): (Instruction, AddressingMode) = {
val instruction =
Seq(ORA, AND, EOR, ADC, STA, LDA, CMP, SBC)(aaa)
val addressingMode =
Seq(IndirectX, ZeroPage, Immediate, Absolute, IndirectY, ZeroPageX, AbsoluteY, AbsoluteX)(bbb)
Some(instruction -> addressingMode)
instruction -> addressingMode
}
def c10(aaa: Int, bbb: Int): Option[(Instruction, AddressingMode)] = {
def c10(aaa: Int, bbb: Int): (Instruction, AddressingMode) = {
val instruction =
Seq(ASL, ROL, LSR, ROR, STX, LDX, DEC, INC)(aaa)
val addressingMode =
Seq(Immediate, ZeroPage, Accumulator, Absolute, NoMode, ZeroPageX, NoMode, AbsoluteX)(bbb)
Some(instruction -> addressingMode)
instruction -> addressingMode
}
def c00(aaa: Int, bbb: Int): Option[(Instruction, AddressingMode)] = {
def c00(aaa: Int, bbb: Int): (Instruction, AddressingMode) = {
val instruction =
Seq(NoInstruction, BIT, JMP, JMP, STY, LDY, CPY, CPX)(aaa)
val addressingMode =
Seq(Immediate, ZeroPage, NoMode, Absolute, NoMode, ZeroPageX, NoMode, AbsoluteX)(bbb)
Some(instruction -> addressingMode)
instruction -> addressingMode
}
}