44 lines
3.5 KiB
Markdown
44 lines
3.5 KiB
Markdown
- normalize A, X, Y, ZP, and GP to "registers", allocated by an allocator
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- X and Y are also index registers, so slightly special
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- unit test: what if a for loop is three deep? the outermost loop must be a memory register
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- it would be cool for the 22-tuple Scala code generator code writer to go to files
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- and make the +1 methods optional (for when it is at max == 22)
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- the payload/`xs` of a program should be an ADT of either chunks or one instruction
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- where a chunk is just many instructions
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- and an instruction already has the value X with its encoder, but chooses an eternal mode
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- depending on the asm language or config
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- create classes for read/write, read-only (volatile), and write-only memory locations
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- zero page and absolute
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- but how do we encode it? subclassing?
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- writing a value does two things
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1. establishes a fungible "init" phase (where we can take advantage of accumulator sharing)
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2. allows read-leases for some known scope
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- shared initialization can happen with constants but can also be shared with read side effects
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- is the spec for reading from a register descriable as data? e.g. are these two requests semantically equal vs independent side-effects
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- but what then is a write lease and how is it finite?
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- every register must offer up read or write leases that other instructions can use and emit AsmN programs of
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- a method that offers up a lease maybe has a return type completely inherited from its body (doesn't know N shape, other than that the register should participate somewhere)
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- maybe the AXY registers don't offer up leases and are always consumed in predictable, prepackaged ways
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- there needs to be another abstraction. just because reads and writes are tracked, doesn't mean they tie to exactly single addresses (think of a mechanism with many independent switches, all producing separate write actions)
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- automatic address assignment; if you stack them in a list, you can at "compile" time just assign registers from 0 to n
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- have an easy combinator to switch between byte and word length
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- and another combinator to switch between zero and global (maybe global is the default and zero is opt-in)
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- stack register assignment
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- helper functions like multiplication (?) probably need a temp working area
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- if always used like a well bounded resource, maybe you can keep reusing this temp area with different functions
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- but if some one subroutine or "context" uses a function twice (e.g. 3 * 4 * 5) then the stack depth for that context is at least two now, which can be known at interpretation time by going through the call graph
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- imagine the multiplier operation providing context/a lease and every operation on that lease actually pushes onto a stack
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- 99% of the time the stack size would just be one but it could be for nested calls something else
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- and then very late into register assignment (above) it would occupy N registers
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- what if you model all functions using the same "bounce" area and then just use this as the canonical way to calculate stack depth
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- this would maybe be "optimal" register allocation?
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## Advanced vs basic interpreters
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- Given "basic" elements `foo` and `bar`
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- And given another advanced feature `superfoo`
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- `foo` and `bar` should inhereit both `BasicInterpreter` and `AdvancedInterpreter`
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- and `superfoo` should only inherit `AdvancedInterpreter`
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- Then `superfoo` just be desugared into many `BasicInterpreter` blocks
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- And then the interpretation for `foo` and `bar` under advanced just echos them as `BasicInterpreter`
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