2013-08-07 16:56:09 +00:00
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; 6 5 0 2 F U N C T I O N A L T E S T
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;
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; Copyright (C) 2012-2013 Klaus Dormann
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;
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; This program is free software: you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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; the Free Software Foundation, either version 3 of the License, or
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; (at your option) any later version.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with this program. If not, see <http://www.gnu.org/licenses/>.
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; This program is designed to test all opcodes of a 6502 emulator using all
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; addressing modes with focus on propper setting of the processor status
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; register bits.
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;
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2013-08-16 11:30:31 +00:00
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; version 16-aug-2013
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2013-08-07 16:56:09 +00:00
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; contact info at http://2m5.de or email K@2m5.de
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;
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; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/
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; command line switches: -l -m -s2 -w -h0
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; | | | | no page headers in listing
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; | | | wide listing (133 char/col)
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; | | write intel hex file instead of binary
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; | expand macros in listing
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; generate pass2 listing
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;
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; No IO - should be run from a monitor with access to registers.
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; To run load intel hex image with a load command, than alter PC to 400 hex
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; (code_segment) and enter a go command.
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; Loop on program counter determines error or successful completion of test.
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; Check listing for relevant traps (jump/branch *).
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; Please note that in early tests some instructions will have to be used before
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; they are actually tested!
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;
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; RESET, NMI or IRQ should not occur and will be trapped if vectors are enabled.
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; Tests documented behavior of the original NMOS 6502 only! No unofficial
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; opcodes. Additional opcodes of newer versions of the CPU (65C02, 65816) will
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; not be tested. Decimal ops will only be tested with valid BCD operands and
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; N V Z flags will be ignored.
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;
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; Debugging hints:
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; Most of the code is written sequentially. if you hit a trap, check the
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; immediately preceeding code for the instruction to be tested. Results are
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; tested first, flags are checked second by pushing them onto the stack and
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; pulling them to the accumulator after the result was checked. The "real"
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; flags are no longer valid for the tested instruction at this time!
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; If the tested instruction was indexed, the relevant index (X or Y) must
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; also be checked. Opposed to the flags, X and Y registers are still valid.
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;
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; versions:
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; 28-jul-2012 1st version distributed for testing
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; 29-jul-2012 fixed references to location 0, now #0
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; added license - GPLv3
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; 30-jul-2012 added configuration options
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; 01-aug-2012 added trap macro to allow user to change error handling
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; 01-dec-2012 fixed trap in branch field must be a branch
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; 02-mar-2013 fixed PLA flags not tested
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; 19-jul-2013 allowed ROM vectors to be loaded when load_data_direct = 0
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; added test sequence check to detect if tests jump their fence
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2013-08-16 11:30:31 +00:00
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; 23-jul-2013 added RAM integrity check option
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; 16-aug-2013 added error report to standard output option
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2013-08-07 16:56:09 +00:00
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; C O N F I G U R A T I O N
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2013-08-16 11:30:31 +00:00
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2013-08-07 16:56:09 +00:00
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;ROM_vectors writable (0=no, 1=yes)
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;if ROM vectors can not be used interrupts will not be trapped
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;as a consequence BRK can not be tested but will be emulated to test RTI
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ROM_vectors = 1
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2013-08-16 11:30:31 +00:00
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2013-08-07 16:56:09 +00:00
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;load_data_direct (0=move from code segment, 1=load directly)
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;loading directly is preferred but may not be supported by your platform
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;0 produces only consecutive object code, 1 is not suitable for a binary image
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load_data_direct = 1
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2013-08-16 11:30:31 +00:00
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2013-08-07 16:56:09 +00:00
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;I_flag behavior (0=force enabled, 1=force disabled, 2=prohibit change, 3=allow
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;change) 2 requires extra code and is not recommended. SEI & CLI can only be
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;tested if you allow changing the interrupt status (I_flag = 3)
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I_flag = 3
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2013-08-16 11:30:31 +00:00
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2013-08-07 16:56:09 +00:00
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;configure memory - try to stay away from memory used by the system
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;zero_page memory start address, $50 (80) consecutive Bytes required
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; add 2 if I_flag = 2
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zero_page = $a
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2013-08-16 11:30:31 +00:00
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2013-08-07 16:56:09 +00:00
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;data_segment memory start address, $5B (91) consecutive Bytes required
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data_segment = $200
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if (data_segment & $ff) != 0
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ERROR ERROR ERROR low byte of data_segment MUST be $00 !!
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endif
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2013-08-16 11:30:31 +00:00
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2013-08-07 16:56:09 +00:00
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;code_segment memory start address, 13kB of consecutive space required
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; add 2.5 kB if I_flag = 2
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;parts of the code are self modifying and must reside in RAM
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code_segment = $400
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2013-08-16 11:30:31 +00:00
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;report errors through I/O channel (0=use standard self trap loops, 1=include
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;report.i65 as I/O channel, add 3.5 kB)
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report = 0
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2013-08-07 16:56:09 +00:00
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;RAM integrity test option. Checks for undesired RAM writes.
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;set lowest non RAM or RAM mirror address page (-1=disable, 0=64k, $40=16k)
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;leave disabled if a monitor, OS or background interrupt is allowed to alter RAM
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ram_top = -1
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noopt ;do not take shortcuts
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;macros for error & success traps to allow user modification
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;example:
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;trap macro
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; jsr my_error_handler
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; endm
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;trap_eq macro
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; bne skip\?
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; trap ;failed equal (zero)
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;skip\?
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; endm
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;
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; my_error_handler should pop the calling address from the stack and report it.
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; putting larger portions of code (more than 3 bytes) inside the trap macro
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; may lead to branch range problems for some tests.
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2013-08-16 11:30:31 +00:00
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if report = 0
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2013-08-07 16:56:09 +00:00
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trap macro
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jmp * ;failed anyway
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endm
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trap_eq macro
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beq * ;failed equal (zero)
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endm
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trap_ne macro
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bne * ;failed not equal (non zero)
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endm
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trap_cs macro
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bcs * ;failed carry set
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endm
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trap_cc macro
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bcc * ;failed carry clear
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endm
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trap_mi macro
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bmi * ;failed minus (bit 7 set)
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endm
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trap_pl macro
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bpl * ;failed plus (bit 7 clear)
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endm
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trap_vs macro
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bvs * ;failed overflow set
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endm
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trap_vc macro
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bvc * ;failed overflow clear
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endm
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2013-08-16 11:30:31 +00:00
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; please observe that during the test the stack gets invalidated
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; therefore a RTS inside the success macro is not possible
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2013-08-07 16:56:09 +00:00
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success macro
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jmp * ;test passed, no errors
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endm
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2013-08-16 11:30:31 +00:00
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endif
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if report = 1
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trap macro
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jsr report_error
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endm
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trap_eq macro
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bne skip\?
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trap ;failed equal (zero)
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skip\?
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endm
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trap_ne macro
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beq skip\?
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trap ;failed not equal (non zero)
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skip\?
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endm
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trap_cs macro
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bcc skip\?
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trap ;failed carry set
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skip\?
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endm
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trap_cc macro
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bcs skip\?
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trap ;failed carry clear
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skip\?
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endm
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trap_mi macro
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bpl skip\?
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trap ;failed minus (bit 7 set)
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skip\?
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endm
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trap_pl macro
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bmi skip\?
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trap ;failed plus (bit 7 clear)
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skip\?
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endm
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trap_vs macro
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bvc skip\?
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trap ;failed overflow set
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skip\?
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endm
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trap_vc macro
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bvs skip\?
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trap ;failed overflow clear
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skip\?
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endm
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; please observe that during the test the stack gets invalidated
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; therefore a RTS inside the success macro is not possible
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success macro
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jsr report_success
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endm
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endif
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2013-08-07 16:56:09 +00:00
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carry equ %00000001 ;flag bits in status
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zero equ %00000010
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intdis equ %00000100
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decmode equ %00001000
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break equ %00010000
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reserv equ %00100000
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overfl equ %01000000
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minus equ %10000000
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fc equ carry
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fz equ zero
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fzc equ carry+zero
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fv equ overfl
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fvz equ overfl+zero
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fn equ minus
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fnc equ minus+carry
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fnz equ minus+zero
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fnzc equ minus+zero+carry
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fnv equ minus+overfl
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fao equ break+reserv ;bits always on after PHP, BRK
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fai equ fao+intdis ;+ forced interrupt disable
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m8 equ $ff ;8 bit mask
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m8i equ $ff&~intdis ;8 bit mask - interrupt disable
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;macros to allow masking of status bits.
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;masking of interrupt enable/disable on load and compare
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;masking of always on bits after PHP or BRK (unused & break) on compare
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if I_flag = 0
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load_flag macro
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lda #\1&m8i ;force enable interrupts (mask I)
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endm
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cmp_flag macro
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cmp #(\1|fao)&m8i ;I_flag is always enabled + always on bits
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endm
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eor_flag macro
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eor #(\1&m8i|fao) ;mask I, invert expected flags + always on bits
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endm
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endif
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if I_flag = 1
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load_flag macro
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lda #\1|intdis ;force disable interrupts
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endm
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cmp_flag macro
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cmp #(\1|fai)&m8 ;I_flag is always disabled + always on bits
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endm
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eor_flag macro
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eor #(\1|fai) ;invert expected flags + always on bits + I
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endm
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endif
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if I_flag = 2
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load_flag macro
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lda #\1
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ora flag_I_on ;restore I-flag
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and flag_I_off
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endm
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cmp_flag macro
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eor flag_I_on ;I_flag is never changed
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cmp #(\1|fao)&m8i ;expected flags + always on bits, mask I
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endm
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eor_flag macro
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eor flag_I_on ;I_flag is never changed
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eor #(\1&m8i|fao) ;mask I, invert expected flags + always on bits
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endm
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endif
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if I_flag = 3
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load_flag macro
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lda #\1 ;allow test to change I-flag (no mask)
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endm
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cmp_flag macro
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cmp #(\1|fao)&m8 ;expected flags + always on bits
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endm
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eor_flag macro
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eor #\1|fao ;invert expected flags + always on bits
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endm
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endif
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;macros to set (register|memory|zeropage) & status
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set_stat macro ;setting flags in the processor status register
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load_flag \1
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pha ;use stack to load status
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plp
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endm
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set_a macro ;precharging accu & status
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load_flag \2
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pha ;use stack to load status
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lda #\1 ;precharge accu
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plp
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endm
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set_x macro ;precharging index & status
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load_flag \2
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pha ;use stack to load status
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ldx #\1 ;precharge index x
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plp
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endm
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set_y macro ;precharging index & status
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load_flag \2
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pha ;use stack to load status
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ldy #\1 ;precharge index y
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plp
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endm
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set_ax macro ;precharging indexed accu & immediate status
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|
|
|
load_flag \2
|
|
|
|
|
pha ;use stack to load status
|
|
|
|
|
lda \1,x ;precharge accu
|
|
|
|
|
plp
|
|
|
|
|
endm
|
|
|
|
|
|
|
|
|
|
set_ay macro ;precharging indexed accu & immediate status
|
|
|
|
|
load_flag \2
|
|
|
|
|
pha ;use stack to load status
|
|
|
|
|
lda \1,y ;precharge accu
|
|
|
|
|
plp
|
|
|
|
|
endm
|
|
|
|
|
|
|
|
|
|
set_z macro ;precharging indexed zp & immediate status
|
|
|
|
|
load_flag \2
|
|
|
|
|
pha ;use stack to load status
|
|
|
|
|
lda \1,x ;load to zeropage
|
|
|
|
|
sta zpt
|
|
|
|
|
plp
|
|
|
|
|
endm
|
|
|
|
|
|
|
|
|
|
set_zx macro ;precharging zp,x & immediate status
|
|
|
|
|
load_flag \2
|
|
|
|
|
pha ;use stack to load status
|
|
|
|
|
lda \1,x ;load to indexed zeropage
|
|
|
|
|
sta zpt,x
|
|
|
|
|
plp
|
|
|
|
|
endm
|
|
|
|
|
|
|
|
|
|
set_abs macro ;precharging indexed memory & immediate status
|
|
|
|
|
load_flag \2
|
|
|
|
|
pha ;use stack to load status
|
|
|
|
|
lda \1,x ;load to memory
|
|
|
|
|
sta abst
|
|
|
|
|
plp
|
|
|
|
|
endm
|
|
|
|
|
|
|
|
|
|
set_absx macro ;precharging abs,x & immediate status
|
|
|
|
|
load_flag \2
|
|
|
|
|
pha ;use stack to load status
|
|
|
|
|
lda \1,x ;load to indexed memory
|
|
|
|
|
sta abst,x
|
|
|
|
|
plp
|
|
|
|
|
endm
|
|
|
|
|
|
|
|
|
|
;macros to test (register|memory|zeropage) & status & (mask)
|
|
|
|
|
tst_stat macro ;testing flags in the processor status register
|
|
|
|
|
php ;save status
|
|
|
|
|
php ;use stack to retrieve status
|
|
|
|
|
pla
|
|
|
|
|
cmp_flag \1
|
|
|
|
|
trap_ne
|
|
|
|
|
plp ;restore status
|
|
|
|
|
endm
|
|
|
|
|
|
|
|
|
|
tst_a macro ;testing result in accu & flags
|
|
|
|
|
php ;save flags
|
|
|
|
|
php
|
|
|
|
|
cmp #\1 ;test result
|
|
|
|
|
trap_ne
|
|
|
|
|
pla ;load status
|
|
|
|
|
cmp_flag \2
|
|
|
|
|
trap_ne
|
|
|
|
|
plp ;restore status
|
|
|
|
|
endm
|
|
|
|
|
|
|
|
|
|
tst_x macro ;testing result in x index & flags
|
|
|
|
|
php ;save flags
|
|
|
|
|
php
|
|
|
|
|
cpx #\1 ;test result
|
|
|
|
|
trap_ne
|
|
|
|
|
pla ;load status
|
|
|
|
|
cmp_flag \2
|
|
|
|
|
trap_ne
|
|
|
|
|
plp ;restore status
|
|
|
|
|
endm
|
|
|
|
|
|
|
|
|
|
tst_y macro ;testing result in y index & flags
|
|
|
|
|
php ;save flags
|
|
|
|
|
php
|
|
|
|
|
cpy #\1 ;test result
|
|
|
|
|
trap_ne
|
|
|
|
|
pla ;load status
|
|
|
|
|
cmp_flag \2
|
|
|
|
|
trap_ne
|
|
|
|
|
plp ;restore status
|
|
|
|
|
endm
|
|
|
|
|
|
|
|
|
|
tst_ax macro ;indexed testing result in accu & flags
|
|
|
|
|
php ;save flags
|
|
|
|
|
cmp \1,x ;test result
|
|
|
|
|
trap_ne
|
|
|
|
|
pla ;load status
|
|
|
|
|
eor_flag \3
|
|
|
|
|
cmp \2,x ;test flags
|
|
|
|
|
trap_ne ;
|
|
|
|
|
endm
|
|
|
|
|
|
|
|
|
|
tst_ay macro ;indexed testing result in accu & flags
|
|
|
|
|
php ;save flags
|
|
|
|
|
cmp \1,y ;test result
|
|
|
|
|
trap_ne ;
|
|
|
|
|
pla ;load status
|
|
|
|
|
eor_flag \3
|
|
|
|
|
cmp \2,y ;test flags
|
|
|
|
|
trap_ne
|
|
|
|
|
endm
|
|
|
|
|
|
|
|
|
|
tst_z macro ;indexed testing result in zp & flags
|
|
|
|
|
php ;save flags
|
|
|
|
|
lda zpt
|
|
|
|
|
cmp \1,x ;test result
|
|
|
|
|
trap_ne
|
|
|
|
|
pla ;load status
|
|
|
|
|
eor_flag \3
|
|
|
|
|
cmp \2,x ;test flags
|
|
|
|
|
trap_ne
|
|
|
|
|
endm
|
|
|
|
|
|
|
|
|
|
tst_zx macro ;testing result in zp,x & flags
|
|
|
|
|
php ;save flags
|
|
|
|
|
lda zpt,x
|
|
|
|
|
cmp \1,x ;test result
|
|
|
|
|
trap_ne
|
|
|
|
|
pla ;load status
|
|
|
|
|
eor_flag \3
|
|
|
|
|
cmp \2,x ;test flags
|
|
|
|
|
trap_ne
|
|
|
|
|
endm
|
|
|
|
|
|
|
|
|
|
tst_abs macro ;indexed testing result in memory & flags
|
|
|
|
|
php ;save flags
|
|
|
|
|
lda abst
|
|
|
|
|
cmp \1,x ;test result
|
|
|
|
|
trap_ne
|
|
|
|
|
pla ;load status
|
|
|
|
|
eor_flag \3
|
|
|
|
|
cmp \2,x ;test flags
|
|
|
|
|
trap_ne
|
|
|
|
|
endm
|
|
|
|
|
|
|
|
|
|
tst_absx macro ;testing result in abs,x & flags
|
|
|
|
|
php ;save flags
|
|
|
|
|
lda abst,x
|
|
|
|
|
cmp \1,x ;test result
|
|
|
|
|
trap_ne
|
|
|
|
|
pla ;load status
|
|
|
|
|
eor_flag \3
|
|
|
|
|
cmp \2,x ;test flags
|
|
|
|
|
trap_ne
|
|
|
|
|
endm
|
|
|
|
|
|
|
|
|
|
; RAM integrity test
|
|
|
|
|
; verifies that none of the previous tests has altered RAM outside of the
|
|
|
|
|
; designated write areas.
|
|
|
|
|
; uses zpt word as indirect pointer, zpt+2 word as checksum
|
|
|
|
|
if ram_top > -1
|
|
|
|
|
check_ram macro
|
|
|
|
|
cld
|
|
|
|
|
lda #0
|
|
|
|
|
sta zpt ;set low byte of indirect pointer
|
|
|
|
|
sta zpt+3 ;checksum high byte
|
|
|
|
|
sta range_adr ;reset self modifying code
|
|
|
|
|
sta tandi1
|
|
|
|
|
sta tandi2
|
|
|
|
|
sta teori1
|
|
|
|
|
sta teori2
|
|
|
|
|
sta torai1
|
|
|
|
|
sta torai2
|
|
|
|
|
sta chkdadi
|
|
|
|
|
sta chkdsbi
|
|
|
|
|
sta chkadi
|
|
|
|
|
sta chksbi
|
|
|
|
|
clc
|
|
|
|
|
ldx #zp_bss-zero_page ;zeropage - write test area
|
|
|
|
|
ccs3\? adc zero_page,x
|
|
|
|
|
bcc ccs2\?
|
|
|
|
|
inc zpt+3 ;carry to high byte
|
|
|
|
|
clc
|
|
|
|
|
ccs2\? inx
|
|
|
|
|
bne ccs3\?
|
|
|
|
|
ldx #hi(data_segment) ;set high byte of indirect pointer
|
|
|
|
|
stx zpt+1
|
|
|
|
|
ldy #lo(data_bss) ;data after write test area
|
|
|
|
|
ccs5\? adc (zpt),y
|
|
|
|
|
bcc ccs4\?
|
|
|
|
|
inc zpt+3 ;carry to high byte
|
|
|
|
|
clc
|
|
|
|
|
ccs4\? iny
|
|
|
|
|
bne ccs5\?
|
|
|
|
|
inx ;advance RAM high address
|
|
|
|
|
stx zpt+1
|
|
|
|
|
cpx #ram_top
|
|
|
|
|
bne ccs5\?
|
|
|
|
|
sta zpt+2 ;checksum low is
|
|
|
|
|
cmp ram_chksm ;checksum low expected
|
|
|
|
|
trap_ne ;checksum mismatch
|
|
|
|
|
lda zpt+3 ;checksum high is
|
|
|
|
|
cmp ram_chksm+1 ;checksum high expected
|
|
|
|
|
trap_ne ;checksum mismatch
|
|
|
|
|
endm
|
|
|
|
|
else
|
|
|
|
|
check_ram macro
|
|
|
|
|
;RAM check disabled - RAM size not set
|
|
|
|
|
endm
|
|
|
|
|
endif
|
|
|
|
|
|
|
|
|
|
next_test macro ;make sure, tests don't jump the fence
|
|
|
|
|
lda test_case ;previous test
|
|
|
|
|
cmp #test_num
|
|
|
|
|
trap_ne ;test is out of sequence
|
|
|
|
|
test_num = test_num + 1
|
2013-08-16 11:30:31 +00:00
|
|
|
lda #test_num ;*** next tests' number
|
2013-08-07 16:56:09 +00:00
|
|
|
sta test_case
|
|
|
|
|
;check_ram ;uncomment to find altered RAM after each test
|
|
|
|
|
endm
|
|
|
|
|
|
|
|
|
|
if load_data_direct = 1
|
|
|
|
|
data
|
|
|
|
|
else
|
|
|
|
|
bss ;uninitialized segment, copy of data at end of code!
|
|
|
|
|
endif
|
|
|
|
|
org zero_page
|
|
|
|
|
;break test interrupt save
|
|
|
|
|
irq_a ds 1 ;a register
|
|
|
|
|
irq_x ds 1 ;x register
|
|
|
|
|
if I_flag = 2
|
|
|
|
|
;masking for I bit in status
|
|
|
|
|
flag_I_on ds 1 ;or mask to load flags
|
|
|
|
|
flag_I_off ds 1 ;and mask to load flags
|
|
|
|
|
endif
|
|
|
|
|
zpt ;5 bytes store/modify test area
|
|
|
|
|
;add/subtract operand generation and result/flag prediction
|
|
|
|
|
adfc ds 1 ;carry flag before op
|
|
|
|
|
ad1 ds 1 ;operand 1 - accumulator
|
|
|
|
|
ad2 ds 1 ;operand 2 - memory / immediate
|
|
|
|
|
adrl ds 1 ;expected result bits 0-7
|
|
|
|
|
adrh ds 1 ;expected result bit 8 (carry)
|
2013-08-16 11:30:31 +00:00
|
|
|
adrf ds 1 ;expected flags NV0000ZC (only binary mode)
|
2013-08-07 16:56:09 +00:00
|
|
|
sb2 ds 1 ;operand 2 complemented for subtract
|
|
|
|
|
zp_bss
|
|
|
|
|
zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
|
|
|
|
|
zp7f db $7f ;test pattern for compare
|
|
|
|
|
;logical zeropage operands
|
|
|
|
|
zpOR db 0,$1f,$71,$80 ;test pattern for OR
|
|
|
|
|
zpAN db $0f,$ff,$7f,$80 ;test pattern for AND
|
|
|
|
|
zpEO db $ff,$0f,$8f,$8f ;test pattern for EOR
|
|
|
|
|
;indirect addressing pointers
|
|
|
|
|
ind1 dw abs1 ;indirect pointer to pattern in absolute memory
|
|
|
|
|
dw abs1+1
|
|
|
|
|
dw abs1+2
|
|
|
|
|
dw abs1+3
|
|
|
|
|
dw abs7f
|
|
|
|
|
inw1 dw abs1-$f8 ;indirect pointer for wrap-test pattern
|
|
|
|
|
indt dw abst ;indirect pointer to store area in absolute memory
|
|
|
|
|
dw abst+1
|
|
|
|
|
dw abst+2
|
|
|
|
|
dw abst+3
|
|
|
|
|
inwt dw abst-$f8 ;indirect pointer for wrap-test store
|
|
|
|
|
indAN dw absAN ;indirect pointer to AND pattern in absolute memory
|
|
|
|
|
dw absAN+1
|
|
|
|
|
dw absAN+2
|
|
|
|
|
dw absAN+3
|
|
|
|
|
indEO dw absEO ;indirect pointer to EOR pattern in absolute memory
|
|
|
|
|
dw absEO+1
|
|
|
|
|
dw absEO+2
|
|
|
|
|
dw absEO+3
|
|
|
|
|
indOR dw absOR ;indirect pointer to OR pattern in absolute memory
|
|
|
|
|
dw absOR+1
|
|
|
|
|
dw absOR+2
|
|
|
|
|
dw absOR+3
|
|
|
|
|
;add/subtract indirect pointers
|
|
|
|
|
adi2 dw ada2 ;indirect pointer to operand 2 in absolute memory
|
|
|
|
|
sbi2 dw sba2 ;indirect pointer to complemented operand 2 (SBC)
|
|
|
|
|
adiy2 dw ada2-$ff ;with offset for indirect indexed
|
|
|
|
|
sbiy2 dw sba2-$ff
|
|
|
|
|
zp_bss_end
|
|
|
|
|
|
|
|
|
|
org data_segment
|
|
|
|
|
test_case ds 1 ;current test number
|
|
|
|
|
ram_chksm ds 2 ;checksum for RAM integrity test
|
|
|
|
|
;add/subtract operand copy - abs tests write area
|
|
|
|
|
abst ;5 bytes store/modify test area
|
|
|
|
|
ada2 ds 1 ;operand 2
|
|
|
|
|
sba2 ds 1 ;operand 2 complemented for subtract
|
|
|
|
|
ds 3 ;fill remaining bytes
|
|
|
|
|
data_bss
|
|
|
|
|
abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
|
|
|
|
|
abs7f db $7f ;test pattern for compare
|
|
|
|
|
;loads
|
|
|
|
|
fLDx db fn,fn,0,fz ;expected flags for load
|
|
|
|
|
;shifts
|
|
|
|
|
rASL ;expected result ASL & ROL -carry
|
|
|
|
|
rROL db $86,$04,$82,0 ; "
|
|
|
|
|
rROLc db $87,$05,$83,1 ;expected result ROL +carry
|
|
|
|
|
rLSR ;expected result LSR & ROR -carry
|
|
|
|
|
rROR db $61,$41,$20,0 ; "
|
|
|
|
|
rRORc db $e1,$c1,$a0,$80 ;expected result ROR +carry
|
|
|
|
|
fASL ;expected flags for shifts
|
|
|
|
|
fROL db fnc,fc,fn,fz ;no carry in
|
|
|
|
|
fROLc db fnc,fc,fn,0 ;carry in
|
|
|
|
|
fLSR
|
|
|
|
|
fROR db fc,0,fc,fz ;no carry in
|
|
|
|
|
fRORc db fnc,fn,fnc,fn ;carry in
|
|
|
|
|
;increments (decrements)
|
|
|
|
|
rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC
|
|
|
|
|
fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC
|
|
|
|
|
;logical memory operand
|
|
|
|
|
absOR db 0,$1f,$71,$80 ;test pattern for OR
|
|
|
|
|
absAN db $0f,$ff,$7f,$80 ;test pattern for AND
|
|
|
|
|
absEO db $ff,$0f,$8f,$8f ;test pattern for EOR
|
|
|
|
|
;logical accu operand
|
|
|
|
|
absORa db 0,$f1,$1f,0 ;test pattern for OR
|
|
|
|
|
absANa db $f0,$ff,$ff,$ff ;test pattern for AND
|
|
|
|
|
absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR
|
|
|
|
|
;logical results
|
|
|
|
|
absrlo db 0,$ff,$7f,$80
|
|
|
|
|
absflo db fz,fn,0,fn
|
|
|
|
|
data_bss_end
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
code
|
|
|
|
|
org code_segment
|
|
|
|
|
start cld
|
2013-08-16 11:30:31 +00:00
|
|
|
ldx #$ff
|
|
|
|
|
txs
|
2013-08-07 16:56:09 +00:00
|
|
|
lda #0 ;*** test 0 = initialize
|
|
|
|
|
sta test_case
|
|
|
|
|
test_num = 0
|
|
|
|
|
|
|
|
|
|
;stop interrupts before initializing BSS
|
|
|
|
|
if I_flag = 1
|
|
|
|
|
sei
|
|
|
|
|
endif
|
|
|
|
|
|
2013-08-16 11:30:31 +00:00
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;initialize I/O for report channel
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if report = 1
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jsr report_init
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endif
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2013-08-07 16:56:09 +00:00
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;initialize BSS segment
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if load_data_direct != 1
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ldx #zp_end-zp_init-1
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ld_zp lda zp_init,x
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sta zp_bss,x
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dex
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bpl ld_zp
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ldx #data_end-data_init-1
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ld_data lda data_init,x
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sta data_bss,x
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dex
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bpl ld_data
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if ROM_vectors = 1
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ldx #5
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ld_vect lda vec_init,x
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sta vec_bss,x
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dex
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bpl ld_vect
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endif
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endif
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;retain status of interrupt flag
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if I_flag = 2
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php
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pla
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and #4 ;isolate flag
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sta flag_I_on ;or mask
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eor #lo(~4) ;reverse
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sta flag_I_off ;and mask
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endif
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;generate checksum for RAM integrity test
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if ram_top > -1
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lda #0
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sta zpt ;set low byte of indirect pointer
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sta ram_chksm+1 ;checksum high byte
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sta range_adr ;reset self modifying code
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sta tandi1
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sta tandi2
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sta teori1
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sta teori2
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sta torai1
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sta torai2
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sta chkdadi
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sta chkdsbi
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sta chkadi
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sta chksbi
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clc
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ldx #zp_bss-zero_page ;zeropage - write test area
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gcs3 adc zero_page,x
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bcc gcs2
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inc ram_chksm+1 ;carry to high byte
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clc
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gcs2 inx
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bne gcs3
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ldx #hi(data_segment) ;set high byte of indirect pointer
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stx zpt+1
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ldy #lo(data_bss) ;data after write test area
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gcs5 adc (zpt),y
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bcc gcs4
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inc ram_chksm+1 ;carry to high byte
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clc
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gcs4 iny
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bne gcs5
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inx ;advance RAM high address
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stx zpt+1
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cpx #ram_top
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bne gcs5
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sta ram_chksm ;checksum complete
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endif
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next_test
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;testing relative addressing with BEQ
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ldy #$fe ;testing maximum range, not -1/-2 (invalid/self adr)
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range_loop
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dey ;next relative address
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tya
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tax ;precharge count to end of loop
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bpl range_fw ;calculate relative address
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clc ;avoid branch self or to relative address of branch
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adc #2
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range_fw
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eor #$7f ;complement except sign
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sta range_adr ;load into test target
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lda #0 ;should set zero flag in status register
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jmp range_op
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;relative address target field with branch under test in the middle
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dex ;-128 - max backward
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;-120
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;-110
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;-100
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;-90
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;-80
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;-70
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;-60
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;-50
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;-40
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;-30
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;-20
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;-10
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;-3
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range_op ;test target with zero flag=0, z=1 if previous dex
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range_adr = *+1 ;modifiable relative address
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beq *+64 ;if called without modification
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dex ;+0
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;+10
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;+20
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;+30
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;+40
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;+50
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;+60
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;+70
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;+80
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;+90
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;+100
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex ;+110
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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dex
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|
dex ;+120
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dex
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dex
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dex
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dex
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|
dex
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|
dex
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beq range_ok ;+127 - max forward
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trap ; bad range
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range_ok
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cpy #0
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beq range_end
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jmp range_loop
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range_end ;range test successful
|
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next_test
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;partial test BNE & CMP, CPX, CPY immediate
|
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cpy #1 ;testing BNE true
|
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bne test_bne
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trap
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test_bne
|
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lda #0
|
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cmp #0 ;test compare immediate
|
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trap_ne
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trap_cc
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trap_mi
|
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|
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cmp #1
|
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trap_eq
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trap_cs
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trap_pl
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tax
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cpx #0 ;test compare x immediate
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trap_ne
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trap_cc
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trap_mi
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cpx #1
|
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trap_eq
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trap_cs
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trap_pl
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tay
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cpy #0 ;test compare y immediate
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trap_ne
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trap_cc
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trap_mi
|
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cpy #1
|
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trap_eq
|
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trap_cs
|
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trap_pl
|
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|
next_test
|
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|
|
|
;testing stack operations PHA PHP PLA PLP
|
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|
|
|
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|
|
ldx #$ff ;initialize stack
|
|
|
|
|
txs
|
|
|
|
|
lda #$55
|
|
|
|
|
pha
|
|
|
|
|
lda #$aa
|
|
|
|
|
pha
|
|
|
|
|
cmp $1fe ;on stack ?
|
|
|
|
|
trap_ne
|
|
|
|
|
tsx
|
|
|
|
|
txa ;overwrite accu
|
|
|
|
|
cmp #$fd ;sp decremented?
|
|
|
|
|
trap_ne
|
|
|
|
|
pla
|
|
|
|
|
cmp #$aa ;successful retreived from stack?
|
|
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trap_ne
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pla
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cmp #$55
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trap_ne
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cmp $1ff ;remains on stack?
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trap_ne
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tsx
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cpx #$ff ;sp incremented?
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trap_ne
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next_test
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;testing branch decisions BPL BMI BVC BVS BCC BCS BNE BEQ
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set_stat $ff ;all on
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bpl nbr1 ;branches should not be taken
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bvc nbr2
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bcc nbr3
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bne nbr4
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bmi br1 ;branches should be taken
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trap
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br1 bvs br2
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trap
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br2 bcs br3
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trap
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br3 beq br4
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trap
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nbr1
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trap ;previous bpl taken
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nbr2
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trap ;previous bvc taken
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nbr3
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trap ;previous bcc taken
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nbr4
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trap ;previous bne taken
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br4 php
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tsx
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cpx #$fe ;sp after php?
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trap_ne
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pla
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cmp_flag $ff ;returned all flags on?
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trap_ne
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tsx
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cpx #$ff ;sp after php?
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trap_ne
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set_stat 0 ;all off
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bmi nbr11 ;branches should not be taken
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bvs nbr12
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bcs nbr13
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beq nbr14
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bpl br11 ;branches should be taken
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trap
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br11 bvc br12
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trap
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br12 bcc br13
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trap
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br13 bne br14
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trap
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nbr11
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trap ;previous bmi taken
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nbr12
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trap ;previous bvs taken
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nbr13
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trap ;previous bcs taken
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nbr14
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trap ;previous beq taken
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br14 php
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pla
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cmp_flag 0 ;flags off except break (pushed by sw) + reserved?
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trap_ne
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;crosscheck flags
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set_stat zero
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2013-08-16 11:30:31 +00:00
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bne brzs1
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beq brzs2
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brzs1
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trap ;branch zero/non zero
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brzs2 bcs brzs3
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bcc brzs4
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brzs3
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trap ;branch carry/no carry
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brzs4 bmi brzs5
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bpl brzs6
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brzs5
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trap ;branch minus/plus
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brzs6 bvs brzs7
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bvc brzs8
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brzs7
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trap ;branch overflow/no overflow
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brzs8
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set_stat carry
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beq brcs1
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bne brcs2
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brcs1
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trap ;branch zero/non zero
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brcs2 bcc brcs3
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bcs brcs4
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brcs3
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trap ;branch carry/no carry
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brcs4 bmi brcs5
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bpl brcs6
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brcs5
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trap ;branch minus/plus
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brcs6 bvs brcs7
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bvc brcs8
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brcs7
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trap ;branch overflow/no overflow
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brcs8
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2013-08-07 16:56:09 +00:00
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set_stat minus
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2013-08-16 11:30:31 +00:00
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beq brmi1
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bne brmi2
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brmi1
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trap ;branch zero/non zero
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brmi2 bcs brmi3
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bcc brmi4
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brmi3
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trap ;branch carry/no carry
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brmi4 bpl brmi5
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bmi brmi6
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brmi5
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trap ;branch minus/plus
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brmi6 bvs brmi7
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bvc brmi8
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brmi7
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trap ;branch overflow/no overflow
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brmi8
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set_stat overfl
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beq brvs1
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bne brvs2
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brvs1
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trap ;branch zero/non zero
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brvs2 bcs brvs3
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bcc brvs4
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brvs3
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trap ;branch carry/no carry
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brvs4 bmi brvs5
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bpl brvs6
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brvs5
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trap ;branch minus/plus
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brvs6 bvc brvs7
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bvs brvs8
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brvs7
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trap ;branch overflow/no overflow
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brvs8
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2013-08-07 16:56:09 +00:00
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set_stat $ff-zero
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2013-08-16 11:30:31 +00:00
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beq brzc1
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bne brzc2
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brzc1
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trap ;branch zero/non zero
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brzc2 bcc brzc3
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bcs brzc4
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brzc3
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trap ;branch carry/no carry
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brzc4 bpl brzc5
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bmi brzc6
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brzc5
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trap ;branch minus/plus
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brzc6 bvc brzc7
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bvs brzc8
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brzc7
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trap ;branch overflow/no overflow
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brzc8
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set_stat $ff-carry
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bne brcc1
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beq brcc2
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brcc1
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trap ;branch zero/non zero
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brcc2 bcs brcc3
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bcc brcc4
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brcc3
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trap ;branch carry/no carry
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brcc4 bpl brcc5
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bmi brcc6
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brcc5
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trap ;branch minus/plus
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brcc6 bvc brcc7
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bvs brcc8
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brcc7
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trap ;branch overflow/no overflow
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brcc8
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2013-08-07 16:56:09 +00:00
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set_stat $ff-minus
|
2013-08-16 11:30:31 +00:00
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bne brpl1
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beq brpl2
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brpl1
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trap ;branch zero/non zero
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brpl2 bcc brpl3
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bcs brpl4
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brpl3
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trap ;branch carry/no carry
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brpl4 bmi brpl5
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bpl brpl6
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brpl5
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trap ;branch minus/plus
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brpl6 bvc brpl7
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bvs brpl8
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brpl7
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trap ;branch overflow/no overflow
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brpl8
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set_stat $ff-overfl
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bne brvc1
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beq brvc2
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brvc1
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trap ;branch zero/non zero
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brvc2 bcc brvc3
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bcs brvc4
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|
