mirror of
https://github.com/Klaus2m5/6502_65C02_functional_tests.git
synced 2024-09-07 20:54:29 +00:00
fixed shifts not testing zero result and flag when last 1-bit is shifted out
This commit is contained in:
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@ -1,7 +1,7 @@
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;
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; 6 5 0 2 F U N C T I O N A L T E S T
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;
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; Copyright (C) 2012-2015 Klaus Dormann
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; Copyright (C) 2012-2020 Klaus Dormann
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;
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; This program is free software: you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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@ -21,10 +21,11 @@
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; addressing modes with focus on propper setting of the processor status
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; register bits.
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;
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; version 04-dec-2017
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; version 05-jan-2020
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; contact info at http://2m5.de or email K@2m5.de
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;
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; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/
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; assembled with AS65 written by Frank A. Kingswood
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; The assembler as65_142.zip can be obtained from my GitHub repository
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; command line switches: -l -m -s2 -w -h0
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; | | | | no page headers in listing
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; | | | wide listing (133 char/col)
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@ -76,7 +77,8 @@
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; 04-dec-2017 fixed BRK only tested with interrupts enabled
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; added option to skip the remainder of a failing test
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; in report.i65
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; 05-jan-2020 fixed shifts not testing zero result and flag when last 1-bit
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; is shifted out
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; C O N F I G U R A T I O N
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@ -96,17 +98,17 @@ load_data_direct = 1
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I_flag = 3
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;configure memory - try to stay away from memory used by the system
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;zero_page memory start address, $50 (80) consecutive Bytes required
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;zero_page memory start address, $52 (82) consecutive Bytes required
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; add 2 if I_flag = 2
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zero_page = $a
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;data_segment memory start address, $6A (106) consecutive Bytes required
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;data_segment memory start address, $7B (123) consecutive Bytes required
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data_segment = $200
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if (data_segment & $ff) != 0
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ERROR ERROR ERROR low byte of data_segment MUST be $00 !!
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endif
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;code_segment memory start address, 13kB of consecutive space required
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;code_segment memory start address, 13.1kB of consecutive space required
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; add 2.5 kB if I_flag = 2
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code_segment = $400
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@ -621,7 +623,7 @@ irq_x ds 1 ;x register
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flag_I_on ds 1 ;or mask to load flags
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flag_I_off ds 1 ;and mask to load flags
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endif
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zpt ;5 bytes store/modify test area
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zpt ;6 bytes store/modify test area
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;add/subtract operand generation and result/flag prediction
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adfc ds 1 ;carry flag before op
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ad1 ds 1 ;operand 1 - accumulator
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@ -631,6 +633,7 @@ adrh ds 1 ;expected result bit 8 (carry)
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adrf ds 1 ;expected flags NV0000ZC (only binary mode)
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sb2 ds 1 ;operand 2 complemented for subtract
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zp_bss
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zps db $80,1 ;additional shift pattern to test zero result & flag
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zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
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zp7f db $7f ;test pattern for compare
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;logical zeropage operands
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@ -672,10 +675,10 @@ zp_bss_end
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test_case ds 1 ;current test number
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ram_chksm ds 2 ;checksum for RAM integrity test
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;add/subtract operand copy - abs tests write area
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abst ;5 bytes store/modify test area
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abst ;6 bytes store/modify test area
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ada2 ds 1 ;operand 2
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sba2 ds 1 ;operand 2 complemented for subtract
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ds 3 ;fill remaining bytes
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ds 4 ;fill remaining bytes
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data_bss
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if load_data_direct = 1
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ex_andi and #0 ;execute immediate opcodes
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@ -695,23 +698,24 @@ ex_orai ds 3
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ex_adci ds 3
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ex_sbci ds 3
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endif
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;zps db $80,1 ;additional shift patterns test zero result & flag
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abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
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abs7f db $7f ;test pattern for compare
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;loads
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fLDx db fn,fn,0,fz ;expected flags for load
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;shifts
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rASL ;expected result ASL & ROL -carry
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rROL db $86,$04,$82,0 ; "
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rROLc db $87,$05,$83,1 ;expected result ROL +carry
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rROL db 0,2,$86,$04,$82,0
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rROLc db 1,3,$87,$05,$83,1 ;expected result ROL +carry
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rLSR ;expected result LSR & ROR -carry
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rROR db $61,$41,$20,0 ; "
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rRORc db $e1,$c1,$a0,$80 ;expected result ROR +carry
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rROR db $40,0,$61,$41,$20,0
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rRORc db $c0,$80,$e1,$c1,$a0,$80 ;expected result ROR +carry
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fASL ;expected flags for shifts
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fROL db fnc,fc,fn,fz ;no carry in
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fROLc db fnc,fc,fn,0 ;carry in
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fROL db fzc,0,fnc,fc,fn,fz ;no carry in
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fROLc db fc,0,fnc,fc,fn,0 ;carry in
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fLSR
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fROR db fc,0,fc,fz ;no carry in
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fRORc db fnc,fn,fnc,fn ;carry in
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fROR db 0,fzc,fc,0,fc,fz ;no carry in
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fRORc db fn,fnc,fnc,fn,fnc,fn ;carry in
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;increments (decrements)
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rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC
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fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC
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@ -4070,91 +4074,91 @@ tstay6 lda abst,y
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; testing shifts - ASL LSR ROL ROR all addressing modes
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; shifts - accumulator
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ldx #3
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ldx #5
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tasl
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set_ax zp1,0
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set_ax zps,0
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asl a
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tst_ax rASL,fASL,0
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dex
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bpl tasl
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ldx #3
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ldx #5
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tasl1
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set_ax zp1,$ff
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set_ax zps,$ff
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asl a
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tst_ax rASL,fASL,$ff-fnzc
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dex
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bpl tasl1
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ldx #3
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ldx #5
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tlsr
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set_ax zp1,0
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set_ax zps,0
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lsr a
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tst_ax rLSR,fLSR,0
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dex
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bpl tlsr
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ldx #3
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ldx #5
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tlsr1
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set_ax zp1,$ff
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set_ax zps,$ff
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lsr a
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tst_ax rLSR,fLSR,$ff-fnzc
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dex
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bpl tlsr1
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ldx #3
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ldx #5
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trol
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set_ax zp1,0
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set_ax zps,0
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rol a
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tst_ax rROL,fROL,0
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dex
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bpl trol
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ldx #3
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ldx #5
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trol1
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set_ax zp1,$ff-fc
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set_ax zps,$ff-fc
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rol a
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tst_ax rROL,fROL,$ff-fnzc
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dex
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bpl trol1
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ldx #3
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ldx #5
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trolc
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set_ax zp1,fc
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set_ax zps,fc
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rol a
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tst_ax rROLc,fROLc,0
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dex
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bpl trolc
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ldx #3
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ldx #5
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trolc1
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set_ax zp1,$ff
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set_ax zps,$ff
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rol a
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tst_ax rROLc,fROLc,$ff-fnzc
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dex
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bpl trolc1
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ldx #3
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ldx #5
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tror
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set_ax zp1,0
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set_ax zps,0
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ror a
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tst_ax rROR,fROR,0
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dex
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bpl tror
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ldx #3
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ldx #5
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tror1
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set_ax zp1,$ff-fc
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set_ax zps,$ff-fc
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ror a
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tst_ax rROR,fROR,$ff-fnzc
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dex
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bpl tror1
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ldx #3
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ldx #5
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trorc
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set_ax zp1,fc
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set_ax zps,fc
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ror a
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tst_ax rRORc,fRORc,0
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dex
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bpl trorc
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ldx #3
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ldx #5
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trorc1
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set_ax zp1,$ff
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set_ax zps,$ff
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ror a
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tst_ax rRORc,fRORc,$ff-fnzc
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dex
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@ -4162,91 +4166,91 @@ trorc1
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next_test
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; shifts - zeropage
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ldx #3
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ldx #5
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tasl2
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set_z zp1,0
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set_z zps,0
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asl zpt
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tst_z rASL,fASL,0
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dex
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bpl tasl2
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ldx #3
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ldx #5
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tasl3
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set_z zp1,$ff
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set_z zps,$ff
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asl zpt
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tst_z rASL,fASL,$ff-fnzc
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dex
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bpl tasl3
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ldx #3
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ldx #5
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tlsr2
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set_z zp1,0
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set_z zps,0
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lsr zpt
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tst_z rLSR,fLSR,0
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dex
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bpl tlsr2
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ldx #3
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ldx #5
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tlsr3
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set_z zp1,$ff
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set_z zps,$ff
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lsr zpt
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tst_z rLSR,fLSR,$ff-fnzc
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dex
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bpl tlsr3
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ldx #3
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ldx #5
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trol2
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set_z zp1,0
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set_z zps,0
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rol zpt
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tst_z rROL,fROL,0
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dex
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bpl trol2
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ldx #3
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ldx #5
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trol3
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set_z zp1,$ff-fc
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set_z zps,$ff-fc
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rol zpt
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tst_z rROL,fROL,$ff-fnzc
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dex
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bpl trol3
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ldx #3
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ldx #5
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trolc2
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set_z zp1,fc
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set_z zps,fc
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rol zpt
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tst_z rROLc,fROLc,0
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dex
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bpl trolc2
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ldx #3
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ldx #5
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trolc3
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set_z zp1,$ff
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set_z zps,$ff
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rol zpt
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tst_z rROLc,fROLc,$ff-fnzc
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dex
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bpl trolc3
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ldx #3
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ldx #5
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tror2
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set_z zp1,0
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set_z zps,0
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ror zpt
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tst_z rROR,fROR,0
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dex
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bpl tror2
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ldx #3
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ldx #5
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tror3
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set_z zp1,$ff-fc
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set_z zps,$ff-fc
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ror zpt
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tst_z rROR,fROR,$ff-fnzc
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dex
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bpl tror3
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ldx #3
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ldx #5
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trorc2
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set_z zp1,fc
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set_z zps,fc
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ror zpt
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tst_z rRORc,fRORc,0
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dex
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bpl trorc2
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ldx #3
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ldx #5
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trorc3
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set_z zp1,$ff
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set_z zps,$ff
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ror zpt
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tst_z rRORc,fRORc,$ff-fnzc
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dex
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@ -4254,91 +4258,91 @@ trorc3
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next_test
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; shifts - absolute
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ldx #3
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ldx #5
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tasl4
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set_abs zp1,0
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set_abs zps,0
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asl abst
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tst_abs rASL,fASL,0
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dex
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bpl tasl4
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ldx #3
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ldx #5
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tasl5
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set_abs zp1,$ff
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set_abs zps,$ff
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asl abst
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tst_abs rASL,fASL,$ff-fnzc
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dex
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bpl tasl5
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ldx #3
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ldx #5
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tlsr4
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set_abs zp1,0
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set_abs zps,0
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lsr abst
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tst_abs rLSR,fLSR,0
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dex
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bpl tlsr4
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ldx #3
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ldx #5
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tlsr5
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set_abs zp1,$ff
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set_abs zps,$ff
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lsr abst
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tst_abs rLSR,fLSR,$ff-fnzc
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dex
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bpl tlsr5
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ldx #3
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ldx #5
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trol4
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set_abs zp1,0
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set_abs zps,0
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rol abst
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tst_abs rROL,fROL,0
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dex
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bpl trol4
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ldx #3
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ldx #5
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trol5
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set_abs zp1,$ff-fc
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set_abs zps,$ff-fc
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rol abst
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tst_abs rROL,fROL,$ff-fnzc
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dex
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bpl trol5
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ldx #3
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ldx #5
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trolc4
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set_abs zp1,fc
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set_abs zps,fc
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rol abst
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tst_abs rROLc,fROLc,0
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dex
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bpl trolc4
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ldx #3
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ldx #5
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trolc5
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set_abs zp1,$ff
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set_abs zps,$ff
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rol abst
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tst_abs rROLc,fROLc,$ff-fnzc
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dex
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bpl trolc5
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ldx #3
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ldx #5
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tror4
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set_abs zp1,0
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set_abs zps,0
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ror abst
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tst_abs rROR,fROR,0
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dex
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bpl tror4
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ldx #3
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ldx #5
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tror5
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set_abs zp1,$ff-fc
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set_abs zps,$ff-fc
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ror abst
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tst_abs rROR,fROR,$ff-fnzc
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dex
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bpl tror5
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ldx #3
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ldx #5
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trorc4
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set_abs zp1,fc
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set_abs zps,fc
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ror abst
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tst_abs rRORc,fRORc,0
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dex
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bpl trorc4
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ldx #3
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ldx #5
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trorc5
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set_abs zp1,$ff
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set_abs zps,$ff
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ror abst
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tst_abs rRORc,fRORc,$ff-fnzc
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dex
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@ -4346,91 +4350,91 @@ trorc5
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next_test
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; shifts - zp indexed
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ldx #3
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ldx #5
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tasl6
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set_zx zp1,0
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set_zx zps,0
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asl zpt,x
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tst_zx rASL,fASL,0
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dex
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bpl tasl6
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ldx #3
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ldx #5
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tasl7
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set_zx zp1,$ff
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set_zx zps,$ff
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asl zpt,x
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tst_zx rASL,fASL,$ff-fnzc
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dex
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bpl tasl7
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ldx #3
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ldx #5
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tlsr6
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set_zx zp1,0
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set_zx zps,0
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lsr zpt,x
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tst_zx rLSR,fLSR,0
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dex
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bpl tlsr6
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ldx #3
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ldx #5
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tlsr7
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set_zx zp1,$ff
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set_zx zps,$ff
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lsr zpt,x
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tst_zx rLSR,fLSR,$ff-fnzc
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dex
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bpl tlsr7
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ldx #3
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ldx #5
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trol6
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set_zx zp1,0
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||||
set_zx zps,0
|
||||
rol zpt,x
|
||||
tst_zx rROL,fROL,0
|
||||
dex
|
||||
bpl trol6
|
||||
ldx #3
|
||||
ldx #5
|
||||
trol7
|
||||
set_zx zp1,$ff-fc
|
||||
set_zx zps,$ff-fc
|
||||
rol zpt,x
|
||||
tst_zx rROL,fROL,$ff-fnzc
|
||||
dex
|
||||
bpl trol7
|
||||
|
||||
ldx #3
|
||||
ldx #5
|
||||
trolc6
|
||||
set_zx zp1,fc
|
||||
set_zx zps,fc
|
||||
rol zpt,x
|
||||
tst_zx rROLc,fROLc,0
|
||||
dex
|
||||
bpl trolc6
|
||||
ldx #3
|
||||
ldx #5
|
||||
trolc7
|
||||
set_zx zp1,$ff
|
||||
set_zx zps,$ff
|
||||
rol zpt,x
|
||||
tst_zx rROLc,fROLc,$ff-fnzc
|
||||
dex
|
||||
bpl trolc7
|
||||
|
||||
ldx #3
|
||||
ldx #5
|
||||
tror6
|
||||
set_zx zp1,0
|
||||
set_zx zps,0
|
||||
ror zpt,x
|
||||
tst_zx rROR,fROR,0
|
||||
dex
|
||||
bpl tror6
|
||||
ldx #3
|
||||
ldx #5
|
||||
tror7
|
||||
set_zx zp1,$ff-fc
|
||||
set_zx zps,$ff-fc
|
||||
ror zpt,x
|
||||
tst_zx rROR,fROR,$ff-fnzc
|
||||
dex
|
||||
bpl tror7
|
||||
|
||||
ldx #3
|
||||
ldx #5
|
||||
trorc6
|
||||
set_zx zp1,fc
|
||||
set_zx zps,fc
|
||||
ror zpt,x
|
||||
tst_zx rRORc,fRORc,0
|
||||
dex
|
||||
bpl trorc6
|
||||
ldx #3
|
||||
ldx #5
|
||||
trorc7
|
||||
set_zx zp1,$ff
|
||||
set_zx zps,$ff
|
||||
ror zpt,x
|
||||
tst_zx rRORc,fRORc,$ff-fnzc
|
||||
dex
|
||||
@ -4438,91 +4442,91 @@ trorc7
|
||||
next_test
|
||||
|
||||
; shifts - abs indexed
|
||||
ldx #3
|
||||
ldx #5
|
||||
tasl8
|
||||
set_absx zp1,0
|
||||
set_absx zps,0
|
||||
asl abst,x
|
||||
tst_absx rASL,fASL,0
|
||||
dex
|
||||
bpl tasl8
|
||||
ldx #3
|
||||
ldx #5
|
||||
tasl9
|
||||
set_absx zp1,$ff
|
||||
set_absx zps,$ff
|
||||
asl abst,x
|
||||
tst_absx rASL,fASL,$ff-fnzc
|
||||
dex
|
||||
bpl tasl9
|
||||
|
||||
ldx #3
|
||||
ldx #5
|
||||
tlsr8
|
||||
set_absx zp1,0
|
||||
set_absx zps,0
|
||||
lsr abst,x
|
||||
tst_absx rLSR,fLSR,0
|
||||
dex
|
||||
bpl tlsr8
|
||||
ldx #3
|
||||
ldx #5
|
||||
tlsr9
|
||||
set_absx zp1,$ff
|
||||
set_absx zps,$ff
|
||||
lsr abst,x
|
||||
tst_absx rLSR,fLSR,$ff-fnzc
|
||||
dex
|
||||
bpl tlsr9
|
||||
|
||||
ldx #3
|
||||
ldx #5
|
||||
trol8
|
||||
set_absx zp1,0
|
||||
set_absx zps,0
|
||||
rol abst,x
|
||||
tst_absx rROL,fROL,0
|
||||
dex
|
||||
bpl trol8
|
||||
ldx #3
|
||||
ldx #5
|
||||
trol9
|
||||
set_absx zp1,$ff-fc
|
||||
set_absx zps,$ff-fc
|
||||
rol abst,x
|
||||
tst_absx rROL,fROL,$ff-fnzc
|
||||
dex
|
||||
bpl trol9
|
||||
|
||||
ldx #3
|
||||
ldx #5
|
||||
trolc8
|
||||
set_absx zp1,fc
|
||||
set_absx zps,fc
|
||||
rol abst,x
|
||||
tst_absx rROLc,fROLc,0
|
||||
dex
|
||||
bpl trolc8
|
||||
ldx #3
|
||||
ldx #5
|
||||
trolc9
|
||||
set_absx zp1,$ff
|
||||
set_absx zps,$ff
|
||||
rol abst,x
|
||||
tst_absx rROLc,fROLc,$ff-fnzc
|
||||
dex
|
||||
bpl trolc9
|
||||
|
||||
ldx #3
|
||||
ldx #5
|
||||
tror8
|
||||
set_absx zp1,0
|
||||
set_absx zps,0
|
||||
ror abst,x
|
||||
tst_absx rROR,fROR,0
|
||||
dex
|
||||
bpl tror8
|
||||
ldx #3
|
||||
ldx #5
|
||||
tror9
|
||||
set_absx zp1,$ff-fc
|
||||
set_absx zps,$ff-fc
|
||||
ror abst,x
|
||||
tst_absx rROR,fROR,$ff-fnzc
|
||||
dex
|
||||
bpl tror9
|
||||
|
||||
ldx #3
|
||||
ldx #5
|
||||
trorc8
|
||||
set_absx zp1,fc
|
||||
set_absx zps,fc
|
||||
ror abst,x
|
||||
tst_absx rRORc,fRORc,0
|
||||
dex
|
||||
bpl trorc8
|
||||
ldx #3
|
||||
ldx #5
|
||||
trorc9
|
||||
set_absx zp1,$ff
|
||||
set_absx zps,$ff
|
||||
ror abst,x
|
||||
tst_absx rRORc,fRORc,$ff-fnzc
|
||||
dex
|
||||
@ -5997,6 +6001,7 @@ break2 ;BRK pass 2
|
||||
;copy of data to initialize BSS segment
|
||||
if load_data_direct != 1
|
||||
zp_init
|
||||
zps_ db $80,1 ;additional shift pattern to test zero result & flag
|
||||
zp1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
|
||||
zp7f_ db $7f ;test pattern for compare
|
||||
;logical zeropage operands
|
||||
@ -6048,23 +6053,24 @@ ex_adc_ adc #0 ;execute immediate opcodes
|
||||
rts
|
||||
ex_sbc_ sbc #0 ;execute immediate opcodes
|
||||
rts
|
||||
;zps db $80,1 ;additional shift patterns test zero result & flag
|
||||
abs1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
|
||||
abs7f_ db $7f ;test pattern for compare
|
||||
;loads
|
||||
fLDx_ db fn,fn,0,fz ;expected flags for load
|
||||
;shifts
|
||||
rASL_ ;expected result ASL & ROL -carry
|
||||
rROL_ db $86,$04,$82,0 ; "
|
||||
rROLc_ db $87,$05,$83,1 ;expected result ROL +carry
|
||||
rROL_ db 0,2,$86,$04,$82,0
|
||||
rROLc_ db 1,3,$87,$05,$83,1 ;expected result ROL +carry
|
||||
rLSR_ ;expected result LSR & ROR -carry
|
||||
rROR_ db $61,$41,$20,0 ; "
|
||||
rRORc_ db $e1,$c1,$a0,$80 ;expected result ROR +carry
|
||||
rROR_ db $40,0,$61,$41,$20,0
|
||||
rRORc_ db $c0,$80,$e1,$c1,$a0,$80 ;expected result ROR +carry
|
||||
fASL_ ;expected flags for shifts
|
||||
fROL_ db fnc,fc,fn,fz ;no carry in
|
||||
fROLc_ db fnc,fc,fn,0 ;carry in
|
||||
fROL_ db fzc,0,fnc,fc,fn,fz ;no carry in
|
||||
fROLc_ db fc,0,fnc,fc,fn,0 ;carry in
|
||||
fLSR_
|
||||
fROR_ db fc,0,fc,fz ;no carry in
|
||||
fRORc_ db fnc,fn,fnc,fn ;carry in
|
||||
fROR_ db 0,fzc,fc,0,fc,fz ;no carry in
|
||||
fRORc_ db fn,fnc,fnc,fn,fnc,fn ;carry in
|
||||
;increments (decrements)
|
||||
rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC
|
||||
fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC
|
||||
|
BIN
as65_142.zip
Normal file
BIN
as65_142.zip
Normal file
Binary file not shown.
12
readme.txt
12
readme.txt
@ -10,14 +10,18 @@ The 6502_interrupt_test.a65 is a simple test to check the interrupt system
|
||||
of both processors. A feedback register is required to inject IRQ and NMI
|
||||
requests.
|
||||
|
||||
The 6502_decimal_test.a65 is Bruce Clark's code to accurately test decimal mode
|
||||
of the various 6502 cores (6502, 65c02 & 65816 in 8-bit mode) with added
|
||||
configuration options (invalid bcd or not, which flags to ignore).
|
||||
|
||||
Detailed information about how to configure, assemble and run the tests is
|
||||
included in each source file.
|
||||
|
||||
The tests have primarily been written to test my own ATMega16 6502 emulator
|
||||
project. You can find it here: http://2m5.de/6502_Emu/index.htm
|
||||
The assembler used is no longer available on the author's website. as65_142.zip
|
||||
is now included in this repository.
|
||||
|
||||
A discussion about the tests can be found here:
|
||||
http://forum.6502.org/viewtopic.php?f=2&t=2241
|
||||
And no, I will not switch to another assembler. However, GitHub user amb5l has
|
||||
a CA65 compatible version in his repository.
|
||||
|
||||
Good luck debugging your emulator, simulator, fpga core, discrete
|
||||
logic implementation or whatever you have!
|
||||
|
Loading…
Reference in New Issue
Block a user