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https://github.com/fadden/6502bench.git
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81 lines
1.8 KiB
ArmAsm
81 lines
1.8 KiB
ArmAsm
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; Copyright 2020 faddenSoft. All Rights Reserved.
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; See the LICENSE.txt file for distribution terms (Apache 2.0).
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;
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; Assembler: Merlin 32
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;
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; Segment #1 : code; main segment, loads anywhere
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BANK2_START EXT
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BANK2_MOV_DST EXT
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BANK8_START EXT
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BANK8_ADDR EXT
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BANK8_MOV_SRC EXT
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ADDR_FFE0 EXT
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REL ;generate relocatable code
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start
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clc
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xce
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sep #$30
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mx %11
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ldal start
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nop
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jsl BANK2_START
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jsl BANK8_START
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ldal BANK2_START
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lda BANK2_START
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lda #<BANK2_START
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lda #>BANK2_START
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lda #^BANK2_START
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ldal BANK8_ADDR
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lda BANK8_ADDR
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lda #<BANK8_ADDR
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lda #>BANK8_ADDR
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lda #^BANK8_ADDR
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nop
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; Do some stuff with 16-bit registers. Merlin 32 treats <>^ as shift
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; operations rather than byte selectors.
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rep #$30
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mx %00
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lda #<BANK8_ADDR
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lda #>BANK8_ADDR
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lda #^BANK8_ADDR
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nop
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; Check MVN/MVP. Handing them correctly requires having two different
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; symbol refs on a single instruction.
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lda #15
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ldx #BANK8_MOV_SRC
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ldy #BANK2_MOV_DST
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mvn #^BANK8_MOV_SRC,#^BANK2_MOV_DST
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nop
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check_pea
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pea $0000
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pea $f000
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pea BANK8_ADDR
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pea ^BANK8_ADDR
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pea check_pea
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pea >check_pea
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pea ^check_pea
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pea check_pea+18
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pea check_pea+$1000
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nop
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jmp :skipdata
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; Generate 2/3/4-byte refs. The OMF reloc entry generated by Merlin32
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; for ADRL is only 3 bytes wide.
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dw ADDR_FFE0
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adr ADDR_FFE0
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adrl ADDR_FFE0
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:skipdata
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rts
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