1
0
mirror of https://github.com/fadden/6502bench.git synced 2025-11-05 16:17:24 +00:00

Add Data Bank Register management, part 1

On the 65816, 16-bit data access instructions (e.g. LDA abs) are
expanded to 24 bits by merging in the Data Bank Register (B).  The
value of the register is difficult to determine via static analysis,
so we need a way to annotate the disassembly with the correct value.
Without this, the mapping of address to file offset will sometimes
be incorrect.

This change adds the basic data structures and "fixup" function, a
functional but incomplete editor, and source for a new test case.
This commit is contained in:
Andy McFadden
2020-07-08 17:56:27 -07:00
parent 44522dc2f2
commit 18e6951f17
15 changed files with 590 additions and 22 deletions

View File

@@ -36,6 +36,8 @@ namespace SourceGen {
InlineData = 1 << 2, // byte is inline data
Data = 1 << 3, // byte is data
UsesDataBankReg = 1 << 4, // operand value should be merged with DBR
EntryPoint = 1 << 8, // external code branches here
BranchTarget = 1 << 9, // internal code branches here
ExternalBranch = 1 << 10, // this abs/rel branch lands outside input file
@@ -113,6 +115,18 @@ namespace SourceGen {
return IsInstructionStart || IsDataStart || IsInlineDataStart;
}
}
public bool UsesDataBankReg {
get {
return (mAttribFlags & AttribFlags.UsesDataBankReg) != 0;
}
set {
if (value) {
mAttribFlags |= AttribFlags.UsesDataBankReg;
} else {
mAttribFlags &= ~AttribFlags.UsesDataBankReg;
}
}
}
public bool IsEntryPoint {
get {
return (mAttribFlags & AttribFlags.EntryPoint) != 0;