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Add W65C02S support, part 3

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Modified the asm source generators and on-screen display to show the
DP arg for BBR/BBS as hex.  The instructions are otherwise treated
as relative branches, e.g. the DP arg doesn't get factored into the
cross-reference table.

ACME/cc65 put the bit number in the mnemonic, 64tass wants it to be
in the first argument, and Merlin32 wants nothing to do with any of
this because it's incompatible with the 65816.

Added an "all ops" test for W65C02.
This commit is contained in:
Andy McFadden 2020-10-11 14:35:17 -07:00
parent 70ee8793ae
commit 34ba47e71d
25 changed files with 2355 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Asm65/Formatter.cs
View File

@ -805,7 +805,7 @@ namespace Asm65 {
case AddressMode.BlockMove:
case AddressMode.StackAbs:
case AddressMode.DP:
case AddressMode.DPPCRel:
case AddressMode.DPPCRel: // BBR/BBS
case AddressMode.PCRel:
case AddressMode.PCRelLong: // BRL
case AddressMode.StackInt: // COP and two-byte BRK

14
Asm65/OpDef.cs
View File

@ -206,6 +206,11 @@ namespace Asm65 {
public int Cycles { get { return CycDef & 0xff; } }
public CycleMod CycleMods { get { return (CycleMod)(CycDef & ~0xff); } }
/// <summary>
/// True if this is a numbered bit operation, i.e. BBR/BBS/RMB/SMB on the W65C02.
/// </summary>
public bool IsNumberedBitOp { get; private set; }
/// <summary>
/// True if the instruction's address mode is a direct page access.
/// </summary>
@ -221,6 +226,7 @@ namespace Asm65 {
case AddressMode.DPIndIndexYLong:
case AddressMode.DPIndLong:
case AddressMode.StackDPInd:
// not currently handling DPPCRel as DP
return true;
default:
return false;
@ -347,6 +353,7 @@ namespace Asm65 {
this.Opcode = src.Opcode;
this.AddrMode = src.AddrMode;
this.IsUndocumented = src.IsUndocumented;
this.IsNumberedBitOp = src.IsNumberedBitOp;
this.Mnemonic = src.Mnemonic;
this.FlagsAffected = src.FlagsAffected;
this.Effect = src.Effect;
@ -578,7 +585,8 @@ namespace Asm65 {
}
/// <summary>
/// Determines if a conditional branch is always taken, based on the status flags.
/// Determines if a conditional branch is always taken, based on the status flags. Only
/// call here for branch instructions.
/// </summary>
/// <param name="op">Conditional branch instruction.</param>
/// <param name="flags">Processor status flags.</param>
@ -3559,21 +3567,25 @@ namespace Asm65 {
//
private static OpDef OpBBR = new OpDef() {
IsNumberedBitOp = true,
Mnemonic = "???",
Effect = FlowEffect.ConditionalBranch,
BaseMemEffect = MemoryEffect.None
};
private static OpDef OpBBS = new OpDef() {
IsNumberedBitOp = true,
Mnemonic = "???",
Effect = FlowEffect.ConditionalBranch,
BaseMemEffect = MemoryEffect.None
};
private static OpDef OpRMB = new OpDef() {
IsNumberedBitOp = true,
Mnemonic = "???",
Effect = FlowEffect.Cont,
BaseMemEffect = MemoryEffect.ReadModifyWrite
};
private static OpDef OpSMB = new OpDef() {
IsNumberedBitOp = true,
Mnemonic = "???",
Effect = FlowEffect.Cont,
BaseMemEffect = MemoryEffect.ReadModifyWrite

5
SourceGen/AsmGen/AsmAcme.cs
View File

@ -283,6 +283,8 @@ namespace SourceGen.AsmGen {
cpuStr = "65816";
} else if (cpuDef.Type == CpuDef.CpuType.Cpu65C02) {
cpuStr = "65c02";
} else if (cpuDef.Type == CpuDef.CpuType.CpuW65C02) {
cpuStr = "w65c02";
} else if (cpuDef.Type == CpuDef.CpuType.Cpu6502 && cpuDef.HasUndocumented) {
cpuStr = "6510";
} else {
@ -295,7 +297,8 @@ namespace SourceGen.AsmGen {
// IGenerator
public string ModifyOpcode(int offset, OpDef op) {
if (op.IsUndocumented) {
if (Project.CpuDef.Type == CpuDef.CpuType.Cpu65C02) {
if (Project.CpuDef.Type == CpuDef.CpuType.Cpu65C02 ||
Project.CpuDef.Type == CpuDef.CpuType.CpuW65C02) {
// none of the "LDD" stuff is handled
return null;
}

3
SourceGen/AsmGen/AsmCc65.cs
View File

@ -283,7 +283,8 @@ namespace SourceGen.AsmGen {
string cpuStr;
if (cpuDef.Type == CpuDef.CpuType.Cpu65816) {
cpuStr = "65816";
} else if (cpuDef.Type == CpuDef.CpuType.Cpu65C02) {
} else if (cpuDef.Type == CpuDef.CpuType.Cpu65C02 ||
cpuDef.Type == CpuDef.CpuType.CpuW65C02) {
cpuStr = "65C02";
} else if (cpuDef.Type == CpuDef.CpuType.Cpu6502 && cpuDef.HasUndocumented) {
cpuStr = "6502X";

6
SourceGen/AsmGen/AsmMerlin32.cs
View File

@ -380,6 +380,12 @@ namespace SourceGen.AsmGen {
if (op.IsUndocumented) {
return null;
}
if (Project.CpuDef.Type == CpuDef.CpuType.CpuW65C02) {
if ((op.Opcode & 0x0f) == 0x07 || (op.Opcode & 0x0f) == 0x0f) {
// BBR, BBS, RMB, SMB not supported
return null;
}
}
// The assembler works correctly if the symbol is defined as a two-digit hex
// value (e.g. "foo equ $80") but fails if it's four (e.g. "foo equ $0080"). We

6
SourceGen/AsmGen/AsmTass64.cs
View File

@ -165,6 +165,7 @@ namespace SourceGen.AsmGen {
Quirks.StackIntOperandIsImmediate = true;
Quirks.LeadingUnderscoreSpecial = true;
Quirks.Need24BitsForAbsPBR = true;
Quirks.BitNumberIsArg = true;
mWorkDirectory = workDirectory;
mFileNameBase = fileNameBase;
@ -267,6 +268,8 @@ namespace SourceGen.AsmGen {
cpuStr = "65816";
} else if (cpuDef.Type == CpuDef.CpuType.Cpu65C02) {
cpuStr = "65c02";
} else if (cpuDef.Type == CpuDef.CpuType.CpuW65C02) {
cpuStr = "w65c02";
} else if (cpuDef.Type == CpuDef.CpuType.Cpu6502 && cpuDef.HasUndocumented) {
cpuStr = "6502i";
} else {
@ -330,7 +333,8 @@ namespace SourceGen.AsmGen {
// IGenerator
public string ModifyOpcode(int offset, OpDef op) {
if (op.IsUndocumented) {
if (Project.CpuDef.Type == CpuDef.CpuType.Cpu65C02) {
if (Project.CpuDef.Type == CpuDef.CpuType.Cpu65C02 ||
Project.CpuDef.Type == CpuDef.CpuType.CpuW65C02) {
// none of the "LDD" stuff is handled
return null;
}

23
SourceGen/AsmGen/GenCommon.cs
View File

@ -220,7 +220,8 @@ namespace SourceGen.AsmGen {
// Tweak branch instructions. We want to show the absolute address rather
// than the relative offset (which happens with the OperandAddress assignment
// below), and 1-byte branches should always appear as a 4-byte hex value.
if (op.AddrMode == OpDef.AddressMode.PCRel) {
if (op.AddrMode == OpDef.AddressMode.PCRel ||
op.AddrMode == OpDef.AddressMode.DPPCRel) {
Debug.Assert(attr.OperandAddress >= 0);
operandLen = 2;
opFlags |= PseudoOp.FormatNumericOpFlags.IsPcRel;
@ -269,6 +270,14 @@ namespace SourceGen.AsmGen {
}
string hash = gen.Quirks.BlockMoveArgsNoHash ? "" : "#";
formattedOperand = hash + opstr1 + "," + hash + opstr2;
} else if (op.AddrMode == OpDef.AddressMode.DPPCRel) {
// Special handling for double-operand BBR/BBS. The instruction generally
// behaves like a branch, so format that first.
string branchStr = PseudoOp.FormatNumericOperand(formatter,
proj.SymbolTable, gen.Localizer.LabelMap, dfd,
operandForSymbol, operandLen, opFlags);
string dpStr = formatter.FormatHexValue(operand & 0xff, 2);
formattedOperand = dpStr + "," + branchStr;
} else {
if (attr.DataDescriptor.IsStringOrCharacter) {
gen.UpdateCharacterEncoding(dfd);
@ -291,6 +300,9 @@ namespace SourceGen.AsmGen {
string hash = gen.Quirks.BlockMoveArgsNoHash ? "" : "#";
formattedOperand = hash + formatter.FormatHexValue(arg1, 2) + "," +
hash + formatter.FormatHexValue(arg2, 2);
} else if (op.AddrMode == OpDef.AddressMode.DPPCRel) {
formattedOperand = formatter.FormatHexValue(operand & 0xff, 2) + "," +
formatter.FormatHexValue(operandForSymbol, operandLen * 2);
} else {
if (operandLen == 2 && !(op.IsAbsolutePBR && gen.Quirks.Need24BitsForAbsPBR)) {
// This is necessary for 16-bit operands, like "LDA abs" and "PEA val",
@ -309,6 +321,15 @@ namespace SourceGen.AsmGen {
operandStr = '#' + operandStr;
}
// The BBR/BBS/RMB/SMB instructions include a bit index (0-7). The standard way is
// to make it part of the mnemonic, but some assemblers make it an argument.
if (gen.Quirks.BitNumberIsArg && op.IsNumberedBitOp) {
// Easy way: do some string manipulation.
char bitIndex = opcodeStr[opcodeStr.Length - 1];
opcodeStr = opcodeStr.Substring(0, opcodeStr.Length - 1);
operandStr = bitIndex.ToString() + "," + operandStr;
}
string eolComment = proj.Comments[offset];
if (doAddCycles) {
bool branchCross = (attr.Address & 0xff00) != (operandForSymbol & 0xff00);

26
SourceGen/AsmGen/IGenerator.cs
View File

@ -202,9 +202,10 @@ namespace SourceGen.AsmGen {
/// </summary>
public class AssemblerQuirks {
/// <summary>
/// Does a leading underscore in a label have a special meaning? (e.g. 64tass)
/// Does the assembler expect the bit index for BBR/BBS/RMB/SMB to be expressed as
/// a separate argument?
/// </summary>
public bool LeadingUnderscoreSpecial { get; set; }
public bool BitNumberIsArg { get; set; }
/// <summary>
/// Are 8-bit constant args to MVN/MVP output without a leading '#'?
@ -216,18 +217,17 @@ namespace SourceGen.AsmGen {
/// </summary>
public bool BlockMoveArgsReversed { get; set; }
/// <summary>
/// Does a leading underscore in a label have a special meaning? (e.g. 64tass)
/// </summary>
public bool LeadingUnderscoreSpecial { get; set; }
/// <summary>
/// Do we need to specify a 24-bit value for 16-bit absolute arguments that are
/// formed with the Program Bank Register (JMP/JSR)?
/// </summary>
public bool Need24BitsForAbsPBR { get; set; }
/// <summary>
/// Does the assembler support a type of label whose value can be redefined to
/// act as a local variable?
/// </summary>
public bool NoRedefinableSymbols { get; set; }
/// <summary>
/// Is the assembler unable to generate relative branches that wrap around banks?
/// (Note this affects long-distance BRLs that don't appear to wrap.)
@ -235,9 +235,10 @@ namespace SourceGen.AsmGen {
public bool NoPcRelBankWrap { get; set; }
/// <summary>
/// Do 8-bit constant args to StackInt ops (BRK/COP) require a leading '#'?
/// Does the assembler support a type of label whose value can be redefined to
/// act as a local variable?
/// </summary>
public bool StackIntOperandIsImmediate { get; set; }
public bool NoRedefinableSymbols { get; set; }
/// <summary>
/// Is the assembler implemented as a single pass? (e.g. cc65)
@ -250,6 +251,11 @@ namespace SourceGen.AsmGen {
/// </summary>
public bool SinglePassNoLabelCorrection { get; set; }
/// <summary>
/// Do 8-bit constant args to StackInt ops (BRK/COP) require a leading '#'?
/// </summary>
public bool StackIntOperandIsImmediate { get; set; }
/// <summary>
/// Does the assembler configure assembler widths based on SEP/REP, but doesn't
/// track the emulation bit?

10
SourceGen/CodeAnalysis.cs
View File

@ -941,6 +941,13 @@ namespace SourceGen {
Asm65.Helper.RelOffset8(mAnattribs[offset].Address,
(sbyte)operand) | bank;
break;
case OpDef.AddressMode.DPPCRel:
// Like PCRel, but part of a 2-byte operand, so we use the 16-bit offset
// function. We totally ignore the DP byte.
mAnattribs[offset].OperandAddress =
Asm65.Helper.RelOffset16(mAnattribs[offset].Address,
(sbyte)(operand << 8)) | bank;
break;
case OpDef.AddressMode.PCRelLong:
case OpDef.AddressMode.StackPCRelLong:
mAnattribs[offset].OperandAddress =
@ -950,7 +957,7 @@ namespace SourceGen {
default:
// Immediate, implied, accumulator, stack relative. We can't do
// immediate yet because we won't necessarily have a final assessment
// of the operand width.
// of the operand width on the 16-bit CPUs.
Debug.Assert(mAnattribs[offset].OperandAddress == -1);
break;
}
@ -969,6 +976,7 @@ namespace SourceGen {
case OpDef.AddressMode.Abs:
case OpDef.AddressMode.AbsLong:
case OpDef.AddressMode.DP:
case OpDef.AddressMode.DPPCRel:
case OpDef.AddressMode.PCRel:
case OpDef.AddressMode.PCRelLong:
case OpDef.AddressMode.StackPCRelLong:

14
SourceGen/LineListGen.cs
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@ -1265,7 +1265,8 @@ namespace SourceGen {
// Tweak branch instructions. We want to show the absolute address rather
// than the relative offset (which happens with the OperandAddress assignment
// below), and 1-byte branches should always appear as a 4-byte hex value.
if (op.AddrMode == OpDef.AddressMode.PCRel) {
if (op.AddrMode == OpDef.AddressMode.PCRel ||
op.AddrMode == OpDef.AddressMode.DPPCRel) {
Debug.Assert(attr.OperandAddress >= 0);
operandLen = 2;
opFlags = PseudoOp.FormatNumericOpFlags.IsPcRel;
@ -1304,6 +1305,14 @@ namespace SourceGen {
null, attr.DataDescriptor, operand & 0xff, 1,
PseudoOp.FormatNumericOpFlags.None);
formattedOperand = '#' + opstr1 + "," + '#' + opstr2;
} else if (op.AddrMode == OpDef.AddressMode.DPPCRel) {
// Special handling for double-operand BBR/BBS. The instruction generally
// behaves like a branch, so format that first.
string branchStr = PseudoOp.FormatNumericOperand(mFormatter,
mProject.SymbolTable, mLvLookup, null, attr.DataDescriptor, offset,
operandForSymbol, operandLen, opFlags);
string dpStr = mFormatter.FormatHexValue(operand & 0xff, 2);
formattedOperand = dpStr + "," + branchStr;
} else {
formattedOperand = PseudoOp.FormatNumericOperand(mFormatter,
mProject.SymbolTable, mLvLookup, null, attr.DataDescriptor, offset,
@ -1314,6 +1323,9 @@ namespace SourceGen {
if (op.AddrMode == OpDef.AddressMode.BlockMove) {
formattedOperand = '#' + mFormatter.FormatHexValue(operand >> 8, 2) + "," +
'#' + mFormatter.FormatHexValue(operand & 0xff, 2);
} else if (op.AddrMode == OpDef.AddressMode.DPPCRel) {
formattedOperand = mFormatter.FormatHexValue(operand & 0xff, 2) + "," +
mFormatter.FormatHexValue(operandForSymbol, operandLen * 2);
} else {
if (operandLen == 2) {
// This is necessary for 16-bit operands, like "LDA abs" and "PEA val",

4
SourceGen/RuntimeData/Help/editors.html
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@ -103,6 +103,10 @@ SourceGen currently only allows you to set one format, which will be
applied to both operands. If you specify a symbol, the symbol will
be used twice, adjusted if necessary. (This limitation may be addressed
in a future release.)</p>
<p>The <code>BBR</code> and <code>BBS</code> instructions on the W65C02
also have two operands: a direct page address, and a relative branch.
In general the direct page address is ignored, so these are treated as
branch instructions.</p>
<p>The bottom part of the window has some shortcuts for working with
address references and local variables. These are primarily used to

BIN
SourceGen/SGTestData/10003-allops-value-W65C02 Normal file
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BIN
SourceGen/SGTestData/10013-allops-zero-W65C02 Normal file
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279
SourceGen/SGTestData/Expected/10003-allops-value-W65C02_64tass.S Normal file
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@ -0,0 +1,279 @@
.cpu "w65c02"
* = $1000
jsr L1017
jsr L1099
jsr L10D9
jsr L10EE
jsr L110F
jsr L11CF
nop
nop
nop
brk
.byte $ff
L1017 ora ($ff,x)
.byte $02,$ff
.byte $03
tsb $ff
ora $ff
asl $ff
rmb 0,$ff
php
ora #$ff
asl a
.byte $0b
tsb $feff
ora $feff
asl $feff
bbr 0,$ff,_L1035
_L1035 bpl _L1037
_L1037 ora ($ff),y
ora ($ff)
.byte $13
trb $ff
ora $ff,x
asl $ff,x
rmb 1,$ff
clc
ora $feff,y
inc a
.byte $1b
trb $feff
ora $feff,x
asl $feff,x
bbr 1,$ff,_L1056
_L1056 jsr $feff
and ($ff,x)
.byte $22,$ff
.byte $23
bit $ff
and $ff
rol $ff
rmb 2,$ff
plp
and #$ff
rol a
.byte $2b
bit $feff
and $feff
rol $feff
bbr 2,$ff,_L1077
_L1077 bmi _L1079
_L1079 and ($ff),y
and ($ff)
.byte $33
bit $ff,x
and $ff,x
rol $ff,x
rmb 3,$ff
sec
and $feff,y
dec a
.byte $3b
bit $feff,x
and $feff,x
rol $feff,x
bbr 3,$ff,_L1098
_L1098 rti
L1099 eor ($ff,x)
.byte $42,$ff
.byte $43
.byte $44,$ff
eor $ff
lsr $ff
rmb 4,$ff
pha
eor #$ff
lsr a
.byte $4b
jmp _L10AE
_L10AE eor $feff
lsr $feff
bbr 4,$ff,_L10B7
_L10B7 bvc _L10B9
_L10B9 eor ($ff),y
eor ($ff)
.byte $53
.byte $54,$ff
eor $ff,x
lsr $ff,x
rmb 5,$ff
cli
eor $feff,y
phy
.byte $5b
.byte $5c,$ff,$fe
eor $feff,x
lsr $feff,x
bbr 5,$ff,_L10D8
_L10D8 rts
L10D9 adc ($ff,x)
.byte $62,$ff
.byte $63
stz $ff
adc $ff
ror $ff
rmb 6,$ff
pla
adc #$ff
ror a
.byte $6b
jmp ($feff)
L10EE adc $feff
ror $feff
bbr 6,$ff,_L10F7
_L10F7 bvs _L10F9
_L10F9 adc ($ff),y
adc ($ff)
.byte $73
stz $ff,x
adc $ff,x
ror $ff,x
rmb 7,$ff
sei
adc $feff,y
ply
.byte $7b
jmp ($feff,x)
L110F adc $feff,x
ror $feff,x
bbr 7,$ff,_L1118
_L1118 bra _L111A
_L111A sta ($ff,x)
.byte $82,$ff
.byte $83
sty $ff
sta $ff
stx $ff
smb 0,$ff
dey
bit #$ff
txa
.byte $8b
sty $feff
sta $feff
stx $feff
bbs 0,$ff,_L1138
_L1138 bcc _L113A
_L113A sta ($ff),y
sta ($ff)
.byte $93
sty $ff,x
sta $ff,x
stx $ff,y
smb 1,$ff
tya
sta $feff,y
txs
.byte $9b
stz $feff
sta $feff,x
stz $feff,x
bbs 1,$ff,_L1159
_L1159 ldy #$ff
lda ($ff,x)
ldx #$ff
.byte $a3
ldy $ff
lda $ff
ldx $ff
smb 2,$ff
tay
lda #$ff
tax
.byte $ab
ldy $feff
lda $feff
ldx $feff
bbs 2,$ff,_L1179
_L1179 bcs _L117B
_L117B lda ($ff),y
lda ($ff)
.byte $b3
ldy $ff,x
lda $ff,x
ldx $ff,y
smb 3,$ff
clv
lda $feff,y
tsx
.byte $bb
ldy $feff,x
lda $feff,x
ldx $feff,y
bbs 3,$ff,_L119A
_L119A cpy #$ff
cmp ($ff,x)
.byte $c2,$ff
.byte $c3
cpy $ff
cmp $ff
dec $ff
smb 4,$ff
iny
cmp #$ff
dex
wai
cpy $feff
cmp $feff
dec $feff
bbs 4,$ff,_L11BA
_L11BA bne _L11BC
_L11BC cmp ($ff),y
cmp ($ff)
.byte $d3
.byte $d4,$ff
cmp $ff,x
dec $ff,x
smb 5,$ff
cld
cmp $feff,y
phx
stp
L11CF .byte $dc,$ff,$fe
cmp $feff,x
dec $feff,x
bbs 5,$ff,_L11DB
_L11DB cpx #$ff
sbc ($ff,x)
.byte $e2,$ff
.byte $e3
cpx $ff
sbc $ff
inc $ff
smb 6,$ff
inx
sbc #$ff
nop
.byte $eb
cpx $feff
sbc $feff
inc $feff
bbs 6,$ff,_L11FB
_L11FB beq _L11FD
_L11FD sbc ($ff),y
sbc ($ff)
.byte $f3
.byte $f4,$ff
sbc $ff,x
inc $ff,x
smb 7,$ff
sed
sbc $feff,y
plx
.byte $fb
.byte $fc,$ff,$fe
sbc $feff,x
inc $feff,x
bbs 7,$ff,_L121C
_L121C rts

278
SourceGen/SGTestData/Expected/10003-allops-value-W65C02_Merlin32.S Normal file
View File

@ -0,0 +1,278 @@
org $1000
jsr L1017
jsr L1099
jsr L10D9
jsr L10EE
jsr L110F
jsr L11CF
nop
nop
nop
brk
dfb $ff
L1017 ora ($ff,x)
dfb $02,$ff
dfb $03
tsb $ff
ora $ff
asl $ff
dfb $07,$ff
php
ora #$ff
asl A
dfb $0b
tsb $feff
ora $feff
asl $feff
dfb $0f,$ff,$00
:L1035 bpl :L1037
:L1037 ora ($ff),y
ora ($ff)
dfb $13
trb $ff
ora $ff,x
asl $ff,x
dfb $17,$ff
clc
ora $feff,y
inc A
dfb $1b
trb $feff
ora $feff,x
asl $feff,x
dfb $1f,$ff,$00
:L1056 jsr $feff
and ($ff,x)
dfb $22,$ff
dfb $23
bit $ff
and $ff
rol $ff
dfb $27,$ff
plp
and #$ff
rol A
dfb $2b
bit $feff
and $feff
rol $feff
dfb $2f,$ff,$00
:L1077 bmi :L1079
:L1079 and ($ff),y
and ($ff)
dfb $33
bit $ff,x
and $ff,x
rol $ff,x
dfb $37,$ff
sec
and $feff,y
dec A
dfb $3b
bit $feff,x
and $feff,x
rol $feff,x
dfb $3f,$ff,$00
:L1098 rti
L1099 eor ($ff,x)
dfb $42,$ff
dfb $43
dfb $44,$ff
eor $ff
lsr $ff
dfb $47,$ff
pha
eor #$ff
lsr A
dfb $4b
jmp :L10AE
:L10AE eor $feff
lsr $feff
dfb $4f,$ff,$00
:L10B7 bvc :L10B9
:L10B9 eor ($ff),y
eor ($ff)
dfb $53
dfb $54,$ff
eor $ff,x
lsr $ff,x
dfb $57,$ff
cli
eor $feff,y
phy
dfb $5b
dfb $5c,$ff,$fe
eor $feff,x
lsr $feff,x
dfb $5f,$ff,$00
:L10D8 rts
L10D9 adc ($ff,x)
dfb $62,$ff
dfb $63
stz $ff
adc $ff
ror $ff
dfb $67,$ff
pla
adc #$ff
ror A
dfb $6b
jmp ($feff)
L10EE adc $feff
ror $feff
dfb $6f,$ff,$00
:L10F7 bvs :L10F9
:L10F9 adc ($ff),y
adc ($ff)
dfb $73
stz $ff,x
adc $ff,x
ror $ff,x
dfb $77,$ff
sei
adc $feff,y
ply
dfb $7b
jmp ($feff,x)
L110F adc $feff,x
ror $feff,x
dfb $7f,$ff,$00
:L1118 bra :L111A
:L111A sta ($ff,x)
dfb $82,$ff
dfb $83
sty $ff
sta $ff
stx $ff
dfb $87,$ff
dey
bit #$ff
txa
dfb $8b
sty $feff
sta $feff
stx $feff
dfb $8f,$ff,$00
:L1138 bcc :L113A
:L113A sta ($ff),y
sta ($ff)
dfb $93
sty $ff,x
sta $ff,x
stx $ff,y
dfb $97,$ff
tya
sta $feff,y
txs
dfb $9b
stz $feff
sta $feff,x
stz $feff,x
dfb $9f,$ff,$00
:L1159 ldy #$ff
lda ($ff,x)
ldx #$ff
dfb $a3
ldy $ff
lda $ff
ldx $ff
dfb $a7,$ff
tay
lda #$ff
tax
dfb $ab
ldy $feff
lda $feff
ldx $feff
dfb $af,$ff,$00
:L1179 bcs :L117B
:L117B lda ($ff),y
lda ($ff)
dfb $b3
ldy $ff,x
lda $ff,x
ldx $ff,y
dfb $b7,$ff
clv
lda $feff,y
tsx
dfb $bb
ldy $feff,x
lda $feff,x
ldx $feff,y
dfb $bf,$ff,$00
:L119A cpy #$ff
cmp ($ff,x)
dfb $c2,$ff
dfb $c3
cpy $ff
cmp $ff
dec $ff
dfb $c7,$ff
iny
cmp #$ff
dex
wai
cpy $feff
cmp $feff
dec $feff
dfb $cf,$ff,$00
:L11BA bne :L11BC
:L11BC cmp ($ff),y
cmp ($ff)
dfb $d3
dfb $d4,$ff
cmp $ff,x
dec $ff,x
dfb $d7,$ff
cld
cmp $feff,y
phx
stp
L11CF dfb $dc,$ff,$fe
cmp $feff,x
dec $feff,x
dfb $df,$ff,$00
:L11DB cpx #$ff
sbc ($ff,x)
dfb $e2,$ff
dfb $e3
cpx $ff
sbc $ff
inc $ff
dfb $e7,$ff
inx
sbc #$ff
nop
dfb $eb
cpx $feff
sbc $feff
inc $feff
dfb $ef,$ff,$00
:L11FB beq :L11FD
:L11FD sbc ($ff),y
sbc ($ff)
dfb $f3
dfb $f4,$ff
sbc $ff,x
inc $ff,x
dfb $f7,$ff
sed
sbc $feff,y
plx
dfb $fb
dfb $fc,$ff,$fe
sbc $feff,x
inc $feff,x
dfb $ff,$ff,$00
:L121C rts

279
SourceGen/SGTestData/Expected/10003-allops-value-W65C02_acme.S Normal file
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!cpu w65c02
* = $1000
jsr L1017
jsr L1099
jsr L10D9
jsr L10EE
jsr L110F
jsr L11CF
nop
nop
nop
brk
!byte $ff
L1017 ora ($ff,x)
!byte $02,$ff
!byte $03
tsb $ff
ora $ff
asl $ff
rmb0 $ff
php
ora #$ff
asl
!byte $0b
tsb $feff
ora $feff
asl $feff
bbr0 $ff,@L1035
@L1035 bpl @L1037
@L1037 ora ($ff),y
ora ($ff)
!byte $13
trb $ff
ora $ff,x
asl $ff,x
rmb1 $ff
clc
ora $feff,y
inc
!byte $1b
trb $feff
ora $feff,x
asl $feff,x
bbr1 $ff,@L1056
@L1056 jsr $feff
and ($ff,x)
!byte $22,$ff
!byte $23
bit $ff
and $ff
rol $ff
rmb2 $ff
plp
and #$ff
rol
!byte $2b
bit $feff
and $feff
rol $feff
bbr2 $ff,@L1077
@L1077 bmi @L1079
@L1079 and ($ff),y
and ($ff)
!byte $33
bit $ff,x
and $ff,x
rol $ff,x
rmb3 $ff
sec
and $feff,y
dec
!byte $3b
bit $feff,x
and $feff,x
rol $feff,x
bbr3 $ff,@L1098
@L1098 rti
L1099 eor ($ff,x)
!byte $42,$ff
!byte $43
!byte $44,$ff
eor $ff
lsr $ff
rmb4 $ff
pha
eor #$ff
lsr
!byte $4b
jmp @L10AE
@L10AE eor $feff
lsr $feff
bbr4 $ff,@L10B7
@L10B7 bvc @L10B9
@L10B9 eor ($ff),y
eor ($ff)
!byte $53
!byte $54,$ff
eor $ff,x
lsr $ff,x
rmb5 $ff
cli
eor $feff,y
phy
!byte $5b
!byte $5c,$ff,$fe
eor $feff,x
lsr $feff,x
bbr5 $ff,@L10D8
@L10D8 rts
L10D9 adc ($ff,x)
!byte $62,$ff
!byte $63
stz $ff
adc $ff
ror $ff
rmb6 $ff
pla
adc #$ff
ror
!byte $6b
jmp ($feff)
L10EE adc $feff
ror $feff
bbr6 $ff,@L10F7
@L10F7 bvs @L10F9
@L10F9 adc ($ff),y
adc ($ff)
!byte $73
stz $ff,x
adc $ff,x
ror $ff,x
rmb7 $ff
sei
adc $feff,y
ply
!byte $7b
jmp ($feff,x)
L110F adc $feff,x
ror $feff,x
bbr7 $ff,@L1118
@L1118 bra @L111A
@L111A sta ($ff,x)
!byte $82,$ff
!byte $83
sty $ff
sta $ff
stx $ff
smb0 $ff
dey
bit #$ff
txa
!byte $8b
sty $feff
sta $feff
stx $feff
bbs0 $ff,@L1138
@L1138 bcc @L113A
@L113A sta ($ff),y
sta ($ff)
!byte $93
sty $ff,x
sta $ff,x
stx $ff,y
smb1 $ff
tya
sta $feff,y
txs
!byte $9b
stz $feff
sta $feff,x
stz $feff,x
bbs1 $ff,@L1159
@L1159 ldy #$ff
lda ($ff,x)
ldx #$ff
!byte $a3
ldy $ff
lda $ff
ldx $ff
smb2 $ff
tay
lda #$ff
tax
!byte $ab
ldy $feff
lda $feff
ldx $feff
bbs2 $ff,@L1179
@L1179 bcs @L117B
@L117B lda ($ff),y
lda ($ff)
!byte $b3
ldy $ff,x
lda $ff,x
ldx $ff,y
smb3 $ff
clv
lda $feff,y
tsx
!byte $bb
ldy $feff,x
lda $feff,x
ldx $feff,y
bbs3 $ff,@L119A
@L119A cpy #$ff
cmp ($ff,x)
!byte $c2,$ff
!byte $c3
cpy $ff
cmp $ff
dec $ff
smb4 $ff
iny
cmp #$ff
dex
wai
cpy $feff
cmp $feff
dec $feff
bbs4 $ff,@L11BA
@L11BA bne @L11BC
@L11BC cmp ($ff),y
cmp ($ff)
!byte $d3
!byte $d4,$ff
cmp $ff,x
dec $ff,x
smb5 $ff
cld
cmp $feff,y
phx
stp
L11CF !byte $dc,$ff,$fe
cmp $feff,x
dec $feff,x
bbs5 $ff,@L11DB
@L11DB cpx #$ff
sbc ($ff,x)
!byte $e2,$ff
!byte $e3
cpx $ff
sbc $ff
inc $ff
smb6 $ff
inx
sbc #$ff
nop
!byte $eb
cpx $feff
sbc $feff
inc $feff
bbs6 $ff,@L11FB
@L11FB beq @L11FD
@L11FD sbc ($ff),y
sbc ($ff)
!byte $f3
!byte $f4,$ff
sbc $ff,x
inc $ff,x
smb7 $ff
sed
sbc $feff,y
plx
!byte $fb
!byte $fc,$ff,$fe
sbc $feff,x
inc $feff,x
bbs7 $ff,@L121C
@L121C rts

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SourceGen/SGTestData/Expected/10003-allops-value-W65C02_cc65.S Normal file
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.setcpu "65C02"
; .segment "SEG000"
.org $1000
jsr L1017
jsr L1099
jsr L10D9
jsr L10EE
jsr L110F
jsr L11CF
nop
nop
nop
brk
.byte $ff
L1017: ora ($ff,x)
.byte $02,$ff
.byte $03
tsb $ff
ora $ff
asl $ff
rmb0 $ff
php
ora #$ff
asl A
.byte $0b
tsb $feff
ora $feff
asl $feff
bbr0 $ff,@L1035
@L1035: bpl @L1037
@L1037: ora ($ff),y
ora ($ff)
.byte $13
trb $ff
ora $ff,x
asl $ff,x
rmb1 $ff
clc
ora $feff,y
inc A
.byte $1b
trb $feff
ora $feff,x
asl $feff,x
bbr1 $ff,@L1056
@L1056: jsr $feff
and ($ff,x)
.byte $22,$ff
.byte $23
bit $ff
and $ff
rol $ff
rmb2 $ff
plp
and #$ff
rol A
.byte $2b
bit $feff
and $feff
rol $feff
bbr2 $ff,@L1077
@L1077: bmi @L1079
@L1079: and ($ff),y
and ($ff)
.byte $33
bit $ff,x
and $ff,x
rol $ff,x
rmb3 $ff
sec
and $feff,y
dec A
.byte $3b
bit $feff,x
and $feff,x
rol $feff,x
bbr3 $ff,@L1098
@L1098: rti
L1099: eor ($ff,x)
.byte $42,$ff
.byte $43
.byte $44,$ff
eor $ff
lsr $ff
rmb4 $ff
pha
eor #$ff
lsr A
.byte $4b
jmp @L10AE
@L10AE: eor $feff
lsr $feff
bbr4 $ff,@L10B7
@L10B7: bvc @L10B9
@L10B9: eor ($ff),y
eor ($ff)
.byte $53
.byte $54,$ff
eor $ff,x
lsr $ff,x
rmb5 $ff
cli
eor $feff,y
phy
.byte $5b
.byte $5c,$ff,$fe
eor $feff,x
lsr $feff,x
bbr5 $ff,@L10D8
@L10D8: rts
L10D9: adc ($ff,x)
.byte $62,$ff
.byte $63
stz $ff
adc $ff
ror $ff
rmb6 $ff
pla
adc #$ff
ror A
.byte $6b
jmp ($feff)
L10EE: adc $feff
ror $feff
bbr6 $ff,@L10F7
@L10F7: bvs @L10F9
@L10F9: adc ($ff),y
adc ($ff)
.byte $73
stz $ff,x
adc $ff,x
ror $ff,x
rmb7 $ff
sei
adc $feff,y
ply
.byte $7b
jmp ($feff,x)
L110F: adc $feff,x
ror $feff,x
bbr7 $ff,@L1118
@L1118: bra @L111A
@L111A: sta ($ff,x)
.byte $82,$ff
.byte $83
sty $ff
sta $ff
stx $ff
smb0 $ff
dey
bit #$ff
txa
.byte $8b
sty $feff
sta $feff
stx $feff
bbs0 $ff,@L1138
@L1138: bcc @L113A
@L113A: sta ($ff),y
sta ($ff)
.byte $93
sty $ff,x
sta $ff,x
stx $ff,y
smb1 $ff
tya
sta $feff,y
txs
.byte $9b
stz $feff
sta $feff,x
stz $feff,x
bbs1 $ff,@L1159
@L1159: ldy #$ff
lda ($ff,x)
ldx #$ff
.byte $a3
ldy $ff
lda $ff
ldx $ff
smb2 $ff
tay
lda #$ff
tax
.byte $ab
ldy $feff
lda $feff
ldx $feff
bbs2 $ff,@L1179
@L1179: bcs @L117B
@L117B: lda ($ff),y
lda ($ff)
.byte $b3
ldy $ff,x
lda $ff,x
ldx $ff,y
smb3 $ff
clv
lda $feff,y
tsx
.byte $bb
ldy $feff,x
lda $feff,x
ldx $feff,y
bbs3 $ff,@L119A
@L119A: cpy #$ff
cmp ($ff,x)
.byte $c2,$ff
.byte $c3
cpy $ff
cmp $ff
dec $ff
smb4 $ff
iny
cmp #$ff
dex
wai
cpy $feff
cmp $feff
dec $feff
bbs4 $ff,@L11BA
@L11BA: bne @L11BC
@L11BC: cmp ($ff),y
cmp ($ff)
.byte $d3
.byte $d4,$ff
cmp $ff,x
dec $ff,x
smb5 $ff
cld
cmp $feff,y
phx
stp
L11CF: .byte $dc,$ff,$fe
cmp $feff,x
dec $feff,x
bbs5 $ff,@L11DB
@L11DB: cpx #$ff
sbc ($ff,x)
.byte $e2,$ff
.byte $e3
cpx $ff
sbc $ff
inc $ff
smb6 $ff
inx
sbc #$ff
nop
.byte $eb
cpx $feff
sbc $feff
inc $feff
bbs6 $ff,@L11FB
@L11FB: beq @L11FD
@L11FD: sbc ($ff),y
sbc ($ff)
.byte $f3
.byte $f4,$ff
sbc $ff,x
inc $ff,x
smb7 $ff
sed
sbc $feff,y
plx
.byte $fb
.byte $fc,$ff,$fe
sbc $feff,x
inc $feff,x
bbs7 $ff,@L121C
@L121C: rts

11
SourceGen/SGTestData/Expected/10003-allops-value-W65C02_cc65.cfg Normal file
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@ -0,0 +1,11 @@
# 6502bench SourceGen generated linker script for 10003-allops-value-W65C02
MEMORY {
MAIN: file=%O, start=%S, size=65536;
# MEM000: file=%O, start=$1000, size=541;
}
SEGMENTS {
CODE: load=MAIN, type=rw;
# SEG000: load=MEM000, type=rw;
}
FEATURES {}
SYMBOLS {}

279
SourceGen/SGTestData/Expected/10013-allops-zero-W65C02_64tass.S Normal file
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.cpu "w65c02"
* = $1000
jsr L1017
jsr L1099
jsr L10D9
jsr L10EE
jsr L110F
jsr L11CF
nop
nop
nop
brk
.byte $00
L1017 ora ($00,x)
.byte $02,$00
.byte $03
tsb $00
ora $00
asl $00
rmb 0,$00
php
ora #$00
asl a
.byte $0b
tsb @w$0000
ora @w$0000
asl @w$0000
bbr 0,$00,_L1035
_L1035 bpl _L1037
_L1037 ora ($00),y
ora ($00)
.byte $13
trb $00
ora $00,x
asl $00,x
rmb 1,$00
clc
ora $0000,y
inc a
.byte $1b
trb @w$0000
ora @w$0000,x
asl @w$0000,x
bbr 1,$00,_L1056
_L1056 jsr $0000
and ($00,x)
.byte $22,$00
.byte $23
bit $00
and $00
rol $00
rmb 2,$00
plp
and #$00
rol a
.byte $2b
bit @w$0000
and @w$0000
rol @w$0000
bbr 2,$00,_L1077
_L1077 bmi _L1079
_L1079 and ($00),y
and ($00)
.byte $33
bit $00,x
and $00,x
rol $00,x
rmb 3,$00
sec
and $0000,y
dec a
.byte $3b
bit @w$0000,x
and @w$0000,x
rol @w$0000,x
bbr 3,$00,_L1098
_L1098 rti
L1099 eor ($00,x)
.byte $42,$00
.byte $43
.byte $44,$00
eor $00
lsr $00
rmb 4,$00
pha
eor #$00
lsr a
.byte $4b
jmp _L10AE
_L10AE eor @w$0000
lsr @w$0000
bbr 4,$00,_L10B7
_L10B7 bvc _L10B9
_L10B9 eor ($00),y
eor ($00)
.byte $53
.byte $54,$00
eor $00,x
lsr $00,x
rmb 5,$00
cli
eor $0000,y
phy
.byte $5b
.byte $5c,$00,$00
eor @w$0000,x
lsr @w$0000,x
bbr 5,$00,_L10D8
_L10D8 rts
L10D9 adc ($00,x)
.byte $62,$00
.byte $63
stz $00
adc $00
ror $00
rmb 6,$00
pla
adc #$00
ror a
.byte $6b
jmp ($0000)
L10EE adc @w$0000
ror @w$0000
bbr 6,$00,_L10F7
_L10F7 bvs _L10F9
_L10F9 adc ($00),y
adc ($00)
.byte $73
stz $00,x
adc $00,x
ror $00,x
rmb 7,$00
sei
adc $0000,y
ply
.byte $7b
jmp ($0000,x)
L110F adc @w$0000,x
ror @w$0000,x
bbr 7,$00,_L1118
_L1118 bra _L111A
_L111A sta ($00,x)
.byte $82,$00
.byte $83
sty $00
sta $00
stx $00
smb 0,$00
dey
bit #$00
txa
.byte $8b
sty @w$0000
sta @w$0000
stx @w$0000
bbs 0,$00,_L1138
_L1138 bcc _L113A
_L113A sta ($00),y
sta ($00)
.byte $93
sty $00,x
sta $00,x
stx $00,y
smb 1,$00
tya
sta $0000,y
txs
.byte $9b
stz @w$0000
sta @w$0000,x
stz @w$0000,x
bbs 1,$00,_L1159
_L1159 ldy #$00
lda ($00,x)
ldx #$00
.byte $a3
ldy $00
lda $00
ldx $00
smb 2,$00
tay
lda #$00
tax
.byte $ab
ldy @w$0000
lda @w$0000
ldx @w$0000
bbs 2,$00,_L1179
_L1179 bcs _L117B
_L117B lda ($00),y
lda ($00)
.byte $b3
ldy $00,x
lda $00,x
ldx $00,y
smb 3,$00
clv
lda $0000,y
tsx
.byte $bb
ldy @w$0000,x
lda @w$0000,x
ldx @w$0000,y
bbs 3,$00,_L119A
_L119A cpy #$00
cmp ($00,x)
.byte $c2,$00
.byte $c3
cpy $00
cmp $00
dec $00
smb 4,$00
iny
cmp #$00
dex
wai
cpy @w$0000
cmp @w$0000
dec @w$0000
bbs 4,$00,_L11BA
_L11BA bne _L11BC
_L11BC cmp ($00),y
cmp ($00)
.byte $d3
.byte $d4,$00
cmp $00,x
dec $00,x
smb 5,$00
cld
cmp $0000,y
phx
stp
L11CF .byte $dc,$00,$00
cmp @w$0000,x
dec @w$0000,x
bbs 5,$00,_L11DB
_L11DB cpx #$00
sbc ($00,x)
.byte $e2,$00
.byte $e3
cpx $00
sbc $00
inc $00
smb 6,$00
inx
sbc #$00
nop
.byte $eb
cpx @w$0000
sbc @w$0000
inc @w$0000
bbs 6,$00,_L11FB
_L11FB beq _L11FD
_L11FD sbc ($00),y
sbc ($00)
.byte $f3
.byte $f4,$00
sbc $00,x
inc $00,x
smb 7,$00
sed
sbc $0000,y
plx
.byte $fb
.byte $fc,$00,$00
sbc @w$0000,x
inc @w$0000,x
bbs 7,$00,_L121C
_L121C rts

278
SourceGen/SGTestData/Expected/10013-allops-zero-W65C02_Merlin32.S Normal file
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org $1000
jsr L1017
jsr L1099
jsr L10D9
jsr L10EE
jsr L110F
jsr L11CF
nop
nop
nop
brk
dfb $00
L1017 ora ($00,x)
dfb $02,$00
dfb $03
tsb $00
ora $00
asl $00
dfb $07,$00
php
ora #$00
asl A
dfb $0b
tsb: $0000
ora: $0000
asl: $0000
dfb $0f,$00,$00
:L1035 bpl :L1037
:L1037 ora ($00),y
ora ($00)
dfb $13
trb $00
ora $00,x
asl $00,x
dfb $17,$00
clc
ora $0000,y
inc A
dfb $1b
trb: $0000
ora: $0000,x
asl: $0000,x
dfb $1f,$00,$00
:L1056 jsr $0000
and ($00,x)
dfb $22,$00
dfb $23
bit $00
and $00
rol $00
dfb $27,$00
plp
and #$00
rol A
dfb $2b
bit: $0000
and: $0000
rol: $0000
dfb $2f,$00,$00
:L1077 bmi :L1079
:L1079 and ($00),y
and ($00)
dfb $33
bit $00,x
and $00,x
rol $00,x
dfb $37,$00
sec
and $0000,y
dec A
dfb $3b
bit: $0000,x
and: $0000,x
rol: $0000,x
dfb $3f,$00,$00
:L1098 rti
L1099 eor ($00,x)
dfb $42,$00
dfb $43
dfb $44,$00
eor $00
lsr $00
dfb $47,$00
pha
eor #$00
lsr A
dfb $4b
jmp :L10AE
:L10AE eor: $0000
lsr: $0000
dfb $4f,$00,$00
:L10B7 bvc :L10B9
:L10B9 eor ($00),y
eor ($00)
dfb $53
dfb $54,$00
eor $00,x
lsr $00,x
dfb $57,$00
cli
eor $0000,y
phy
dfb $5b
dfb $5c,$00,$00
eor: $0000,x
lsr: $0000,x
dfb $5f,$00,$00
:L10D8 rts
L10D9 adc ($00,x)
dfb $62,$00
dfb $63
stz $00
adc $00
ror $00
dfb $67,$00
pla
adc #$00
ror A
dfb $6b
jmp ($0000)
L10EE adc: $0000
ror: $0000
dfb $6f,$00,$00
:L10F7 bvs :L10F9
:L10F9 adc ($00),y
adc ($00)
dfb $73
stz $00,x
adc $00,x
ror $00,x
dfb $77,$00
sei
adc $0000,y
ply
dfb $7b
jmp ($0000,x)
L110F adc: $0000,x
ror: $0000,x
dfb $7f,$00,$00
:L1118 bra :L111A
:L111A sta ($00,x)
dfb $82,$00
dfb $83
sty $00
sta $00
stx $00
dfb $87,$00
dey
bit #$00
txa
dfb $8b
sty: $0000
sta: $0000
stx: $0000
dfb $8f,$00,$00
:L1138 bcc :L113A
:L113A sta ($00),y
sta ($00)
dfb $93
sty $00,x
sta $00,x
stx $00,y
dfb $97,$00
tya
sta $0000,y
txs
dfb $9b
stz: $0000
sta: $0000,x
stz: $0000,x
dfb $9f,$00,$00
:L1159 ldy #$00
lda ($00,x)
ldx #$00
dfb $a3
ldy $00
lda $00
ldx $00
dfb $a7,$00
tay
lda #$00
tax
dfb $ab
ldy: $0000
lda: $0000
ldx: $0000
dfb $af,$00,$00
:L1179 bcs :L117B
:L117B lda ($00),y
lda ($00)
dfb $b3
ldy $00,x
lda $00,x
ldx $00,y
dfb $b7,$00
clv
lda $0000,y
tsx
dfb $bb
ldy: $0000,x
lda: $0000,x
ldx: $0000,y
dfb $bf,$00,$00
:L119A cpy #$00
cmp ($00,x)
dfb $c2,$00
dfb $c3
cpy $00
cmp $00
dec $00
dfb $c7,$00
iny
cmp #$00
dex
wai
cpy: $0000
cmp: $0000
dec: $0000
dfb $cf,$00,$00
:L11BA bne :L11BC
:L11BC cmp ($00),y
cmp ($00)
dfb $d3
dfb $d4,$00
cmp $00,x
dec $00,x
dfb $d7,$00
cld
cmp $0000,y
phx
stp
L11CF dfb $dc,$00,$00
cmp: $0000,x
dec: $0000,x
dfb $df,$00,$00
:L11DB cpx #$00
sbc ($00,x)
dfb $e2,$00
dfb $e3
cpx $00
sbc $00
inc $00
dfb $e7,$00
inx
sbc #$00
nop
dfb $eb
cpx: $0000
sbc: $0000
inc: $0000
dfb $ef,$00,$00
:L11FB beq :L11FD
:L11FD sbc ($00),y
sbc ($00)
dfb $f3
dfb $f4,$00
sbc $00,x
inc $00,x
dfb $f7,$00
sed
sbc $0000,y
plx
dfb $fb
dfb $fc,$00,$00
sbc: $0000,x
inc: $0000,x
dfb $ff,$00,$00
:L121C rts

279
SourceGen/SGTestData/Expected/10013-allops-zero-W65C02_acme.S Normal file
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@ -0,0 +1,279 @@
!cpu w65c02
* = $1000
jsr L1017
jsr L1099
jsr L10D9
jsr L10EE
jsr L110F
jsr L11CF
nop
nop
nop
brk
!byte $00
L1017 ora ($00,x)
!byte $02,$00
!byte $03
tsb $00
ora $00
asl $00
rmb0 $00
php
ora #$00
asl
!byte $0b
tsb+2 $0000
ora+2 $0000
asl+2 $0000
bbr0 $00,@L1035
@L1035 bpl @L1037
@L1037 ora ($00),y
ora ($00)
!byte $13
trb $00
ora $00,x
asl $00,x
rmb1 $00
clc
ora $0000,y
inc
!byte $1b
trb+2 $0000
ora+2 $0000,x
asl+2 $0000,x
bbr1 $00,@L1056
@L1056 jsr $0000
and ($00,x)
!byte $22,$00
!byte $23
bit $00
and $00
rol $00
rmb2 $00
plp
and #$00
rol
!byte $2b
bit+2 $0000
and+2 $0000
rol+2 $0000
bbr2 $00,@L1077
@L1077 bmi @L1079
@L1079 and ($00),y
and ($00)
!byte $33
bit $00,x
and $00,x
rol $00,x
rmb3 $00
sec
and $0000,y
dec
!byte $3b
bit+2 $0000,x
and+2 $0000,x
rol+2 $0000,x
bbr3 $00,@L1098
@L1098 rti
L1099 eor ($00,x)
!byte $42,$00
!byte $43
!byte $44,$00
eor $00
lsr $00
rmb4 $00
pha
eor #$00
lsr
!byte $4b
jmp @L10AE
@L10AE eor+2 $0000
lsr+2 $0000
bbr4 $00,@L10B7
@L10B7 bvc @L10B9
@L10B9 eor ($00),y
eor ($00)
!byte $53
!byte $54,$00
eor $00,x
lsr $00,x
rmb5 $00
cli
eor $0000,y
phy
!byte $5b
!byte $5c,$00,$00
eor+2 $0000,x
lsr+2 $0000,x
bbr5 $00,@L10D8
@L10D8 rts
L10D9 adc ($00,x)
!byte $62,$00
!byte $63
stz $00
adc $00
ror $00
rmb6 $00
pla
adc #$00
ror
!byte $6b
jmp ($0000)
L10EE adc+2 $0000
ror+2 $0000
bbr6 $00,@L10F7
@L10F7 bvs @L10F9
@L10F9 adc ($00),y
adc ($00)
!byte $73
stz $00,x
adc $00,x
ror $00,x
rmb7 $00
sei
adc $0000,y
ply
!byte $7b
jmp ($0000,x)
L110F adc+2 $0000,x
ror+2 $0000,x
bbr7 $00,@L1118
@L1118 bra @L111A
@L111A sta ($00,x)
!byte $82,$00
!byte $83
sty $00
sta $00
stx $00
smb0 $00
dey
bit #$00
txa
!byte $8b
sty+2 $0000
sta+2 $0000
stx+2 $0000
bbs0 $00,@L1138
@L1138 bcc @L113A
@L113A sta ($00),y
sta ($00)
!byte $93
sty $00,x
sta $00,x
stx $00,y
smb1 $00
tya
sta $0000,y
txs
!byte $9b
stz+2 $0000
sta+2 $0000,x
stz+2 $0000,x
bbs1 $00,@L1159
@L1159 ldy #$00
lda ($00,x)
ldx #$00
!byte $a3
ldy $00
lda $00
ldx $00
smb2 $00
tay
lda #$00
tax
!byte $ab
ldy+2 $0000
lda+2 $0000
ldx+2 $0000
bbs2 $00,@L1179
@L1179 bcs @L117B
@L117B lda ($00),y
lda ($00)
!byte $b3
ldy $00,x
lda $00,x
ldx $00,y
smb3 $00
clv
lda $0000,y
tsx
!byte $bb
ldy+2 $0000,x
lda+2 $0000,x
ldx+2 $0000,y
bbs3 $00,@L119A
@L119A cpy #$00
cmp ($00,x)
!byte $c2,$00
!byte $c3
cpy $00
cmp $00
dec $00
smb4 $00
iny
cmp #$00
dex
wai
cpy+2 $0000
cmp+2 $0000
dec+2 $0000
bbs4 $00,@L11BA
@L11BA bne @L11BC
@L11BC cmp ($00),y
cmp ($00)
!byte $d3
!byte $d4,$00
cmp $00,x
dec $00,x
smb5 $00
cld
cmp $0000,y
phx
stp
L11CF !byte $dc,$00,$00
cmp+2 $0000,x
dec+2 $0000,x
bbs5 $00,@L11DB
@L11DB cpx #$00
sbc ($00,x)
!byte $e2,$00
!byte $e3
cpx $00
sbc $00
inc $00
smb6 $00
inx
sbc #$00
nop
!byte $eb
cpx+2 $0000
sbc+2 $0000
inc+2 $0000
bbs6 $00,@L11FB
@L11FB beq @L11FD
@L11FD sbc ($00),y
sbc ($00)
!byte $f3
!byte $f4,$00
sbc $00,x
inc $00,x
smb7 $00
sed
sbc $0000,y
plx
!byte $fb
!byte $fc,$00,$00
sbc+2 $0000,x
inc+2 $0000,x
bbs7 $00,@L121C
@L121C rts

280
SourceGen/SGTestData/Expected/10013-allops-zero-W65C02_cc65.S Normal file
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@ -0,0 +1,280 @@
.setcpu "65C02"
; .segment "SEG000"
.org $1000
jsr L1017
jsr L1099
jsr L10D9
jsr L10EE
jsr L110F
jsr L11CF
nop
nop
nop
brk
.byte $00
L1017: ora ($00,x)
.byte $02,$00
.byte $03
tsb $00
ora $00
asl $00
rmb0 $00
php
ora #$00
asl A
.byte $0b
tsb a:$0000
ora a:$0000
asl a:$0000
bbr0 $00,@L1035
@L1035: bpl @L1037
@L1037: ora ($00),y
ora ($00)
.byte $13
trb $00
ora $00,x
asl $00,x
rmb1 $00
clc
ora $0000,y
inc A
.byte $1b
trb a:$0000
ora a:$0000,x
asl a:$0000,x
bbr1 $00,@L1056
@L1056: jsr $0000
and ($00,x)
.byte $22,$00
.byte $23
bit $00
and $00
rol $00
rmb2 $00
plp
and #$00
rol A
.byte $2b
bit a:$0000
and a:$0000
rol a:$0000
bbr2 $00,@L1077
@L1077: bmi @L1079
@L1079: and ($00),y
and ($00)
.byte $33
bit $00,x
and $00,x
rol $00,x
rmb3 $00
sec
and $0000,y
dec A
.byte $3b
bit a:$0000,x
and a:$0000,x
rol a:$0000,x
bbr3 $00,@L1098
@L1098: rti
L1099: eor ($00,x)
.byte $42,$00
.byte $43
.byte $44,$00
eor $00
lsr $00
rmb4 $00
pha
eor #$00
lsr A
.byte $4b
jmp @L10AE
@L10AE: eor a:$0000
lsr a:$0000
bbr4 $00,@L10B7
@L10B7: bvc @L10B9
@L10B9: eor ($00),y
eor ($00)
.byte $53
.byte $54,$00
eor $00,x
lsr $00,x
rmb5 $00
cli
eor $0000,y
phy
.byte $5b
.byte $5c,$00,$00
eor a:$0000,x
lsr a:$0000,x
bbr5 $00,@L10D8
@L10D8: rts
L10D9: adc ($00,x)
.byte $62,$00
.byte $63
stz $00
adc $00
ror $00
rmb6 $00
pla
adc #$00
ror A
.byte $6b
jmp ($0000)
L10EE: adc a:$0000
ror a:$0000
bbr6 $00,@L10F7
@L10F7: bvs @L10F9
@L10F9: adc ($00),y
adc ($00)
.byte $73
stz $00,x
adc $00,x
ror $00,x
rmb7 $00
sei
adc $0000,y
ply
.byte $7b
jmp ($0000,x)
L110F: adc a:$0000,x
ror a:$0000,x
bbr7 $00,@L1118
@L1118: bra @L111A
@L111A: sta ($00,x)
.byte $82,$00
.byte $83
sty $00
sta $00
stx $00
smb0 $00
dey
bit #$00
txa
.byte $8b
sty a:$0000
sta a:$0000
stx a:$0000
bbs0 $00,@L1138
@L1138: bcc @L113A
@L113A: sta ($00),y
sta ($00)
.byte $93
sty $00,x
sta $00,x
stx $00,y
smb1 $00
tya
sta $0000,y
txs
.byte $9b
stz a:$0000
sta a:$0000,x
stz a:$0000,x
bbs1 $00,@L1159
@L1159: ldy #$00
lda ($00,x)
ldx #$00
.byte $a3
ldy $00
lda $00
ldx $00
smb2 $00
tay
lda #$00
tax
.byte $ab
ldy a:$0000
lda a:$0000
ldx a:$0000
bbs2 $00,@L1179
@L1179: bcs @L117B
@L117B: lda ($00),y
lda ($00)
.byte $b3
ldy $00,x
lda $00,x
ldx $00,y
smb3 $00
clv
lda $0000,y
tsx
.byte $bb
ldy a:$0000,x
lda a:$0000,x
ldx a:$0000,y
bbs3 $00,@L119A
@L119A: cpy #$00
cmp ($00,x)
.byte $c2,$00
.byte $c3
cpy $00
cmp $00
dec $00
smb4 $00
iny
cmp #$00
dex
wai
cpy a:$0000
cmp a:$0000
dec a:$0000
bbs4 $00,@L11BA
@L11BA: bne @L11BC
@L11BC: cmp ($00),y
cmp ($00)
.byte $d3
.byte $d4,$00
cmp $00,x
dec $00,x
smb5 $00
cld
cmp $0000,y
phx
stp
L11CF: .byte $dc,$00,$00
cmp a:$0000,x
dec a:$0000,x
bbs5 $00,@L11DB
@L11DB: cpx #$00
sbc ($00,x)
.byte $e2,$00
.byte $e3
cpx $00
sbc $00
inc $00
smb6 $00
inx
sbc #$00
nop
.byte $eb
cpx a:$0000
sbc a:$0000
inc a:$0000
bbs6 $00,@L11FB
@L11FB: beq @L11FD
@L11FD: sbc ($00),y
sbc ($00)
.byte $f3
.byte $f4,$00
sbc $00,x
inc $00,x
smb7 $00
sed
sbc $0000,y
plx
.byte $fb
.byte $fc,$00,$00
sbc a:$0000,x
inc a:$0000,x
bbs7 $00,@L121C
@L121C: rts

11
SourceGen/SGTestData/Expected/10013-allops-zero-W65C02_cc65.cfg Normal file
View File

@ -0,0 +1,11 @@
# 6502bench SourceGen generated linker script for 10013-allops-zero-W65C02
MEMORY {
MAIN: file=%O, start=%S, size=65536;
# MEM000: file=%O, start=$1000, size=541;
}
SEGMENTS {
CODE: load=MAIN, type=rw;
# SEG000: load=MEM000, type=rw;
}
FEATURES {}
SYMBOLS {}

7
SourceGen/SGTestData/README.md
View File

@ -22,9 +22,10 @@ hyphens. Files with a '.' or '_' are ignored.
If the leading number is between 10000 and 19999, inclusive, the test file
will be loaded as a new project. A load address of $1000 is assumed.
The CPU type is determined by the last digit: 0 for 6502, 1 for 65C02,
and 2 for 65816. Undocumented opcodes are enabled. As with all new
projects, the first byte will be hinted as a code entry point. The entry
flags are currently set to emulation mode, but tests should not rely on that.
2 for 65816, and 3 for W65C02. Undocumented opcodes are enabled. As with
all new projects, the first byte will be hinted as a code entry point. The
entry flags are currently set to emulation mode, but tests should not rely
on that.
If the leading number is 20000 or greater, the test file will be loaded as
a saved project. A file with the same name plus a ".dis65" extension will

3
SourceGen/WpfGui/EditInstructionOperand.xaml.cs
View File

@ -352,7 +352,8 @@ namespace SourceGen.WpfGui {
bool isPcRelative = false;
bool isBlockMove = false;
if (attr.OperandAddress >= 0) {
if (mOpDef.AddrMode == OpDef.AddressMode.PCRel) {
if (mOpDef.AddrMode == OpDef.AddressMode.PCRel ||
mOpDef.AddrMode == OpDef.AddressMode.DPPCRel) {
previewHexDigits = 4; // show branches as $xxxx even when on zero page
isPcRelative = true;
} else if (mOpDef.AddrMode == OpDef.AddressMode.PCRelLong ||