diff --git a/SourceGen/AsmGen/GenCommon.cs b/SourceGen/AsmGen/GenCommon.cs
index a8a62b3..25f7f0f 100644
--- a/SourceGen/AsmGen/GenCommon.cs
+++ b/SourceGen/AsmGen/GenCommon.cs
@@ -291,9 +291,17 @@ namespace SourceGen.AsmGen {
                 int cycles = proj.CpuDef.GetCycles(op.Opcode, attr.StatusFlags, attr.BranchTaken,
                     branchCross);
                 if (cycles > 0) {
-                    eolComment = cycles.ToString() + "  " + eolComment;
+                    if (!string.IsNullOrEmpty(eolComment)) {
+                        eolComment = cycles.ToString() + "  " + eolComment;
+                    } else {
+                        eolComment = cycles.ToString();
+                    }
                 } else {
-                    eolComment = (-cycles).ToString() + "+ " + eolComment;
+                    if (!string.IsNullOrEmpty(eolComment)) {
+                        eolComment = (-cycles).ToString() + "+ " + eolComment;
+                    } else {
+                        eolComment = (-cycles).ToString() + "+";
+                    }
                 }
             }
             string commentStr = formatter.FormatEolComment(eolComment);
diff --git a/SourceGen/SGTestData/2020-cycle-counts-65816.dis65 b/SourceGen/SGTestData/2020-cycle-counts-65816.dis65
index c53e343..24bbde7 100644
--- a/SourceGen/SGTestData/2020-cycle-counts-65816.dis65
+++ b/SourceGen/SGTestData/2020-cycle-counts-65816.dis65
@@ -13,10 +13,9 @@
 "Low":0,"High":0,"Hint":"Code"}],"StatusFlagOverrides":{
 },
 "Comments":{
-},
+"2":"crosses page boundary","28":"branch always","32":"branch never","37":"branch maybe","39":"BRK with E=1","66":"BRK with E=0","105":"should have no effect on cycle counts on 65816"},
 "LongComments":{
-"-2147483647":{
-"Text":"6502bench SourceGen v1.3.0-dev6","BoxMode":false,"MaxWidth":80,"BackgroundColor":0}},
+},
 "Notes":{
 },
 "UserLabels":{
diff --git a/SourceGen/SGTestData/Expected/2020-cycle-counts-65816_64tass.S b/SourceGen/SGTestData/Expected/2020-cycle-counts-65816_64tass.S
index a0616a5..bdf28dc 100644
--- a/SourceGen/SGTestData/Expected/2020-cycle-counts-65816_64tass.S
+++ b/SourceGen/SGTestData/Expected/2020-cycle-counts-65816_64tass.S
@@ -1,80 +1,79 @@
-;6502bench SourceGen v1.3.0-dev6
         .cpu    "65816"
 *       =       $10f0
         .as
         .xs
-L10F0   sec                ;2  
-        xce                ;2  
-        bra     L1108      ;4  
+L10F0   sec                ;2
+        xce                ;2
+        bra     L1108      ;4  crosses page boundary
 
         .fill   20,$00
 
-L1108   bra     L110A      ;3  
+L1108   bra     L110A      ;3
 
-L110A   lda     #$00       ;2  
-        beq     L1110      ;3  
+L110A   lda     #$00       ;2
+        beq     L1110      ;3  branch always
 
         .byte   $00
         .byte   $00
 
-L1110   bne     L1110      ;2  
-        lda     $1234      ;4  
-        beq     L1119      ;2+ 
-        brk                ;7  
+L1110   bne     L1110      ;2  branch never
+        lda     $1234      ;4
+        beq     L1119      ;2+ branch maybe
+        brk                ;7  BRK with E=1
 
         .byte   $01
 
-L1119   lda     $22,s      ;4  
-        trb     $02        ;5+ 
-        asl     $03,x      ;6+ 
-        clc                ;2  
-        xce                ;2  
-        rep     #$30       ;3  
+L1119   lda     $22,s      ;4
+        trb     $02        ;5+
+        asl     $03,x      ;6+
+        clc                ;2
+        xce                ;2
+        rep     #$30       ;3
         .al
         .xl
-        lda     #$0011     ;3  
-        ldy     #$0022     ;3  
-        trb     $04        ;7+ 
-        asl     $05,x      ;8+ 
-        ldx     $1235      ;5  
-        beq     L1134      ;2+ 
-        brk                ;8  
+        lda     #$0011     ;3
+        ldy     #$0022     ;3
+        trb     $04        ;7+
+        asl     $05,x      ;8+
+        ldx     $1235      ;5
+        beq     L1134      ;2+
+        brk                ;8  BRK with E=0
 
         .byte   $02
 
-L1134   lda     $33,s      ;5  
-        beq     L113A      ;2+ 
-        bra     L10F0      ;3  
+L1134   lda     $33,s      ;5
+        beq     L113A      ;2+
+        bra     L10F0      ;3
 
-L113A   rep     #$20       ;3  
-        sep     #$10       ;3  
+L113A   rep     #$20       ;3
+        sep     #$10       ;3
         .xs
-        sta     $10        ;4+ 
-        stx     $11        ;3+ 
-        sty     $12        ;3+ 
-        rep     #$10       ;3  
+        sta     $10        ;4+
+        stx     $11        ;3+
+        sty     $12        ;3+
+        rep     #$10       ;3
         .xl
-        sep     #$20       ;3  
+        sep     #$20       ;3
         .as
-        sta     $11        ;3+ 
-        stx     $12        ;4+ 
-        sty     $13        ;4+ 
-        rep     #$30       ;3  
+        sta     $11        ;3+
+        stx     $12        ;4+
+        sty     $13        ;4+
+        rep     #$30       ;3
         .al
-        lda     $1234      ;5  
-        adc     #$0066     ;3  
-        adc     $1235      ;5  
-        sed                ;2  
-        adc     #$0077     ;3  
-        adc     $1236      ;5  
-        sec                ;2  
-        xce                ;2  
+        lda     $1234      ;5
+        adc     #$0066     ;3
+        adc     $1235      ;5
+        sed                ;2  should have no effect on cycle counts on 65816
+        adc     #$0077     ;3
+        adc     $1236      ;5
+        sec                ;2
+        xce                ;2
         .as
         .xs
-        sbc     #$88       ;2  
-        sbc     $1237      ;4  
-        cld                ;2  
-        sbc     #$99       ;2  
-        sbc     $1238      ;4  
-        rts                ;6  
+        sbc     #$88       ;2
+        sbc     $1237      ;4
+        cld                ;2
+        sbc     #$99       ;2
+        sbc     $1238      ;4
+        rts                ;6
 
diff --git a/SourceGen/SGTestData/Expected/2020-cycle-counts-65816_Merlin32.S b/SourceGen/SGTestData/Expected/2020-cycle-counts-65816_Merlin32.S
index 3b410db..bbf7238 100644
--- a/SourceGen/SGTestData/Expected/2020-cycle-counts-65816_Merlin32.S
+++ b/SourceGen/SGTestData/Expected/2020-cycle-counts-65816_Merlin32.S
@@ -1,75 +1,74 @@
-;6502bench SourceGen v1.3.0-dev6
          org   $10f0
-L10F0    sec              ;2  
-         xce              ;2  
-         bra   L1108      ;4  
+L10F0    sec              ;2
+         xce              ;2
+         bra   L1108      ;4  crosses page boundary
 
          ds    20,$00
 
-L1108    bra   L110A      ;3  
+L1108    bra   L110A      ;3
 
-L110A    lda   #$00       ;2  
-         beq   L1110      ;3  
+L110A    lda   #$00       ;2
+         beq   L1110      ;3  branch always
 
          dfb   $00
          dfb   $00
 
-L1110    bne   L1110      ;2  
-         lda   $1234      ;4  
-         beq   L1119      ;2+ 
-         brk              ;7  
+L1110    bne   L1110      ;2  branch never
+         lda   $1234      ;4
+         beq   L1119      ;2+ branch maybe
+         brk              ;7  BRK with E=1
 
          dfb   $01
 
-L1119    lda   $22,S      ;4  
-         trb   $02        ;5+ 
-         asl   $03,x      ;6+ 
-         clc              ;2  
-         xce              ;2  
-         rep   #$30       ;3  
+L1119    lda   $22,S      ;4
+         trb   $02        ;5+
+         asl   $03,x      ;6+
+         clc              ;2
+         xce              ;2
+         rep   #$30       ;3
          mx    %00
-         lda   #$0011     ;3  
-         ldy   #$0022     ;3  
-         trb   $04        ;7+ 
-         asl   $05,x      ;8+ 
-         ldx   $1235      ;5  
-         beq   L1134      ;2+ 
-         brk              ;8  
+         lda   #$0011     ;3
+         ldy   #$0022     ;3
+         trb   $04        ;7+
+         asl   $05,x      ;8+
+         ldx   $1235      ;5
+         beq   L1134      ;2+
+         brk              ;8  BRK with E=0
 
          dfb   $02
 
-L1134    lda   $33,S      ;5  
-         beq   L113A      ;2+ 
-         bra   L10F0      ;3  
+L1134    lda   $33,S      ;5
+         beq   L113A      ;2+
+         bra   L10F0      ;3
 
-L113A    rep   #$20       ;3  
-         sep   #$10       ;3  
+L113A    rep   #$20       ;3
+         sep   #$10       ;3
          mx    %01
-         sta   $10        ;4+ 
-         stx   $11        ;3+ 
-         sty   $12        ;3+ 
-         rep   #$10       ;3  
+         sta   $10        ;4+
+         stx   $11        ;3+
+         sty   $12        ;3+
+         rep   #$10       ;3
          mx    %00
-         sep   #$20       ;3  
+         sep   #$20       ;3
          mx    %10
-         sta   $11        ;3+ 
-         stx   $12        ;4+ 
-         sty   $13        ;4+ 
-         rep   #$30       ;3  
+         sta   $11        ;3+
+         stx   $12        ;4+
+         sty   $13        ;4+
+         rep   #$30       ;3
          mx    %00
-         lda   $1234      ;5  
-         adc   #$0066     ;3  
-         adc   $1235      ;5  
-         sed              ;2  
-         adc   #$0077     ;3  
-         adc   $1236      ;5  
-         sec              ;2  
-         xce              ;2  
+         lda   $1234      ;5
+         adc   #$0066     ;3
+         adc   $1235      ;5
+         sed              ;2  should have no effect on cycle counts on 65816
+         adc   #$0077     ;3
+         adc   $1236      ;5
+         sec              ;2
+         xce              ;2
          mx    %11
-         sbc   #$88       ;2  
-         sbc   $1237      ;4  
-         cld              ;2  
-         sbc   #$99       ;2  
-         sbc   $1238      ;4  
-         rts              ;6  
+         sbc   #$88       ;2
+         sbc   $1237      ;4
+         cld              ;2
+         sbc   #$99       ;2
+         sbc   $1238      ;4
+         rts              ;6
 
diff --git a/SourceGen/SGTestData/Expected/2020-cycle-counts-65816_acme.S b/SourceGen/SGTestData/Expected/2020-cycle-counts-65816_acme.S
index b288b2c..91e3b84 100644
--- a/SourceGen/SGTestData/Expected/2020-cycle-counts-65816_acme.S
+++ b/SourceGen/SGTestData/Expected/2020-cycle-counts-65816_acme.S
@@ -1,80 +1,79 @@
-;6502bench SourceGen v1.3.0-dev6
         !cpu    65816
 *       =       $10f0
         !as
         !rs
-L10F0   sec                ;2  
-        xce                ;2  
-        bra     L1108      ;4  
+L10F0   sec                ;2
+        xce                ;2
+        bra     L1108      ;4  crosses page boundary
 
         !fill   20,$00
 
-L1108   bra     L110A      ;3  
+L1108   bra     L110A      ;3
 
-L110A   lda     #$00       ;2  
-        beq     L1110      ;3  
+L110A   lda     #$00       ;2
+        beq     L1110      ;3  branch always
 
         !byte   $00
         !byte   $00
 
-L1110   bne     L1110      ;2  
-        lda     $1234      ;4  
-        beq     L1119      ;2+ 
-        brk                ;7  
+L1110   bne     L1110      ;2  branch never
+        lda     $1234      ;4
+        beq     L1119      ;2+ branch maybe
+        brk                ;7  BRK with E=1
 
         !byte   $01
 
-L1119   lda     $22,S      ;4  
-        trb     $02        ;5+ 
-        asl     $03,x      ;6+ 
-        clc                ;2  
-        xce                ;2  
-        rep     #$30       ;3  
+L1119   lda     $22,S      ;4
+        trb     $02        ;5+
+        asl     $03,x      ;6+
+        clc                ;2
+        xce                ;2
+        rep     #$30       ;3
         !al
         !rl
-        lda     #$0011     ;3  
-        ldy     #$0022     ;3  
-        trb     $04        ;7+ 
-        asl     $05,x      ;8+ 
-        ldx     $1235      ;5  
-        beq     L1134      ;2+ 
-        brk                ;8  
+        lda     #$0011     ;3
+        ldy     #$0022     ;3
+        trb     $04        ;7+
+        asl     $05,x      ;8+
+        ldx     $1235      ;5
+        beq     L1134      ;2+
+        brk                ;8  BRK with E=0
 
         !byte   $02
 
-L1134   lda     $33,S      ;5  
-        beq     L113A      ;2+ 
-        bra     L10F0      ;3  
+L1134   lda     $33,S      ;5
+        beq     L113A      ;2+
+        bra     L10F0      ;3
 
-L113A   rep     #$20       ;3  
-        sep     #$10       ;3  
+L113A   rep     #$20       ;3
+        sep     #$10       ;3
         !rs
-        sta     $10        ;4+ 
-        stx     $11        ;3+ 
-        sty     $12        ;3+ 
-        rep     #$10       ;3  
+        sta     $10        ;4+
+        stx     $11        ;3+
+        sty     $12        ;3+
+        rep     #$10       ;3
         !rl
-        sep     #$20       ;3  
+        sep     #$20       ;3
         !as
-        sta     $11        ;3+ 
-        stx     $12        ;4+ 
-        sty     $13        ;4+ 
-        rep     #$30       ;3  
+        sta     $11        ;3+
+        stx     $12        ;4+
+        sty     $13        ;4+
+        rep     #$30       ;3
         !al
-        lda     $1234      ;5  
-        adc     #$0066     ;3  
-        adc     $1235      ;5  
-        sed                ;2  
-        adc     #$0077     ;3  
-        adc     $1236      ;5  
-        sec                ;2  
-        xce                ;2  
+        lda     $1234      ;5
+        adc     #$0066     ;3
+        adc     $1235      ;5
+        sed                ;2  should have no effect on cycle counts on 65816
+        adc     #$0077     ;3
+        adc     $1236      ;5
+        sec                ;2
+        xce                ;2
         !as
         !rs
-        sbc     #$88       ;2  
-        sbc     $1237      ;4  
-        cld                ;2  
-        sbc     #$99       ;2  
-        sbc     $1238      ;4  
-        rts                ;6  
+        sbc     #$88       ;2
+        sbc     $1237      ;4
+        cld                ;2
+        sbc     #$99       ;2
+        sbc     $1238      ;4
+        rts                ;6
 
diff --git a/SourceGen/SGTestData/Expected/2020-cycle-counts-65816_cc65.S b/SourceGen/SGTestData/Expected/2020-cycle-counts-65816_cc65.S
index f8b865d..d1d073f 100644
--- a/SourceGen/SGTestData/Expected/2020-cycle-counts-65816_cc65.S
+++ b/SourceGen/SGTestData/Expected/2020-cycle-counts-65816_cc65.S
@@ -1,81 +1,80 @@
-;6502bench SourceGen v1.3.0-dev6
          .setcpu "65816"
 ;         .segment "SEG000"
          .org    $10f0
          .a8
          .i8
-L10F0:   sec                ;2  
-         xce                ;2  
-         bra     L1108      ;4  
+L10F0:   sec                ;2
+         xce                ;2
+         bra     L1108      ;4  crosses page boundary
 
          .res    20,$00
 
-L1108:   bra     L110A      ;3  
+L1108:   bra     L110A      ;3
 
-L110A:   lda     #$00       ;2  
-         beq     L1110      ;3  
+L110A:   lda     #$00       ;2
+         beq     L1110      ;3  branch always
 
          .byte   $00
          .byte   $00
 
-L1110:   bne     L1110      ;2  
-         lda     $1234      ;4  
-         beq     L1119      ;2+ 
-         brk                ;7  
+L1110:   bne     L1110      ;2  branch never
+         lda     $1234      ;4
+         beq     L1119      ;2+ branch maybe
+         brk                ;7  BRK with E=1
 
          .byte   $01
 
-L1119:   lda     $22,S      ;4  
-         trb     $02        ;5+ 
-         asl     $03,x      ;6+ 
-         clc                ;2  
-         xce                ;2  
-         rep     #$30       ;3  
+L1119:   lda     $22,S      ;4
+         trb     $02        ;5+
+         asl     $03,x      ;6+
+         clc                ;2
+         xce                ;2
+         rep     #$30       ;3
          .a16
          .i16
-         lda     #$0011     ;3  
-         ldy     #$0022     ;3  
-         trb     $04        ;7+ 
-         asl     $05,x      ;8+ 
-         ldx     $1235      ;5  
-         beq     L1134      ;2+ 
-         brk                ;8  
+         lda     #$0011     ;3
+         ldy     #$0022     ;3
+         trb     $04        ;7+
+         asl     $05,x      ;8+
+         ldx     $1235      ;5
+         beq     L1134      ;2+
+         brk                ;8  BRK with E=0
 
          .byte   $02
 
-L1134:   lda     $33,S      ;5  
-         beq     L113A      ;2+ 
-         bra     L10F0      ;3  
+L1134:   lda     $33,S      ;5
+         beq     L113A      ;2+
+         bra     L10F0      ;3
 
-L113A:   rep     #$20       ;3  
-         sep     #$10       ;3  
+L113A:   rep     #$20       ;3
+         sep     #$10       ;3
          .i8
-         sta     $10        ;4+ 
-         stx     $11        ;3+ 
-         sty     $12        ;3+ 
-         rep     #$10       ;3  
+         sta     $10        ;4+
+         stx     $11        ;3+
+         sty     $12        ;3+
+         rep     #$10       ;3
          .i16
-         sep     #$20       ;3  
+         sep     #$20       ;3
          .a8
-         sta     $11        ;3+ 
-         stx     $12        ;4+ 
-         sty     $13        ;4+ 
-         rep     #$30       ;3  
+         sta     $11        ;3+
+         stx     $12        ;4+
+         sty     $13        ;4+
+         rep     #$30       ;3
          .a16
-         lda     $1234      ;5  
-         adc     #$0066     ;3  
-         adc     $1235      ;5  
-         sed                ;2  
-         adc     #$0077     ;3  
-         adc     $1236      ;5  
-         sec                ;2  
-         xce                ;2  
+         lda     $1234      ;5
+         adc     #$0066     ;3
+         adc     $1235      ;5
+         sed                ;2  should have no effect on cycle counts on 65816
+         adc     #$0077     ;3
+         adc     $1236      ;5
+         sec                ;2
+         xce                ;2
          .a8
          .i8
-         sbc     #$88       ;2  
-         sbc     $1237      ;4  
-         cld                ;2  
-         sbc     #$99       ;2  
-         sbc     $1238      ;4  
-         rts                ;6  
+         sbc     #$88       ;2
+         sbc     $1237      ;4
+         cld                ;2
+         sbc     #$99       ;2
+         sbc     $1238      ;4
+         rts                ;6