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https://github.com/fadden/6502bench.git
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Add W65C02S support, part 2
Created the "all ops" tests for W65C02. Filled in enough of the necessary infrastructure to be able to create the project and disassemble the file, though we're not yet handling the instructions correctly.
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@ -359,7 +359,7 @@ namespace Asm65 {
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InternalValidate(Cpu65C02);
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InternalValidate(CpuW65C02);
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InternalValidate(Cpu65816);
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Debug.WriteLine("CpuDefs okay");
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Debug.WriteLine("CpuDef: tests successful");
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return true;
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}
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private static void InternalValidate(CpuDef cdef) {
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@ -406,6 +406,7 @@ namespace Asm65 {
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OpDef.CycleMod.BlockMove;
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break;
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case CpuType.Cpu65C02:
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case CpuType.CpuW65C02:
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ignoreMask = OpDef.CycleMod.OneIfM0 |
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OpDef.CycleMod.TwoIfM0 |
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OpDef.CycleMod.OneIfX0 |
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@ -431,7 +432,7 @@ namespace Asm65 {
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if ((mods & OpDef.CycleMod.OneIf65C02) != 0) {
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// This isn't variable -- the instruction always takes one cycle longer
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// on the 65C02. (Applies to $6C, JMP (addr).)
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Debug.Assert(Type == CpuType.Cpu65C02);
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Debug.Assert(Type == CpuType.Cpu65C02 || Type == CpuType.CpuW65C02);
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baseCycles++;
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mods &= ~OpDef.CycleMod.OneIf65C02;
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}
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@ -973,7 +974,7 @@ namespace Asm65 {
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// behavior of the undocumented instructions remains unchanged, which is probably unwise
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// but I have no information to the contrary.
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private static CpuDef CpuW65C02 { get; } = new CpuDef("WDC W65C02S", (1 << 16) - 1, false) {
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Type = CpuType.Cpu65C02,
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Type = CpuType.CpuW65C02,
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mOpDefs = new OpDef[] {
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OpDef.OpBRK_Implied, // 0x00
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OpDef.OpORA_DPIndexXInd,
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@ -603,6 +603,10 @@ namespace Asm65 {
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case 0xf0: // BEQ
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return FlagToBT(flags.Z, 1);
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default:
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if ((op.Opcode & 0x0f) == 0x0f) {
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// assume W65C02 BBR/BBS
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return BranchTaken.Indeterminate;
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}
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// Not a conditional branch.
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throw new Exception("Not a conditional branch");
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}
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@ -262,6 +262,7 @@ namespace SourceGen {
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Debug.Assert(CommonUtil.RangeSet.Test());
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Debug.Assert(CommonUtil.TypedRangeSet.Test());
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Debug.Assert(CommonUtil.Version.Test());
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Debug.Assert(Asm65.CpuDef.DebugValidate());
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if (RuntimeDataAccess.GetDirectory() == null) {
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MessageBox.Show(Res.Strings.RUNTIME_DIR_NOT_FOUND,
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@ -307,6 +307,19 @@
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"Parameters" : {
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}
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},
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{
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"Name" : "Generic W65C02",
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"GroupName" : "Generic",
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"Cpu" : "W65C02",
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"Speed" : "1",
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"Description" : "Generic W65C02-based system (65C02 with Rockwell and WDC extensions).",
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"SymbolFiles" : [
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],
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"ExtensionScripts" : [
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],
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"Parameters" : {
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}
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},
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{
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"Name" : "Generic 65816",
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"GroupName" : "Generic",
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9
SourceGen/SGTestData/Source/10003-allops-value-W65C02.S
Normal file
9
SourceGen/SGTestData/Source/10003-allops-value-W65C02.S
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@ -0,0 +1,9 @@
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; Copyright 2020 faddenSoft. All Rights Reserved.
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; See the LICENSE.txt file for distribution terms (Apache 2.0).
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;
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; Assembler: Merlin 32
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ZP EQU $FF
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ABS EQU $FEFF
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PUT allops-common-W65C02.S
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9
SourceGen/SGTestData/Source/10013-allops-zero-W65C02.S
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9
SourceGen/SGTestData/Source/10013-allops-zero-W65C02.S
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@ -0,0 +1,9 @@
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; Copyright 2020 faddenSoft. All Rights Reserved.
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; See the LICENSE.txt file for distribution terms (Apache 2.0).
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;
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; Assembler: Merlin 32
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ZP EQU $00
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ABS EQU $0000
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PUT allops-common-W65C02.S
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296
SourceGen/SGTestData/Source/allops-common-W65C02.S
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296
SourceGen/SGTestData/Source/allops-common-W65C02.S
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@ -0,0 +1,296 @@
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; Copyright 2020 faddenSoft. All Rights Reserved.
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; See the LICENSE.txt file for distribution terms (Apache 2.0).
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;
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; Assembler: Merlin 32
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; Macros for Rockwell extensions. We use the 3-arg format to
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; cut down on the code size.
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BBR MAC ;BBR bit,zp,label
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DFB ]1*16+$0f
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DFB ]2
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DFB ]3-*-1
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<<<
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BBS MAC ;BBS bit,zp,label
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DFB ]1*16+$8f
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DFB ]2
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DFB ]3-*-1
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<<<
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RMB MAC ;RMB bit,zp
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DFB ]1*16+$07
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DFB ]2
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<<<
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SMB MAC ;SMB bit,zp
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DFB ]1*16+$87
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DFB ]2
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<<<
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ORG $1000
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JSR PostBRK
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JSR PostRTI
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JSR PostRTS
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JSR PostJMPI
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JSR PostJMPX
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JSR PostSTP
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NOP
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NOP
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NOP
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BRK ZP ;$00
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PostBRK ORA (ZP,X)
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DFB $02,ZP
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DFB $03
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TSB ZP
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ORA ZP
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ASL ZP
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RMB 0;ZP
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PHP
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ORA #ZP
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ASL
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DFB $0B
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TSB: ABS
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ORA: ABS
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ASL: ABS
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BBR 0;ZP;PostBBR0
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PostBBR0 BPL PostBPL ;$10
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PostBPL ORA (ZP),Y
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ORA (ZP)
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DFB $13
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TRB ZP
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ORA ZP,X
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ASL ZP,X
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RMB 1;ZP
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CLC
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ORA: ABS,Y
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INC
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DFB $1B
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TRB: ABS
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ORA: ABS,X
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ASL: ABS,X
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BBR 1;ZP;PostBBR1
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PostBBR1 JSR ABS ;$20
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AND (ZP,X)
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DFB $22,ZP
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DFB $23
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BIT ZP
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AND ZP
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ROL ZP
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RMB 2;ZP
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PLP
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AND #ZP
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ROL
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DFB $2B
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BIT: ABS
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AND: ABS
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ROL: ABS
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BBR 2;ZP;PostBBR2
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PostBBR2 BMI PostBMI ;$30
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PostBMI AND (ZP),Y
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AND (ZP)
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DFB $33
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BIT ZP,X
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AND ZP,X
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ROL ZP,X
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RMB 3;ZP
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SEC
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AND: ABS,Y
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DEC
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DFB $3B
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BIT: ABS,X
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AND: ABS,X
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ROL: ABS,X
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BBR 3;ZP;PostBBR3
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PostBBR3 RTI ;$40
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PostRTI EOR (ZP,X)
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DFB $42,ZP
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DFB $43
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DFB $44,ZP
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EOR ZP
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LSR ZP
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RMB 4;ZP
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PHA
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EOR #ZP
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LSR
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DFB $4B
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JMP PostJMP
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PostJMP EOR: ABS
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LSR: ABS
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BBR 4;ZP;PostBBR4
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PostBBR4 BVC PostBVC ;$50
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PostBVC EOR (ZP),Y
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EOR (ZP)
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DFB $53
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DFB $54,ZP
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EOR ZP,X
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LSR ZP,X
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RMB 5;ZP
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CLI
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EOR: ABS,Y
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PHY
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DFB $5B
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DFB $5C,<ABS,>ABS
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EOR: ABS,X
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LSR: ABS,X
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BBR 5;ZP;PostBBR5
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PostBBR5 RTS ;$60
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PostRTS ADC (ZP,X)
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DFB $62,ZP
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DFB $63
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STZ ZP
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ADC ZP
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ROR ZP
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RMB 6;ZP
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PLA
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ADC #ZP
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ROR
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DFB $6B
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JMP (ABS)
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PostJMPI ADC: ABS
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ROR: ABS
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BBR 6;ZP;PostBBR6
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PostBBR6 BVS PostBVS ;$70
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PostBVS ADC (ZP),Y
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ADC (ZP)
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DFB $73
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STZ ZP,X
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ADC ZP,X
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ROR ZP,X
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RMB 7;ZP
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SEI
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ADC: ABS,Y
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PLY
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DFB $7B
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JMP (ABS,X)
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PostJMPX ADC: ABS,X
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ROR: ABS,X
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BBR 7;ZP;PostBBR7
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PostBBR7 BRA PostBRA ;$80
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PostBRA STA (ZP,X)
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DFB $82,ZP
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DFB $83
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STY ZP
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STA ZP
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STX ZP
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SMB 0;ZP
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DEY
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BIT #ZP
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TXA
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DFB $8B
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STY: ABS
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STA: ABS
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STX: ABS
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BBS 0;ZP;PostBBS0
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PostBBS0 BCC PostBCC ;$90
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PostBCC STA (ZP),Y
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STA (ZP)
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DFB $93
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STY ZP,X
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STA ZP,X
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STX ZP,Y
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SMB 1;ZP
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TYA
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STA: ABS,Y
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TXS
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DFB $9B
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STZ: ABS
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STA: ABS,X
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STZ: ABS,X
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BBS 1;ZP;PostBBS1
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PostBBS1 LDY #ZP ;$A0
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LDA (ZP,X)
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LDX #ZP
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DFB $A3
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LDY ZP
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LDA ZP
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LDX ZP
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SMB 2;ZP
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TAY
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LDA #ZP
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TAX
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DFB $AB
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LDY: ABS
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LDA: ABS
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LDX: ABS
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BBS 2;ZP;PostBBS2
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PostBBS2 BCS PostBCS ;$B0
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PostBCS LDA (ZP),Y
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LDA (ZP)
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DFB $B3
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LDY ZP,X
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LDA ZP,X
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LDX ZP,Y
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SMB 3;ZP
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CLV
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LDA: ABS,Y
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TSX
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DFB $BB
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LDY: ABS,X
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LDA: ABS,X
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LDX: ABS,Y
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BBS 3;ZP;PostBBS3
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PostBBS3 CPY #ZP ;$C0
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CMP (ZP,X)
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DFB $C2,ZP
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DFB $C3
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CPY ZP
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CMP ZP
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DEC ZP
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SMB 4;ZP
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INY
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CMP #ZP
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DEX
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WAI
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CPY: ABS
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CMP: ABS
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DEC: ABS
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BBS 4;ZP;PostBBS4
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PostBBS4 BNE PostBNE ;$D0
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PostBNE CMP (ZP),Y
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CMP (ZP)
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DFB $D3
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DFB $D4,ZP
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CMP ZP,X
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DEC ZP,X
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SMB 5;ZP
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CLD
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CMP: ABS,Y
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PHX
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STP
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PostSTP DFB $DC,<ABS,>ABS
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CMP: ABS,X
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DEC: ABS,X
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BBS 5;ZP;PostBBS5
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PostBBS5 CPX #ZP ;$E0
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SBC (ZP,X)
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DFB $E2,ZP
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DFB $E3
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CPX ZP
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SBC ZP
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INC ZP
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SMB 6;ZP
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INX
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SBC #ZP
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NOP
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DFB $EB
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CPX: ABS
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SBC: ABS
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INC: ABS
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BBS 6;ZP;PostBBS6
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PostBBS6 BEQ PostBEQ ;$F0
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PostBEQ SBC (ZP),Y
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SBC (ZP)
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DFB $F3
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DFB $F4,ZP
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SBC ZP,X
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INC ZP,X
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SMB 7;ZP
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SED
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SBC: ABS,Y
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PLX
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DFB $FB
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DFB $FC,<ABS,>ABS
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SBC: ABS,X
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INC: ABS,X
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BBS 7;ZP;PostBBS7
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PostBBS7 rts
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@ -192,13 +192,14 @@ namespace SourceGen.Tests {
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/// <summary>
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/// Determines the desired CPU from the test case number.
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/// </summary>
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/// <param name="testNum"></param>
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/// <returns></returns>
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/// <param name="testNum">Test number.</param>
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/// <returns>CPU type enumeration value.</returns>
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private CpuDef.CpuType GetCpuTypeFromNum(int testNum) {
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switch (testNum % 10) {
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case 0: return CpuDef.CpuType.Cpu6502;
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case 1: return CpuDef.CpuType.Cpu65C02;
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case 2: return CpuDef.CpuType.Cpu65816;
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case 3: return CpuDef.CpuType.CpuW65C02;
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default: return CpuDef.CpuType.CpuUnknown;
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}
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}
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