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mirror of https://github.com/fadden/6502bench.git synced 2024-06-11 17:29:29 +00:00

Add a line to 20052-branches-and-banks

Throw a non-bank-zero JSR <hexaddr> into the mix.
This commit is contained in:
Andy McFadden 2021-07-31 13:51:35 -07:00
parent 38bc7721a4
commit c16e646701
8 changed files with 18 additions and 4 deletions

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@ -1,8 +1,8 @@
### 6502bench SourceGen dis65 v1.0 ###
{
"_ContentVersion":4,
"FileDataLength":234,
"FileDataCrc32":1224113674,
"FileDataLength":238,
"FileDataCrc32":2077431201,
"ProjectProps":{
"CpuName":"65816",
"IncludeUndocumentedInstr":false,

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@ -132,6 +132,8 @@ L543280 jsr skip+$540000
lda #$eaea
rep #$30
nop
jsr $54edcb
nop
rtl
.here

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@ -8,5 +8,5 @@
!hex 1632201732201832207d32207e32207f32eaa200fc1932fc7a32206e32207132
!hex 206832206b3220743220773280187c19327c7a326c08106c0810dc0810dc0810
!hex 7d3254eaea60200e20eac23008a90000e230a90028a9eaeae23008a900c230a9
!hex 000028a9eaeac230ea6b
!hex 000028a9eaeac230ea20cbedea6b
} ;!pseudopc

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@ -134,5 +134,7 @@ L543280: jsr skip
lda #$eaea
rep #$30
nop
jsr $edcb
nop
rtl

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@ -5,7 +5,7 @@ MEMORY {
# MEM001: file=%O, start=$440000, size=28;
# MEM002: file=%O, start=$44ffc0, size=15;
# MEM003: file=%O, start=$2000, size=32;
# MEM004: file=%O, start=$543210, size=148;
# MEM004: file=%O, start=$543210, size=152;
}
SEGMENTS {
CODE: load=MAIN, type=rw;

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@ -123,5 +123,7 @@ L543280 jsr skip
lda #$eaea
rep #$30
nop
jsr $edcb
nop
rtl

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@ -2,6 +2,7 @@
; See the LICENSE.txt file for distribution terms (Apache 2.0).
;
; Assembler: cc65
; (cl65 --target none -C <cfg>.cfg <src>.S)
;
; For the 65816 we want to exercise some additional things.
@ -129,6 +130,9 @@ fwdchk:
rts
nxt54b:
; Do odd thing: JSR to address in bank $00 from bank $54.
; Most assemblers just accept this because it's a JSR to
; a 16-bit address.
jsr skip ;EDIT: set to "skip" label
nop
@ -165,4 +169,8 @@ nxt54b:
.i16
nop
; try a 16-bit JSR with no symbol
jsr $edcb
nop
rtl