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Add Apple IIgs I/O locations in bank $E1
The $Cxxx I/O locations are mapped into banks $E0/E1, and are usually configured to appear in banks $00/01 as well. Direct access to locations in banks $E0/E1 is common in 16-bit code, but we only had definitions for $E0. This adds a clone of definitions for $E1, and renames the symbols to be _E0/_E1 instead of _GS. This can also be solved with MULTI_MASK, but that will always use $E0 as the base address, so references to $E1/Cxxx will have a large adjustment added ("+$10000"), which is kind of ugly. Note we still don't have definitions for $01/Cxxx. I'll add those if I run into them in 16-bit code. (That might be a reasonable use of MULTI_MASK; feels less ugly somehow.)
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@ -9,128 +9,128 @@
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;
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;
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; This is just the list from Cxxx-IO.sym65, with the addresses in bank $e0
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; This is just the list from Cxxx-IO.sym65, with the addresses in bank $e0
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; and "_GS" appended to the symbol names.
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; and "_E0" appended to the symbol names.
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;
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;
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KBD_GS < $E0C000 ;R last key pressed + 128
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KBD_E0 < $E0C000 ;R last key pressed + 128
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CLR80COL_GS > $E0C000 ;W use $C002-C005 for aux mem (80STOREOFF)
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CLR80COL_E0 > $E0C000 ;W use $C002-C005 for aux mem (80STOREOFF)
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SET80COL_GS @ $E0C001 ;W use PAGE2 for aux mem (80STOREON)
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SET80COL_E0 @ $E0C001 ;W use PAGE2 for aux mem (80STOREON)
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RDMAINRAM_GS @ $E0C002 ;W if 80STORE off: read main mem $0200-BFFF
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RDMAINRAM_E0 @ $E0C002 ;W if 80STORE off: read main mem $0200-BFFF
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RDCARDRAM_GS @ $E0C003 ;W if 80STORE off: read aux mem $0200-BFFF
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RDCARDRAM_E0 @ $E0C003 ;W if 80STORE off: read aux mem $0200-BFFF
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WRMAINRAM_GS @ $E0C004 ;W if 80STORE off: write main mem $0200-BFFF
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WRMAINRAM_E0 @ $E0C004 ;W if 80STORE off: write main mem $0200-BFFF
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WRCARDRAM_GS @ $E0C005 ;W if 80STORE off: write aux mem $0200-BFFF
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WRCARDRAM_E0 @ $E0C005 ;W if 80STORE off: write aux mem $0200-BFFF
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SETSLOTCXROM_GS @ $E0C006 ;W use peripheral ROM ($C100-CFFF)
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SETSLOTCXROM_E0 @ $E0C006 ;W use peripheral ROM ($C100-CFFF)
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SETINTCXROM_GS @ $E0C007 ;W use internal ROM ($C100-CFFF)
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SETINTCXROM_E0 @ $E0C007 ;W use internal ROM ($C100-CFFF)
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SETSTDZP_GS @ $E0C008 ;W use main stack and zero page
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SETSTDZP_E0 @ $E0C008 ;W use main stack and zero page
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SETALTZP_GS @ $E0C009 ;W use aux stack and zero page
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SETALTZP_E0 @ $E0C009 ;W use aux stack and zero page
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SETINTC3ROM_GS @ $E0C00A ;W use internal slot 3 ROM
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SETINTC3ROM_E0 @ $E0C00A ;W use internal slot 3 ROM
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SETSLOTC3ROM_GS @ $E0C00B ;W use external slot 3 ROM
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SETSLOTC3ROM_E0 @ $E0C00B ;W use external slot 3 ROM
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CLR80VID_GS @ $E0C00C ;W disable 80-column display mode
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CLR80VID_E0 @ $E0C00C ;W disable 80-column display mode
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SET80VID_GS @ $E0C00D ;W enable 80-column display mode
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SET80VID_E0 @ $E0C00D ;W enable 80-column display mode
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CLRALTCHAR_GS @ $E0C00E ;W use primary char set
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CLRALTCHAR_E0 @ $E0C00E ;W use primary char set
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SETALTCHAR_GS @ $E0C00F ;W use alternate char set
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SETALTCHAR_E0 @ $E0C00F ;W use alternate char set
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KBDSTRB_GS @ $E0C010 ;RW keyboard strobe
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KBDSTRB_E0 @ $E0C010 ;RW keyboard strobe
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RDLCBNK2_GS @ $E0C011 ;R bit 7: reading from LC bank 2 ($Dx)?
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RDLCBNK2_E0 @ $E0C011 ;R bit 7: reading from LC bank 2 ($Dx)?
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RDLCRAM_GS @ $E0C012 ;R bit 7: reading from LC RAM?
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RDLCRAM_E0 @ $E0C012 ;R bit 7: reading from LC RAM?
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RDRAMRD_GS @ $E0C013 ;R bit 7: reading from aux/alt 48K?
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RDRAMRD_E0 @ $E0C013 ;R bit 7: reading from aux/alt 48K?
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RDRAMWRT_GS @ $E0C014 ;R bit 7: writing to aux/alt 48K?
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RDRAMWRT_E0 @ $E0C014 ;R bit 7: writing to aux/alt 48K?
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RDCXROM_GS @ $E0C015 ;R bit 7: using internal slot ROM?
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RDCXROM_E0 @ $E0C015 ;R bit 7: using internal slot ROM?
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RDALTZP_GS @ $E0C016 ;R bit 7: using alt zero page, stack, & LC?
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RDALTZP_E0 @ $E0C016 ;R bit 7: using alt zero page, stack, & LC?
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RDC3ROM_GS @ $E0C017 ;R bit 7: using external (slot 3) ROM?
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RDC3ROM_E0 @ $E0C017 ;R bit 7: using external (slot 3) ROM?
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RD80COL_GS @ $E0C018 ;R bit 7: 80STORE is on?
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RD80COL_E0 @ $E0C018 ;R bit 7: 80STORE is on?
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RDVBLBAR_GS @ $E0C019 ;R bit 7: not VBL (VBL signal is low)?
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RDVBLBAR_E0 @ $E0C019 ;R bit 7: not VBL (VBL signal is low)?
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RDTEXT_GS @ $E0C01A ;R bit 7: using text mode?
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RDTEXT_E0 @ $E0C01A ;R bit 7: using text mode?
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RDMIX_GS @ $E0C01B ;R bit 7: using mixed mode?
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RDMIX_E0 @ $E0C01B ;R bit 7: using mixed mode?
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RDPAGE2_GS @ $E0C01C ;R bit 7: using page 2?
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RDPAGE2_E0 @ $E0C01C ;R bit 7: using page 2?
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RDHIRES_GS @ $E0C01D ;R bit 7: using hi-res graphics?
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RDHIRES_E0 @ $E0C01D ;R bit 7: using hi-res graphics?
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ALTCHARSET_GS @ $E0C01E ;R bit 7: using alt char set?
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ALTCHARSET_E0 @ $E0C01E ;R bit 7: using alt char set?
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RD80VID_GS @ $E0C01F ;R bit 7: using 80 columns?
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RD80VID_E0 @ $E0C01F ;R bit 7: using 80 columns?
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TAPEOUT_GS @ $E0C020 ;RW toggle caseette tape output
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TAPEOUT_E0 @ $E0C020 ;RW toggle caseette tape output
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MONOCOLOR_GS @ $E0C021 ;W color/mono
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MONOCOLOR_E0 @ $E0C021 ;W color/mono
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TBCOLOR_GS @ $E0C022 ;RW screen color (low is BG, high is FG)
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TBCOLOR_E0 @ $E0C022 ;RW screen color (low is BG, high is FG)
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VGCINT_GS @ $E0C023 ;R VGC interrupts
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VGCINT_E0 @ $E0C023 ;R VGC interrupts
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MOUSEDATA_GS @ $E0C024 ;R mouse data: high bit is button
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MOUSEDATA_E0 @ $E0C024 ;R mouse data: high bit is button
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KEYMODREG_GS @ $E0C025 ;R modifier key state
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KEYMODREG_E0 @ $E0C025 ;R modifier key state
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DATAREG_GS @ $E0C026 ;RW ADB command/data
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DATAREG_E0 @ $E0C026 ;RW ADB command/data
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KMSTATUS_GS @ $E0C027 ;RW ADB status
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KMSTATUS_E0 @ $E0C027 ;RW ADB status
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ROMBANK_GS @ $E0C028 ;RW ROM bank select (IIc Plus)
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ROMBANK_E0 @ $E0C028 ;RW ROM bank select (IIc Plus)
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NEWVIDEO_GS @ $E0C029 ;RW video select (SHR)
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NEWVIDEO_E0 @ $E0C029 ;RW video select (SHR)
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LANGSEL_GS @ $E0C02B ;RW ROM bank select
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LANGSEL_E0 @ $E0C02B ;RW ROM bank select
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CHARROM_GS @ $E0C02C ;R addr for character ROM test
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CHARROM_E0 @ $E0C02C ;R addr for character ROM test
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SLTROMSEL_GS @ $E0C02D ;RW slot vs. ROM selection
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SLTROMSEL_E0 @ $E0C02D ;RW slot vs. ROM selection
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VERTCNT_GS @ $E0C02E ;R read video counter bits (V5-VB)
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VERTCNT_E0 @ $E0C02E ;R read video counter bits (V5-VB)
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HORIZCNT_GS @ $E0C02F ;R read video counter bits (VA-H0)
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HORIZCNT_E0 @ $E0C02F ;R read video counter bits (VA-H0)
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SPKR_GS @ $E0C030 ;RW toggle speaker
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SPKR_E0 @ $E0C030 ;RW toggle speaker
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DISKREG_GS @ $E0C031 ;RW disk interface
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DISKREG_E0 @ $E0C031 ;RW disk interface
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SCANINT_GS @ $E0C032 ;W VGC interrupt clear
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SCANINT_E0 @ $E0C032 ;W VGC interrupt clear
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CLOCKDATA_GS @ $E0C033 ;RW battery RAM interface
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CLOCKDATA_E0 @ $E0C033 ;RW battery RAM interface
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CLOCKCTL_GS @ $E0C034 ;RW bits 0-3 = border color
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CLOCKCTL_E0 @ $E0C034 ;RW bits 0-3 = border color
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SHADOW_GS @ $E0C035 ;RW inhibit shadowing
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SHADOW_E0 @ $E0C035 ;RW inhibit shadowing
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CYAREG_GS @ $E0C036 ;RW Configure Your Apple
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CYAREG_E0 @ $E0C036 ;RW Configure Your Apple
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DMAREG_GS @ $E0C037 ;RW
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DMAREG_E0 @ $E0C037 ;RW
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SCCBREG_GS @ $E0C038 ;RW SCC command channel B
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SCCBREG_E0 @ $E0C038 ;RW SCC command channel B
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SCCAREG_GS @ $E0C039 ;RW SCC command channel A
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SCCAREG_E0 @ $E0C039 ;RW SCC command channel A
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SCCBDATA_GS @ $E0C03A ;RW SCC data channel B
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SCCBDATA_E0 @ $E0C03A ;RW SCC data channel B
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SCCADATA_GS @ $E0C03B ;RW SCC data channel A
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SCCADATA_E0 @ $E0C03B ;RW SCC data channel A
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SOUNDCTL_GS @ $E0C03C ;RW sound settings (0-3=volume)
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SOUNDCTL_E0 @ $E0C03C ;RW sound settings (0-3=volume)
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SOUNDDATA_GS @ $E0C03D ;RW sound data
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SOUNDDATA_E0 @ $E0C03D ;RW sound data
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SOUNDADRL_GS @ $E0C03E ;RW low pointer
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SOUNDADRL_E0 @ $E0C03E ;RW low pointer
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SOUNDADRH_GS @ $E0C03F ;RW high pointer
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SOUNDADRH_E0 @ $E0C03F ;RW high pointer
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STROBE_GS @ $E0C040 ;R game I/O strobe
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STROBE_E0 @ $E0C040 ;R game I/O strobe
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INTEN_GS @ $E0C041 ;RW read VBL interrupt
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INTEN_E0 @ $E0C041 ;RW read VBL interrupt
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MMDELTAX_GS @ $E0C044 ;R mouse delta movement X
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MMDELTAX_E0 @ $E0C044 ;R mouse delta movement X
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MMDELTAY_GS @ $E0C045 ;R mouse delta movement Y
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MMDELTAY_E0 @ $E0C045 ;R mouse delta movement Y
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DIAGTYPE_GS @ $E0C046 ;W self-test diagnostics
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DIAGTYPE_E0 @ $E0C046 ;W self-test diagnostics
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CLRVBLINT_GS @ $E0C047 ;W clear VBL interrupt
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CLRVBLINT_E0 @ $E0C047 ;W clear VBL interrupt
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CLRXYINT_GS @ $E0C048 ;W clear XY interrupt
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CLRXYINT_E0 @ $E0C048 ;W clear XY interrupt
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EMUBYTE_GS @ $E0C04F ;RW used by emulators to identify themselves
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EMUBYTE_E0 @ $E0C04F ;RW used by emulators to identify themselves
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TXTCLR_GS @ $E0C050 ;RW display graphics
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TXTCLR_E0 @ $E0C050 ;RW display graphics
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TXTSET_GS @ $E0C051 ;RW display text
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TXTSET_E0 @ $E0C051 ;RW display text
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MIXCLR_GS @ $E0C052 ;RW display full screen
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MIXCLR_E0 @ $E0C052 ;RW display full screen
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MIXSET_GS @ $E0C053 ;RW display split screen
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MIXSET_E0 @ $E0C053 ;RW display split screen
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TXTPAGE1_GS @ $E0C054 ;RW display page 1
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TXTPAGE1_E0 @ $E0C054 ;RW display page 1
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TXTPAGE2_GS @ $E0C055 ;RW display page 2 (or read/write aux mem)
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TXTPAGE2_E0 @ $E0C055 ;RW display page 2 (or read/write aux mem)
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LORES_GS @ $E0C056 ;RW display lo-res graphics
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LORES_E0 @ $E0C056 ;RW display lo-res graphics
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HIRES_GS @ $E0C057 ;RW display hi-res graphics
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HIRES_E0 @ $E0C057 ;RW display hi-res graphics
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SETAN0_GS @ $E0C058 ;RW annunciator 0 off
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SETAN0_E0 @ $E0C058 ;RW annunciator 0 off
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CLRAN0_GS @ $E0C059 ;RW annunciator 0 on
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CLRAN0_E0 @ $E0C059 ;RW annunciator 0 on
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SETAN1_GS @ $E0C05A ;RW annunciator 1 off
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SETAN1_E0 @ $E0C05A ;RW annunciator 1 off
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CLRAN1_GS @ $E0C05B ;RW annunciator 1 on
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CLRAN1_E0 @ $E0C05B ;RW annunciator 1 on
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SETAN2_GS @ $E0C05C ;RW annunciator 2 off
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SETAN2_E0 @ $E0C05C ;RW annunciator 2 off
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CLRAN2_GS @ $E0C05D ;RW annunciator 2 on
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CLRAN2_E0 @ $E0C05D ;RW annunciator 2 on
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SETAN3_GS @ $E0C05E ;RW annunciator 3 off
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SETAN3_E0 @ $E0C05E ;RW annunciator 3 off
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SETDHIRES_GS = $E0C05E ;W if IOUDIS set, turn on double hi-res
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SETDHIRES_E0 = $E0C05E ;W if IOUDIS set, turn on double hi-res
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CLRAN3_GS @ $E0C05F ;RW annunciator 3 on
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CLRAN3_E0 @ $E0C05F ;RW annunciator 3 on
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CLRDHIRES_GS = $E0C05F ;W if IOUDIS set, turn off double hi-res
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CLRDHIRES_E0 = $E0C05F ;W if IOUDIS set, turn off double hi-res
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TAPEIN_GS @ $E0C060 ;R read cassette input
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TAPEIN_E0 @ $E0C060 ;R read cassette input
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BUTN3_GS = $E0C060 ;R switch input 3
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BUTN3_E0 = $E0C060 ;R switch input 3
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BUTN0_GS @ $E0C061 ;R switch input 0 / open-apple
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BUTN0_E0 @ $E0C061 ;R switch input 0 / open-apple
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BUTN1_GS @ $E0C062 ;R switch input 1 / closed-apple
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BUTN1_E0 @ $E0C062 ;R switch input 1 / closed-apple
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BUTN2_GS @ $E0C063 ;R switch input 2 / shift key
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BUTN2_E0 @ $E0C063 ;R switch input 2 / shift key
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PADDL0_GS @ $E0C064 ;R analog input 0
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PADDL0_E0 @ $E0C064 ;R analog input 0
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PADDL1_GS @ $E0C065 ;R analog input 1
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PADDL1_E0 @ $E0C065 ;R analog input 1
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PADDL2_GS @ $E0C066 ;R analog input 2
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PADDL2_E0 @ $E0C066 ;R analog input 2
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PADDL3_GS @ $E0C067 ;R analog input 3
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PADDL3_E0 @ $E0C067 ;R analog input 3
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STATEREG_GS @ $E0C068 ;RW address state
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STATEREG_E0 @ $E0C068 ;RW address state
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TESTREG_GS @ $E0C06D ;test mode
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TESTREG_E0 @ $E0C06D ;test mode
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CLTRM_GS @ $E0C06E ;clear test mode
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CLTRM_E0 @ $E0C06E ;clear test mode
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ENTM_GS @ $E0C06F ;enable test mode
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ENTM_E0 @ $E0C06F ;enable test mode
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PTRIG_GS @ $E0C070 ;RW analog input reset
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PTRIG_E0 @ $E0C070 ;RW analog input reset
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RDIOUDIS_GS < $E0C07E ;R status of IOU disabling
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RDIOUDIS_E0 < $E0C07E ;R status of IOU disabling
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SETIOUDIS_GS > $E0C07E ;W disable IOU
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SETIOUDIS_E0 > $E0C07E ;W disable IOU
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RDDHIRES_GS < $E0C07F ;R status of double hi-res
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RDDHIRES_E0 < $E0C07F ;R status of double hi-res
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CLRIOUDIS_GS > $E0C07F ;W enable IOU
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CLRIOUDIS_E0 > $E0C07F ;W enable IOU
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LCBANK2_RW_GS @ $E0C080 ;RW read RAM bank 2, write off
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LCBANK2_RW_E0 @ $E0C080 ;RW read RAM bank 2, write off
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ROMIN_GS @ $E0C081 ;RWx2 read ROM, write RAM bank 2
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ROMIN_E0 @ $E0C081 ;RWx2 read ROM, write RAM bank 2
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ROMIN_RO_GS @ $E0C082 ;RW read ROM, no write
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ROMIN_RO_E0 @ $E0C082 ;RW read ROM, no write
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LCBANK2_GS @ $E0C083 ;RWx2 read/write RAM bank 2
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LCBANK2_E0 @ $E0C083 ;RWx2 read/write RAM bank 2
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LCBANK1_RW_GS @ $E0C088 ;RW read RAM bank 1, write off
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LCBANK1_RW_E0 @ $E0C088 ;RW read RAM bank 1, write off
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ROMIN1_GS @ $E0C089 ;RWx2 read ROM, write RAM bank 1
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ROMIN1_E0 @ $E0C089 ;RWx2 read ROM, write RAM bank 1
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ROMIN1_RO_GS @ $E0C08A ;RW read ROM, no write
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ROMIN1_RO_E0 @ $E0C08A ;RW read ROM, no write
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LCBANK1_GS @ $E0C08B ;RWx2 read/write RAM bank 1
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LCBANK1_E0 @ $E0C08B ;RWx2 read/write RAM bank 1
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CLRROM_GS @ $E0CFFF ;disable slot C8 ROM
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CLRROM_E0 @ $E0CFFF ;disable slot C8 ROM
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136
SourceGen/RuntimeData/Apple/E1Cxxx-IO.sym65
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136
SourceGen/RuntimeData/Apple/E1Cxxx-IO.sym65
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@ -0,0 +1,136 @@
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; Copyright 2020 faddenSoft. All Rights Reserved.
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; See the LICENSE.txt file for distribution terms (Apache 2.0).
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;
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; Sources:
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; NiftyList, by Dave Lyons
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; Various Apple II reference materials found online
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*SYNOPSIS Symbols for E1/Cxxx I/O locations
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;
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; This is just the list from Cxxx-IO.sym65, with the addresses in bank $e1
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; and "_E1" appended to the symbol names.
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;
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KBD_E1 < $E1C000 ;R last key pressed + 128
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CLR80COL_E1 > $E1C000 ;W use $C002-C005 for aux mem (80STOREOFF)
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SET80COL_E1 @ $E1C001 ;W use PAGE2 for aux mem (80STOREON)
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RDMAINRAM_E1 @ $E1C002 ;W if 80STORE off: read main mem $0200-BFFF
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RDCARDRAM_E1 @ $E1C003 ;W if 80STORE off: read aux mem $0200-BFFF
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WRMAINRAM_E1 @ $E1C004 ;W if 80STORE off: write main mem $0200-BFFF
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WRCARDRAM_E1 @ $E1C005 ;W if 80STORE off: write aux mem $0200-BFFF
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SETSLOTCXROM_E1 @ $E1C006 ;W use peripheral ROM ($C100-CFFF)
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SETINTCXROM_E1 @ $E1C007 ;W use internal ROM ($C100-CFFF)
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SETSTDZP_E1 @ $E1C008 ;W use main stack and zero page
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SETALTZP_E1 @ $E1C009 ;W use aux stack and zero page
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SETINTC3ROM_E1 @ $E1C00A ;W use internal slot 3 ROM
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SETSLOTC3ROM_E1 @ $E1C00B ;W use external slot 3 ROM
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CLR80VID_E1 @ $E1C00C ;W disable 80-column display mode
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SET80VID_E1 @ $E1C00D ;W enable 80-column display mode
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CLRALTCHAR_E1 @ $E1C00E ;W use primary char set
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SETALTCHAR_E1 @ $E1C00F ;W use alternate char set
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KBDSTRB_E1 @ $E1C010 ;RW keyboard strobe
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RDLCBNK2_E1 @ $E1C011 ;R bit 7: reading from LC bank 2 ($Dx)?
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RDLCRAM_E1 @ $E1C012 ;R bit 7: reading from LC RAM?
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RDRAMRD_E1 @ $E1C013 ;R bit 7: reading from aux/alt 48K?
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RDRAMWRT_E1 @ $E1C014 ;R bit 7: writing to aux/alt 48K?
|
||||||
|
RDCXROM_E1 @ $E1C015 ;R bit 7: using internal slot ROM?
|
||||||
|
RDALTZP_E1 @ $E1C016 ;R bit 7: using alt zero page, stack, & LC?
|
||||||
|
RDC3ROM_E1 @ $E1C017 ;R bit 7: using external (slot 3) ROM?
|
||||||
|
RD80COL_E1 @ $E1C018 ;R bit 7: 80STORE is on?
|
||||||
|
RDVBLBAR_E1 @ $E1C019 ;R bit 7: not VBL (VBL signal is low)?
|
||||||
|
RDTEXT_E1 @ $E1C01A ;R bit 7: using text mode?
|
||||||
|
RDMIX_E1 @ $E1C01B ;R bit 7: using mixed mode?
|
||||||
|
RDPAGE2_E1 @ $E1C01C ;R bit 7: using page 2?
|
||||||
|
RDHIRES_E1 @ $E1C01D ;R bit 7: using hi-res graphics?
|
||||||
|
ALTCHARSET_E1 @ $E1C01E ;R bit 7: using alt char set?
|
||||||
|
RD80VID_E1 @ $E1C01F ;R bit 7: using 80 columns?
|
||||||
|
TAPEOUT_E1 @ $E1C020 ;RW toggle caseette tape output
|
||||||
|
MONOCOLOR_E1 @ $E1C021 ;W color/mono
|
||||||
|
TBCOLOR_E1 @ $E1C022 ;RW screen color (low is BG, high is FG)
|
||||||
|
VGCINT_E1 @ $E1C023 ;R VGC interrupts
|
||||||
|
MOUSEDATA_E1 @ $E1C024 ;R mouse data: high bit is button
|
||||||
|
KEYMODREG_E1 @ $E1C025 ;R modifier key state
|
||||||
|
DATAREG_E1 @ $E1C026 ;RW ADB command/data
|
||||||
|
KMSTATUS_E1 @ $E1C027 ;RW ADB status
|
||||||
|
ROMBANK_E1 @ $E1C028 ;RW ROM bank select (IIc Plus)
|
||||||
|
NEWVIDEO_E1 @ $E1C029 ;RW video select (SHR)
|
||||||
|
LANGSEL_E1 @ $E1C02B ;RW ROM bank select
|
||||||
|
CHARROM_E1 @ $E1C02C ;R addr for character ROM test
|
||||||
|
SLTROMSEL_E1 @ $E1C02D ;RW slot vs. ROM selection
|
||||||
|
VERTCNT_E1 @ $E1C02E ;R read video counter bits (V5-VB)
|
||||||
|
HORIZCNT_E1 @ $E1C02F ;R read video counter bits (VA-H0)
|
||||||
|
SPKR_E1 @ $E1C030 ;RW toggle speaker
|
||||||
|
DISKREG_E1 @ $E1C031 ;RW disk interface
|
||||||
|
SCANINT_E1 @ $E1C032 ;W VGC interrupt clear
|
||||||
|
CLOCKDATA_E1 @ $E1C033 ;RW battery RAM interface
|
||||||
|
CLOCKCTL_E1 @ $E1C034 ;RW bits 0-3 = border color
|
||||||
|
SHADOW_E1 @ $E1C035 ;RW inhibit shadowing
|
||||||
|
CYAREG_E1 @ $E1C036 ;RW Configure Your Apple
|
||||||
|
DMAREG_E1 @ $E1C037 ;RW
|
||||||
|
SCCBREG_E1 @ $E1C038 ;RW SCC command channel B
|
||||||
|
SCCAREG_E1 @ $E1C039 ;RW SCC command channel A
|
||||||
|
SCCBDATA_E1 @ $E1C03A ;RW SCC data channel B
|
||||||
|
SCCADATA_E1 @ $E1C03B ;RW SCC data channel A
|
||||||
|
SOUNDCTL_E1 @ $E1C03C ;RW sound settings (0-3=volume)
|
||||||
|
SOUNDDATA_E1 @ $E1C03D ;RW sound data
|
||||||
|
SOUNDADRL_E1 @ $E1C03E ;RW low pointer
|
||||||
|
SOUNDADRH_E1 @ $E1C03F ;RW high pointer
|
||||||
|
STROBE_E1 @ $E1C040 ;R game I/O strobe
|
||||||
|
INTEN_E1 @ $E1C041 ;RW read VBL interrupt
|
||||||
|
|
||||||
|
MMDELTAX_E1 @ $E1C044 ;R mouse delta movement X
|
||||||
|
MMDELTAY_E1 @ $E1C045 ;R mouse delta movement Y
|
||||||
|
DIAGTYPE_E1 @ $E1C046 ;W self-test diagnostics
|
||||||
|
CLRVBLINT_E1 @ $E1C047 ;W clear VBL interrupt
|
||||||
|
CLRXYINT_E1 @ $E1C048 ;W clear XY interrupt
|
||||||
|
|
||||||
|
EMUBYTE_E1 @ $E1C04F ;RW used by emulators to identify themselves
|
||||||
|
TXTCLR_E1 @ $E1C050 ;RW display graphics
|
||||||
|
TXTSET_E1 @ $E1C051 ;RW display text
|
||||||
|
MIXCLR_E1 @ $E1C052 ;RW display full screen
|
||||||
|
MIXSET_E1 @ $E1C053 ;RW display split screen
|
||||||
|
TXTPAGE1_E1 @ $E1C054 ;RW display page 1
|
||||||
|
TXTPAGE2_E1 @ $E1C055 ;RW display page 2 (or read/write aux mem)
|
||||||
|
LORES_E1 @ $E1C056 ;RW display lo-res graphics
|
||||||
|
HIRES_E1 @ $E1C057 ;RW display hi-res graphics
|
||||||
|
SETAN0_E1 @ $E1C058 ;RW annunciator 0 off
|
||||||
|
CLRAN0_E1 @ $E1C059 ;RW annunciator 0 on
|
||||||
|
SETAN1_E1 @ $E1C05A ;RW annunciator 1 off
|
||||||
|
CLRAN1_E1 @ $E1C05B ;RW annunciator 1 on
|
||||||
|
SETAN2_E1 @ $E1C05C ;RW annunciator 2 off
|
||||||
|
CLRAN2_E1 @ $E1C05D ;RW annunciator 2 on
|
||||||
|
SETAN3_E1 @ $E1C05E ;RW annunciator 3 off
|
||||||
|
SETDHIRES_E1 = $E1C05E ;W if IOUDIS set, turn on double hi-res
|
||||||
|
CLRAN3_E1 @ $E1C05F ;RW annunciator 3 on
|
||||||
|
CLRDHIRES_E1 = $E1C05F ;W if IOUDIS set, turn off double hi-res
|
||||||
|
TAPEIN_E1 @ $E1C060 ;R read cassette input
|
||||||
|
BUTN3_E1 = $E1C060 ;R switch input 3
|
||||||
|
BUTN0_E1 @ $E1C061 ;R switch input 0 / open-apple
|
||||||
|
BUTN1_E1 @ $E1C062 ;R switch input 1 / closed-apple
|
||||||
|
BUTN2_E1 @ $E1C063 ;R switch input 2 / shift key
|
||||||
|
PADDL0_E1 @ $E1C064 ;R analog input 0
|
||||||
|
PADDL1_E1 @ $E1C065 ;R analog input 1
|
||||||
|
PADDL2_E1 @ $E1C066 ;R analog input 2
|
||||||
|
PADDL3_E1 @ $E1C067 ;R analog input 3
|
||||||
|
STATEREG_E1 @ $E1C068 ;RW address state
|
||||||
|
|
||||||
|
TESTREG_E1 @ $E1C06D ;test mode
|
||||||
|
CLTRM_E1 @ $E1C06E ;clear test mode
|
||||||
|
ENTM_E1 @ $E1C06F ;enable test mode
|
||||||
|
PTRIG_E1 @ $E1C070 ;RW analog input reset
|
||||||
|
|
||||||
|
RDIOUDIS_E1 < $E1C07E ;R status of IOU disabling
|
||||||
|
SETIOUDIS_E1 > $E1C07E ;W disable IOU
|
||||||
|
RDDHIRES_E1 < $E1C07F ;R status of double hi-res
|
||||||
|
CLRIOUDIS_E1 > $E1C07F ;W enable IOU
|
||||||
|
|
||||||
|
LCBANK2_RW_E1 @ $E1C080 ;RW read RAM bank 2, write off
|
||||||
|
ROMIN_E1 @ $E1C081 ;RWx2 read ROM, write RAM bank 2
|
||||||
|
ROMIN_RO_E1 @ $E1C082 ;RW read ROM, no write
|
||||||
|
LCBANK2_E1 @ $E1C083 ;RWx2 read/write RAM bank 2
|
||||||
|
LCBANK1_RW_E1 @ $E1C088 ;RW read RAM bank 1, write off
|
||||||
|
ROMIN1_E1 @ $E1C089 ;RWx2 read ROM, write RAM bank 1
|
||||||
|
ROMIN1_RO_E1 @ $E1C08A ;RW read ROM, no write
|
||||||
|
LCBANK1_E1 @ $E1C08B ;RWx2 read/write RAM bank 1
|
||||||
|
|
||||||
|
CLRROM_E1 @ $E1CFFF ;disable slot C8 ROM
|
@ -53,6 +53,7 @@
|
|||||||
"RT:Apple/Cxxx-IO.sym65",
|
"RT:Apple/Cxxx-IO.sym65",
|
||||||
"RT:Apple/C08x-DiskII.sym65",
|
"RT:Apple/C08x-DiskII.sym65",
|
||||||
"RT:Apple/E0Cxxx-IO.sym65",
|
"RT:Apple/E0Cxxx-IO.sym65",
|
||||||
|
"RT:Apple/E1Cxxx-IO.sym65",
|
||||||
"RT:Apple/ProDOS8.sym65",
|
"RT:Apple/ProDOS8.sym65",
|
||||||
"RT:Apple/IIgs-ROM.sym65"
|
"RT:Apple/IIgs-ROM.sym65"
|
||||||
],
|
],
|
||||||
@ -75,6 +76,7 @@
|
|||||||
"RT:Apple/Cxxx-IO.sym65",
|
"RT:Apple/Cxxx-IO.sym65",
|
||||||
"RT:Apple/C08x-DiskII.sym65",
|
"RT:Apple/C08x-DiskII.sym65",
|
||||||
"RT:Apple/E0Cxxx-IO.sym65",
|
"RT:Apple/E0Cxxx-IO.sym65",
|
||||||
|
"RT:Apple/E1Cxxx-IO.sym65",
|
||||||
"RT:Apple/IIgs-ROM.sym65",
|
"RT:Apple/IIgs-ROM.sym65",
|
||||||
"RT:Apple/GSOS.sym65"
|
"RT:Apple/GSOS.sym65"
|
||||||
],
|
],
|
||||||
|
Loading…
Reference in New Issue
Block a user