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The code was making an unwarranted assumption about how the flags were being set. For example, ORA #$00 can't know if the previous contents of the accumulator were nonzero, only that the instruction hasn't made them nonzero, but instead of marking the Z-flag "indeterminate" it was leaving the flag in its previous state. This produces incorrect results if the previous instruction didn't set its flags from the accumulator contents, e.g. it was an LDX. Test 1003-flags-and-branches has been updated to test these states.
275 lines
5.9 KiB
ArmAsm
275 lines
5.9 KiB
ArmAsm
; Copyright 2018 faddenSoft. All Rights Reserved.
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; See the LICENSE.txt file for distribution terms (Apache 2.0).
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;
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; Assembler: Merlin 32
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org $1000
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clc
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xce
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sep #$ff ;set all flags
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mx %11
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; clear individual flags with instructions
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; (this has no effect on the assembled output, but you can see the
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; effects on the "status" column in the display list)
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clv
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cld
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cli
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clc
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lda #$80 ;clear Z
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lda #$01 ;clear N
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sed
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sei
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sec
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lda #$ff ;set N
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adc #$00 ;set V, Z (actually scrambles NVZC)
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; clear individual flags with REP
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sep #$ff
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rep #$80
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rep #$40
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rep #$20
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rep #$10
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rep #$08
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rep #$04
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rep #$02
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rep #$01
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; exercise SEP/REP with #$00
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sep #$00
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sep #$ff
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rep #$00
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rep #$ff
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; confirm emulation behavior
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mx %00 ;long regs
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lda #$feed ;check it
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sec
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xce ;emulation mode
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lda #$ff ;check it
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rep #$30 ;should have no effect...
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mx %11 ;...but Merlin32 doesn't know that
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lda #$ff
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clc
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xce ;back to native, should set M/X=1
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lda #$ff ;check it
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; try one long, one short
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rep #$20 ;long a
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sep #$10 ;short x/y
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mx %01
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lda #$0000
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ldx #$01
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ldy #$02
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sep #$20 ;short a
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rep #$10 ;long x/y
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mx %10
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lda #$01
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ldx #$0000
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ldy #$0000
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; check branch instructions; NVMXDIZC
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sep #$30
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mx %11
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lda #$00
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pha
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plp ;without a nearby PHP, flags will be scrambled
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rep #$80
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bpl ok_bpl
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brk $00
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ok_bpl sep #$80
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bpl :bad ;branch never taken
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bmi ok_bmi
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:bad brk $00
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ok_bmi rep #$40
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bvc ok_bvc
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brk $00
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ok_bvc sep #$40
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bvs ok_bvs
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brk $00
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ok_bvs rep #$01
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bcc ok_bcc
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brk $00
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ok_bcc sep #$01
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bcs ok_bcs
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brk $00
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ok_bcs rep #$02
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bne ok_bne
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brk $00
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ok_bne sep #$02
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beq ok_beq
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brk $00
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ok_beq
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; check NZ flags set by immediate load
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sep #$ff ;set all
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mx %11
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lda #$01
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bne ok_nzero
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brk $db
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ok_nzero
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lda #$00
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beq ok_zero
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brk $db
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ok_zero
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bpl ok_pos
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brk $db
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ok_pos
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lda #$80
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bmi ok_neg
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brk $db
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ok_neg
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; check NZ flags set by immediate AND
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lda #$ff
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and #$00
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beq ok_andZ1
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brk $db
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ok_andZ1
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lda #$00
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ldx #$80
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and #$ff
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beq ok_andZ1A
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bne ok_andZ1A
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ok_andZ1A
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lda #$ff
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ldx #$00
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and #$7f
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beq ok_andZ0
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bne ok_andZ0
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ok_andZ0
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bpl ok_andN0
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brk $db
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ok_andN0
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lda #$ff
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and #$80
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bmi ok_andN1
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brk $db
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ok_andN1
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; check NZ flags set by immediate ORA
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lda #$00
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ldx #$80
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bne :next1
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brk $db
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:next1 ora #$00
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beq ok_oraZ1
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bne ok_oraZ1
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ok_oraZ1
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ora #$01
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bne ok_oraZ0
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brk $db
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ok_oraZ0
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lda #$00
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ldx #$80
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bmi :next2
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brk $db
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:next2 ora #$7f ;N-flag clear, but analyzer doesn't know
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bpl ok_oraN0 ;so both of these are considered viable
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bmi ok_oraN0
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brk $db
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ok_oraN0
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ora #$80
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bmi ok_oraN1
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brk $db
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ok_oraN1
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; check rol/ror
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:foo lda :foo ;scramble N/V
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sec
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ror A ;rotates the carry into the hi bit (N)
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bmi ok_ror1
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brk $dc
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ok_ror1
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clc
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ror A ;now try with carry clear
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bpl ok_ror2
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brk $dc
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ok_ror2
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lda #$00 ;set Z=1
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sec
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rol A ;set Z=0 (could also set C=0)
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bne ok_rol1
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brk $dc
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ok_rol1
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; check lsr
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lda #$ff
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lsr A ;lsr always clears the high bit
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bpl ok_lsr
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brk $dd
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ok_lsr
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; simple php/plp pair test
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clc
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php
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sec
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plp ;should restore cleared carry
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bcc ok_plp
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brk $00
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ok_plp
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; regression test for bug in analyzer
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sec ;here carry is clear
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bcs flg2
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flg1 clc
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flg2 lda $33
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beq flg1
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bcs flg3 ;this should NOT be branch-always
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lda $44
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flg3 nop
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; test tracking across subroutine calls
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rep #$20 ;long a
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sep #$10 ;short x/y
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mx %01
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jsr long_subr ;confirm flag propagation
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rep #$30
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mx %00
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jsr ambig_subr
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sep #$30
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mx %11
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jsr ambig_subr
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rep #$20 ;long a
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sep #$10 ;short x/y
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mx %01
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jsr long_subr ;call it again
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; leave the main routine with short flags set
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sep #$30
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mx %11
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rts
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; only called with longm/shortx
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mx %01
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long_subr
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lda #$1234
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ldx #$ff
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rts
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; this is called with different values for M/X, so it defaults to short
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mx %11
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ambig_subr
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lda #$ff
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ldx #$ee
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ldy #$dd
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rts
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