Files
6502bench/SourceGen/SGTestData/Expected/20310-disregard-operand_cc65.S
T
Andy McFadden cae1fa5173 Disregard operand address, part 2 (of 2)
Added assembler regression tests, for 6502 and 65816.

The "remove formatting" action now clears the flag.  It's a bit of a
stretch to call it "formatting" but this feels right.

Updated the documentation, adding a new section about embedded
instructions to the intro material.
2025-07-30 16:06:21 -07:00

72 lines
1.1 KiB
ArmAsm

.setcpu "6502"
.org $2b00
jsr L2C00
jsr L2C05
jsr L2C07
jsr L2C0D
jsr L2C10
jsr L2C17
jsr L2C18
jsr L2C19
jsr L2C1A
jsr L2C1F
jsr L2C23
jsr site4a
jsr site4b
jmp L2D00
.res 214,$2b
L2C00: bit $ff58
bvs L2C0C
L2C05: sec
.byte $90
L2C07: clc
clv
bvc L2C0C
.byte $80
L2C0C: rts
L2C0D: lda #$00
.byte $2c
L2C10: lda #$ff
sta @L2C16
rts
@L2C16: .byte $cc
L2C17: .byte $2c
L2C18: .byte $2c
L2C19: .byte $2c
L2C1A: .byte $2c
.byte $2c
nop
nop
rts
L2C1F: lda #$1f
sec
.byte $90
L2C23: .byte $a9
.byte $f0
clc
nop
bcc @L2C2A
asl A
@L2C2A: nop
rts
site4a: lda site4b+1
rts
site4b: lda site4a
rts
.res 204,$2c
L2D00: rts
.res 255,$2d