mirror of
https://github.com/fadden/6502bench.git
synced 2024-08-19 20:29:36 +00:00
39b7b20144
This is the first step toward changing the address region map from a linear list to a hierarchy. See issue #107 for the plan. The AddressMap class has been rewritten to support the new approach. The rest of the project has been updated to conform to the new API, but feature-wise is unchanged. While the map class supports nested regions with explicit lengths, the rest of the application still assumes a series of non-overlapping regions with "floating" lengths. The Set Address dialog is currently non-functional. All of the output for cc65 changed because generation of segment comments has been removed. Some of the output for ACME changed as well, because we no longer follow "* = addr" with a redundant pseudopc statement. ACME and 65tass have similar approaches to placing things in memory, and so now have similar implementations.
288 lines
5.9 KiB
ArmAsm
288 lines
5.9 KiB
ArmAsm
.setcpu "65816"
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.org $1000
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.a8
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.i8
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sec
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xce
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jsr L101F
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jsr L10AB
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jsr L10F2
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jsr L1106
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jsr L1109
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jsr L112C
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jsr L11F9
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jsr L11FC
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nop
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nop
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nop
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brk
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.byte $00
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L101F: ora ($00,x)
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cop $00
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ora $00,S
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tsb $00
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ora $00
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asl $00
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ora [$00]
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php
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ora #$00
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asl A
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phd
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tsb a:$0000
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ora a:$0000
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asl a:$0000
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ora f:$000000
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bpl @L1041
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@L1041: ora ($00),y
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ora ($00)
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ora ($00,S),y
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trb $00
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ora $00,x
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asl $00,x
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ora [$00],y
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clc
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ora $0000,y
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inc A
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tcs
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trb a:$0000
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ora a:$0000,x
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asl a:$0000,x
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ora f:$000000,x
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jsr $0000
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and ($00,x)
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jsl $000000
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and $00,S
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bit $00
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and $00
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rol $00
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and [$00]
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plp
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and #$00
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rol A
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pld
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bit a:$0000
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and a:$0000
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rol a:$0000
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and f:$000000
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bmi @L1089
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@L1089: and ($00),y
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and ($00)
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and ($00,S),y
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bit $00,x
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and $00,x
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rol $00,x
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and [$00],y
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sec
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and $0000,y
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dec A
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tsc
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bit a:$0000,x
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and a:$0000,x
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rol a:$0000,x
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and f:$000000,x
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rti
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L10AB: eor ($00,x)
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wdm $00
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eor $00,S
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mvp #$00,#$00
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eor $00
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lsr $00
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eor [$00]
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pha
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eor #$00
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lsr A
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phk
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jmp @L10C2
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@L10C2: eor a:$0000
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lsr a:$0000
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eor f:$000000
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bvc @L10CE
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@L10CE: eor ($00),y
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eor ($00)
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eor ($00,S),y
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mvn #$00,#$00
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eor $00,x
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lsr $00,x
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eor [$00],y
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cli
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eor $0000,y
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phy
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tcd
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jml @L10E7
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@L10E7: eor a:$0000,x
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lsr a:$0000,x
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eor f:$000000,x
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rts
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L10F2: adc ($00,x)
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per $0ff6
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adc $00,S
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stz $00
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adc $00
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ror $00
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adc [$00]
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pla
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adc #$00
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ror A
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rtl
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L1106: jmp ($0000)
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L1109: adc a:$0000
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ror a:$0000
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adc f:$000000
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bvs @L1115
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@L1115: adc ($00),y
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adc ($00)
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adc ($00,S),y
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stz $00,x
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adc $00,x
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ror $00,x
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adc [$00],y
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sei
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adc $0000,y
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ply
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tdc
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jmp ($0000,x)
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L112C: adc a:$0000,x
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ror a:$0000,x
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adc f:$000000,x
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bra @L1138
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@L1138: sta ($00,x)
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brl @L113D
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@L113D: sta $00,S
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sty $00
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sta $00
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stx $00
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sta [$00]
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dey
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bit #$00
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txa
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phb
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sty a:$0000
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sta a:$0000
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stx a:$0000
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sta f:$000000
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bcc @L115B
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@L115B: sta ($00),y
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sta ($00)
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sta ($00,S),y
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sty $00,x
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sta $00,x
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stx $00,y
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sta [$00],y
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tya
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sta $0000,y
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txs
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txy
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stz a:$0000
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sta a:$0000,x
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stz a:$0000,x
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sta f:$000000,x
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ldy #$00
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lda ($00,x)
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ldx #$00
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lda $00,S
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ldy $00
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lda $00
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ldx $00
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lda [$00]
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tay
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lda #$00
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tax
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plb
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ldy a:$0000
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lda a:$0000
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ldx a:$0000
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lda f:$000000
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bcs @L11A0
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@L11A0: lda ($00),y
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lda ($00)
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lda ($00,S),y
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ldy $00,x
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lda $00,x
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ldx $00,y
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lda [$00],y
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clv
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lda $0000,y
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tsx
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tyx
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ldy a:$0000,x
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lda a:$0000,x
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ldx a:$0000,y
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lda f:$000000,x
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cpy #$00
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cmp ($00,x)
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rep #$00
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cmp $00,S
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cpy $00
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cmp $00
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dec $00
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cmp [$00]
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iny
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cmp #$00
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dex
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wai
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cpy a:$0000
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cmp a:$0000
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dec a:$0000
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cmp f:$000000
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bne @L11E5
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@L11E5: cmp ($00),y
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cmp ($00)
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cmp ($00,S),y
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pei ($00)
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cmp $00,x
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dec $00,x
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cmp [$00],y
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cld
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cmp $0000,y
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phx
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stp
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L11F9: jml [$0000]
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L11FC: cmp a:$0000,x
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dec a:$0000,x
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cmp f:$000000,x
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cpx #$00
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sbc ($00,x)
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sep #$00
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sbc $00,S
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cpx $00
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sbc $00
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inc $00
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sbc [$00]
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inx
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sbc #$00
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nop
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xba
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cpx a:$0000
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sbc a:$0000
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inc a:$0000
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sbc f:$000000
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beq @L122A
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@L122A: sbc ($00),y
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sbc ($00)
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sbc ($00,S),y
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pea $0000
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sbc $00,x
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inc $00,x
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sbc [$00],y
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sed
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sbc $0000,y
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plx
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xce
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jsr ($0000,x)
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sbc a:$0000,x
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inc a:$0000,x
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sbc f:$000000,x
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