1
0
mirror of https://github.com/fadden/6502bench.git synced 2024-06-30 06:29:32 +00:00
6502bench/SourceGen/SGTestData/Expected/10010-allops-zero-6502_acme.S
Andy McFadden 3ff0fbae34 Regression test rework, part 1
The regression tests were written with the assumption that all cross
assemblers would support 6502, 65C02, and 65816 code.  There are a
few that support 65816 partially (e.g. ACME) or not at all.  To best
support these, we need to split some of the tests into pieces, so
that important 6502 tests aren't skipped simply because parts of the
test also exercise 65816 code.

The first step is to change the regression test naming scheme.  The
old system used 1xxx for tests without project files, and 2xxx for
tests with project files.  The new system uses 1xxxN / 2xxxN, where
N indicates the CPU type: 0 for 6502, 1 for 65C02, and 2 for 65816.
For the 1xxxN tests the new value determines which CPU is used,
which allows us to move the "allops" 6502/65C02 tests into the
no-project category.  For 2xxxN it just allows the 6502 and 65816
versions to have the same base name and number.

This change updates the first batch of tests.  It involves minor
changes to the test harness and a whole bunch of renaming.
2020-06-06 14:47:19 -07:00

297 lines
5.8 KiB
ArmAsm

!cpu 6510
* = $1000
jsr L1035
jsr L1038
jsr L1059
jsr L107D
jsr L109E
jsr L10BD
jsr L10C0
jsr L10E1
jsr L1100
jsr L1103
jsr L1116
jsr L1124
jsr L1169
jsr L11AE
jsr L11F3
jsr L1238
nop
nop
nop
brk
!byte $00
L1035 ora ($00,x)
jam
L1038 slo ($00,x)
!byte $04,$00
ora $00
asl $00
slo $00
php
ora #$00
asl
anc #$00
!byte $0c,$00,$00
ora+2 $0000
asl+2 $0000
slo+2 $0000
bpl @L1056
@L1056 ora ($00),y
!byte $12
L1059 slo ($00),y
!byte $14,$00
ora $00,x
asl $00,x
slo $00,x
clc
ora $0000,y
!byte $1a
slo $0000,y
!byte $1c,$00,$00
ora+2 $0000,x
asl+2 $0000,x
slo+2 $0000,x
jsr $0000
and ($00,x)
!byte $22
L107D rla ($00,x)
bit $00
and $00
rol $00
rla $00
plp
and #$00
rol
!byte $2b,$00
bit+2 $0000
and+2 $0000
rol+2 $0000
rla+2 $0000
bmi @L109B
@L109B and ($00),y
!byte $32
L109E rla ($00),y
!byte $34,$00
and $00,x
rol $00,x
rla $00,x
sec
and $0000,y
!byte $3a
rla $0000,y
!byte $3c,$00,$00
and+2 $0000,x
rol+2 $0000,x
rla+2 $0000,x
rti
L10BD eor ($00,x)
!byte $42
L10C0 sre ($00,x)
!byte $44,$00
eor $00
lsr $00
sre $00
pha
eor #$00
lsr
asr #$00
jmp @L10D3
@L10D3 eor+2 $0000
lsr+2 $0000
sre+2 $0000
bvc @L10DE
@L10DE eor ($00),y
!byte $52
L10E1 sre ($00),y
!byte $54,$00
eor $00,x
lsr $00,x
sre $00,x
cli
eor $0000,y
!byte $5a
sre $0000,y
!byte $5c,$00,$00
eor+2 $0000,x
lsr+2 $0000,x
sre+2 $0000,x
rts
L1100 adc ($00,x)
!byte $62
L1103 rra ($00,x)
!byte $64,$00
adc $00
ror $00
rra $00
pla
adc #$00
ror
arr #$00
jmp ($0000)
L1116 adc+2 $0000
ror+2 $0000
rra+2 $0000
bvs @L1121
@L1121 adc ($00),y
!byte $72
L1124 rra ($00),y
!byte $74,$00
adc $00,x
ror $00,x
rra $00,x
sei
adc $0000,y
!byte $7a
rra $0000,y
!byte $7c,$00,$00
adc+2 $0000,x
ror+2 $0000,x
rra+2 $0000,x
!byte $80,$00
sta ($00,x)
!byte $82,$00
sax ($00,x)
sty $00
sta $00
stx $00
sax $00
dey
!byte $89,$00
txa
ane #$00
sty+2 $0000
sta+2 $0000
stx+2 $0000
sax+2 $0000
bcc @L1166
@L1166 sta ($00),y
!byte $92
L1169 sha ($00),y
sty $00,x
sta $00,x
stx $00,y
sax $00,y
tya
sta $0000,y
txs
tas $0000,y
shy+2 $0000,x
sta+2 $0000,x
shx $0000,y
sha $0000,y
ldy #$00
lda ($00,x)
ldx #$00
lax ($00,x)
ldy $00
lda $00
ldx $00
lax $00
tay
lda #$00
tax
!byte $ab,$00
ldy+2 $0000
lda+2 $0000
ldx+2 $0000
lax+2 $0000
bcs @L11AB
@L11AB lda ($00),y
!byte $b2
L11AE lax ($00),y
ldy $00,x
lda $00,x
ldx $00,y
lax $00,y
clv
lda $0000,y
tsx
las $0000,y
ldy+2 $0000,x
lda+2 $0000,x
ldx+2 $0000,y
lax+2 $0000,y
cpy #$00
cmp ($00,x)
!byte $c2,$00
dcp ($00,x)
cpy $00
cmp $00
dec $00
dcp $00
iny
cmp #$00
dex
sbx #$00
cpy+2 $0000
cmp+2 $0000
dec+2 $0000
dcp+2 $0000
bne @L11F0
@L11F0 cmp ($00),y
!byte $d2
L11F3 dcp ($00),y
!byte $d4,$00
cmp $00,x
dec $00,x
dcp $00,x
cld
cmp $0000,y
!byte $da
dcp $0000,y
!byte $dc,$00,$00
cmp+2 $0000,x
dec+2 $0000,x
dcp+2 $0000,x
cpx #$00
sbc ($00,x)
!byte $e2,$00
isc ($00,x)
cpx $00
sbc $00
inc $00
isc $00
inx
sbc #$00
nop
!byte $eb,$00
cpx+2 $0000
sbc+2 $0000
inc+2 $0000
isc+2 $0000
beq @L1235
@L1235 sbc ($00),y
!byte $f2
L1238 isc ($00),y
!byte $f4,$00
sbc $00,x
inc $00,x
isc $00,x
sed
sbc $0000,y
!byte $fa
isc $0000,y
!byte $fc,$00,$00
sbc+2 $0000,x
inc+2 $0000,x
isc+2 $0000,x