mirror of
https://github.com/fadden/6502bench.git
synced 2024-06-30 06:29:32 +00:00
39b7b20144
This is the first step toward changing the address region map from a linear list to a hierarchy. See issue #107 for the plan. The AddressMap class has been rewritten to support the new approach. The rest of the project has been updated to conform to the new API, but feature-wise is unchanged. While the map class supports nested regions with explicit lengths, the rest of the application still assumes a series of non-overlapping regions with "floating" lengths. The Set Address dialog is currently non-functional. All of the output for cc65 changed because generation of segment comments has been removed. Some of the output for ACME changed as well, because we no longer follow "* = addr" with a redundant pseudopc statement. ACME and 65tass have similar approaches to placing things in memory, and so now have similar implementations.
297 lines
6.2 KiB
ArmAsm
297 lines
6.2 KiB
ArmAsm
.setcpu "6502X"
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.org $1000
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jsr L1035
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jsr L1038
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jsr L1059
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jsr L107D
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jsr L109E
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jsr L10BD
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jsr L10C0
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jsr L10E1
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jsr L1100
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jsr L1103
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jsr L1116
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jsr L1124
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jsr L1169
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jsr L11AE
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jsr L11F3
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jsr L1238
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nop
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nop
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nop
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brk
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.byte $00
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L1035: ora ($00,x)
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jam
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L1038: slo ($00,x)
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.byte $04,$00
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ora $00
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asl $00
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slo $00
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php
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ora #$00
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asl A
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anc #$00
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.byte $0c,$00,$00
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ora a:$0000
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asl a:$0000
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slo a:$0000
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bpl @L1056
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@L1056: ora ($00),y
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.byte $12
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L1059: slo ($00),y
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.byte $14,$00
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ora $00,x
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asl $00,x
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slo $00,x
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clc
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ora $0000,y
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.byte $1a
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slo $0000,y
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.byte $1c,$00,$00
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ora a:$0000,x
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asl a:$0000,x
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slo a:$0000,x
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jsr $0000
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and ($00,x)
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.byte $22
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L107D: rla ($00,x)
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bit $00
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and $00
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rol $00
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rla $00
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plp
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and #$00
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rol A
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.byte $2b,$00
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bit a:$0000
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and a:$0000
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rol a:$0000
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rla a:$0000
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bmi @L109B
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@L109B: and ($00),y
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.byte $32
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L109E: rla ($00),y
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.byte $34,$00
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and $00,x
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rol $00,x
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rla $00,x
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sec
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and $0000,y
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.byte $3a
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rla $0000,y
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.byte $3c,$00,$00
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and a:$0000,x
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rol a:$0000,x
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rla a:$0000,x
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rti
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L10BD: eor ($00,x)
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.byte $42
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L10C0: sre ($00,x)
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.byte $44,$00
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eor $00
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lsr $00
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sre $00
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pha
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eor #$00
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lsr A
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alr #$00
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jmp @L10D3
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@L10D3: eor a:$0000
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lsr a:$0000
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sre a:$0000
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bvc @L10DE
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@L10DE: eor ($00),y
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.byte $52
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L10E1: sre ($00),y
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.byte $54,$00
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eor $00,x
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lsr $00,x
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sre $00,x
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cli
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eor $0000,y
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.byte $5a
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sre $0000,y
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.byte $5c,$00,$00
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eor a:$0000,x
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lsr a:$0000,x
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sre a:$0000,x
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rts
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L1100: adc ($00,x)
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.byte $62
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L1103: rra ($00,x)
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.byte $64,$00
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adc $00
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ror $00
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rra $00
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pla
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adc #$00
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ror A
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arr #$00
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jmp ($0000)
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L1116: adc a:$0000
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ror a:$0000
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rra a:$0000
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bvs @L1121
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@L1121: adc ($00),y
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.byte $72
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L1124: rra ($00),y
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.byte $74,$00
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adc $00,x
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ror $00,x
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rra $00,x
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sei
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adc $0000,y
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.byte $7a
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rra $0000,y
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.byte $7c,$00,$00
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adc a:$0000,x
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ror a:$0000,x
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rra a:$0000,x
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.byte $80,$00
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sta ($00,x)
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.byte $82,$00
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sax ($00,x)
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sty $00
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sta $00
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stx $00
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sax $00
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dey
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.byte $89,$00
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txa
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ane #$00
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sty a:$0000
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sta a:$0000
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stx a:$0000
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sax a:$0000
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bcc @L1166
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@L1166: sta ($00),y
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.byte $92
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L1169: sha ($00),y
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sty $00,x
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sta $00,x
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stx $00,y
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sax $00,y
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tya
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sta $0000,y
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txs
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tas $0000,y
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shy a:$0000,x
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sta a:$0000,x
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shx $0000,y
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sha $0000,y
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ldy #$00
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lda ($00,x)
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ldx #$00
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lax ($00,x)
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ldy $00
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lda $00
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ldx $00
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lax $00
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tay
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lda #$00
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tax
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lax #$00
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ldy a:$0000
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lda a:$0000
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ldx a:$0000
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lax a:$0000
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bcs @L11AB
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@L11AB: lda ($00),y
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.byte $b2
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L11AE: lax ($00),y
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ldy $00,x
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lda $00,x
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ldx $00,y
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lax $00,y
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clv
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lda $0000,y
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tsx
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las $0000,y
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ldy a:$0000,x
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lda a:$0000,x
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ldx a:$0000,y
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lax a:$0000,y
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cpy #$00
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cmp ($00,x)
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.byte $c2,$00
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dcp ($00,x)
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cpy $00
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cmp $00
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dec $00
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dcp $00
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iny
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cmp #$00
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dex
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axs #$00
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cpy a:$0000
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cmp a:$0000
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dec a:$0000
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dcp a:$0000
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bne @L11F0
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@L11F0: cmp ($00),y
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.byte $d2
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L11F3: dcp ($00),y
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.byte $d4,$00
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cmp $00,x
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dec $00,x
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dcp $00,x
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cld
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cmp $0000,y
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.byte $da
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dcp $0000,y
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.byte $dc,$00,$00
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cmp a:$0000,x
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dec a:$0000,x
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dcp a:$0000,x
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cpx #$00
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sbc ($00,x)
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.byte $e2,$00
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isc ($00,x)
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cpx $00
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sbc $00
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inc $00
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isc $00
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inx
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sbc #$00
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nop
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.byte $eb,$00
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cpx a:$0000
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sbc a:$0000
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inc a:$0000
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isc a:$0000
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beq @L1235
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@L1235: sbc ($00),y
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.byte $f2
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L1238: isc ($00),y
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.byte $f4,$00
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sbc $00,x
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inc $00,x
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isc $00,x
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sed
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sbc $0000,y
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.byte $fa
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isc $0000,y
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.byte $fc,$00,$00
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sbc a:$0000,x
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inc a:$0000,x
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isc a:$0000,x
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