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https://github.com/fadden/6502bench.git
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39b7b20144
This is the first step toward changing the address region map from a linear list to a hierarchy. See issue #107 for the plan. The AddressMap class has been rewritten to support the new approach. The rest of the project has been updated to conform to the new API, but feature-wise is unchanged. While the map class supports nested regions with explicit lengths, the rest of the application still assumes a series of non-overlapping regions with "floating" lengths. The Set Address dialog is currently non-functional. All of the output for cc65 changed because generation of segment comments has been removed. Some of the output for ACME changed as well, because we no longer follow "* = addr" with a redundant pseudopc statement. ACME and 65tass have similar approaches to placing things in memory, and so now have similar implementations.
80 lines
2.0 KiB
ArmAsm
80 lines
2.0 KiB
ArmAsm
.setcpu "65816"
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.org $10f0
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.a8
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.i8
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L10F0: sec ;2
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xce ;2
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bra @L1108 ;4 crosses page boundary
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.res 20,$00
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@L1108: bra @L110A ;3
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@L110A: lda #$00 ;2
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beq @L1110 ;3 branch always
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.byte $00
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.byte $00
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@L1110: bne @L1110 ;2 branch never
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lda $1234 ;4
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beq @L1119 ;2+ branch maybe
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brk ;7 BRK with E=1
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.byte $01
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@L1119: lda $22,S ;4
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trb $02 ;5+
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asl $03,x ;6+
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clc ;2
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xce ;2
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rep #$30 ;3
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.a16
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.i16
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lda #$0011 ;3
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ldy #$0022 ;3
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trb $04 ;7+
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asl $05,x ;8+
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ldx $1235 ;5
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beq @L1134 ;2+
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brk ;8 BRK with E=0
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.byte $02
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@L1134: lda $33,S ;5
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beq @L113A ;2+
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bra L10F0 ;3
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@L113A: rep #$20 ;3
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sep #$10 ;3
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.i8
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sta $10 ;4+
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stx $11 ;3+
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sty $12 ;3+
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rep #$10 ;3
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.i16
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sep #$20 ;3
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.a8
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sta $11 ;3+
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stx $12 ;4+
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sty $13 ;4+
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rep #$30 ;3
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.a16
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lda $1234 ;5
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adc #$0066 ;3
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adc $1235 ;5
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sed ;2 should have no effect on cycle counts on 65816
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adc #$0077 ;3
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adc $1236 ;5
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sec ;2
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xce ;2
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.a8
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.i8
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sbc #$88 ;2
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sbc $1237 ;4
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cld ;2
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sbc #$99 ;2
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sbc $1238 ;4
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rts ;6
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