mirror of
https://github.com/fadden/6502bench.git
synced 2024-06-30 06:29:32 +00:00
387b50d827
Added support for "relative" address regions to the Merlin 32 and cc65 code generators. These generate "flat" address directives, and so were a little more complicated. Suppressed generation of relative operands for non-addressable regions. Also, tweaked the 20250-nested-regions test to include a negative relative region offset.
94 lines
1.8 KiB
ArmAsm
94 lines
1.8 KiB
ArmAsm
.setcpu "6502"
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.org $0000
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.word $3000 ;load address
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.org $1000
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.org *+$1000
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.org *+$1000
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L3000: bit L3000
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@L3003: lda @L3003
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and @LE003
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jmp @L200C
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.org $200c
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@L200C: bit @L200C
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jmp @L1012
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.org $1012
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@L1012: bit @L1012
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jsr @L4000
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.org $0000
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.byte $00
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.byte $ce,$55,$4c,$4c,$2d,$54,$45,$52,$4d,$20,$d0,$c5,$d4,$d3,$c3,$c9
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.byte $c9,$20,$53,$54,$52,$49,$4e,$47,$00
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.byte $80
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.word @L3003
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.word @LE003
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.byte $80
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.org $4000
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@L4000: bit @L4000
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bit @L5000
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bit @L500F
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bit @L500F
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nop
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jmp @L4020
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.org $5000
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@L5000: bit @L5000
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bit @L4000
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nop
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nop
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@L5008: bit @L5008
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bit @L5017
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nop
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@L500F: rts
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.org $4020
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@L4020: bit @L4020
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bit @L500F
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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jmp @L4040
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.org $5008
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@L5008_0: bit @L5008_0
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bit @L5000
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nop
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@L500F_0: bit @L500F_0
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nop
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nop
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nop
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nop
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nop
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@L5017: rts
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.org $4040
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@L4040: bit @L4040
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bit @L5017
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nop
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jmp @LE000
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.org $1082
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.org *+$cf7e
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@LE000: bit @L200C
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@LE003: nop
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jmp @LD000
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.org *-$1007
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@LD000: bit @LD000
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jmp @LF000
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.org $f000
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@LF000: bit @LF000
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lda @L3003
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and @LE003
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nop
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rts
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