mirror of
https://github.com/fadden/6502bench.git
synced 2024-07-14 05:28:55 +00:00
4981c3cdbb
ACME has a "real" PC and a "pseudo" PC. The "real" PC determines the initial position in a 64KB buffer used to hold assembler output. If the amount of code generated runs off the end, the assembler fails with "produced too much code". The source code generator in SourceGen was outputting a "real" PC for the first address range and "psuedo" PCs for any address ranges that followed. This produced nice results for code with a single range, but caused problems for multi-range sources if the initial range was high in memory and a later range was lower in memory. While the assembler isn't actually generating more than 64KB of code, ACME's buffer management was detecting an overflow. Now, if a source file has multiple address ranges, we set the "real" PC to $0000 and use a "pseudo" PC for all ranges. Output for projects with a single address range is unmodified.
298 lines
5.8 KiB
ArmAsm
298 lines
5.8 KiB
ArmAsm
;6502bench SourceGen v1.1.0-dev1
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!cpu 65816
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* = $0000
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!pseudopc $1000 {
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!as
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!rs
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sec
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xce
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jsr L101F
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jsr L10AB
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jsr L10F2
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jsr L1106
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jsr L1109
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jsr L112C
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jsr L11F9
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jsr L11FC
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nop
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nop
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nop
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brk
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!byte $80
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L101F ora (L0080,x)
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cop $80
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ora $80,S
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tsb+1 L0080
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ora+1 L0080
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asl+1 L0080
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ora [L0080]
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php
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ora #$80
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asl
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phd
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tsb+2 L0086
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ora+2 L0086
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asl+2 L0086
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ora+3 L0089
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bpl @L1041
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@L1041 ora (L0080),y
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ora (L0080)
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ora ($80,S),y
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trb+1 L0080
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ora+1 L0080,x
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asl+1 L0080,x
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ora [L0080],y
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clc
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ora L0086,y
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inc
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tcs
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trb+2 L0086
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ora+2 L0086,x
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asl+2 L0086,x
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ora+3 L0089,x
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jsr L0086
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and (L0080,x)
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jsl L0089
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and $80,S
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bit+1 L0080
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and+1 L0080
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rol+1 L0080
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and [L0080]
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plp
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and #$80
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rol
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pld
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bit+2 L0086
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and+2 L0086
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rol+2 L0086
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and+3 L0089
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bmi @L1089
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@L1089 and (L0080),y
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and (L0080)
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and ($80,S),y
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bit+1 L0080,x
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and+1 L0080,x
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rol+1 L0080,x
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and [L0080],y
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sec
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and L0086,y
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dec
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tsc
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bit+2 L0086,x
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and+2 L0086,x
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rol+2 L0086,x
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and+3 L0089,x
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rti
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L10AB eor (L0080,x)
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!byte $42,$80
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eor $80,S
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mvp $84,$83
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eor+1 L0080
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lsr+1 L0080
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eor [L0080]
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pha
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eor #$80
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lsr
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phk
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jmp @L10C2
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@L10C2 eor+2 L0086
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lsr+2 L0086
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eor+3 L0089
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bvc @L10CE
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@L10CE eor (L0080),y
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eor (L0080)
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eor ($80,S),y
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mvn $84,$83
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eor+1 L0080,x
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lsr+1 L0080,x
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eor [L0080],y
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cli
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eor L0086,y
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phy
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tcd
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jml @L10E7
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@L10E7 eor+2 L0086,x
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lsr+2 L0086,x
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eor+3 L0089,x
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rts
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L10F2 adc (L0080,x)
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per $0ff6
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adc $80,S
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stz+1 L0080
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adc+1 L0080
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ror+1 L0080
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adc [L0080]
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pla
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adc #$80
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ror
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rtl
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L1106 jmp (L0086)
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L1109 adc+2 L0086
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ror+2 L0086
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adc+3 L0089
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bvs @L1115
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@L1115 adc (L0080),y
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adc (L0080)
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adc ($80,S),y
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stz+1 L0080,x
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adc+1 L0080,x
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ror+1 L0080,x
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adc [L0080],y
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sei
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adc L0086,y
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ply
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tdc
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jmp (L0086,x)
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L112C adc+2 L0086,x
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ror+2 L0086,x
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adc+3 L0089,x
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bra @L1138
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@L1138 sta (L0080,x)
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brl @L113D
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@L113D sta $80,S
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sty+1 L0080
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sta+1 L0080
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stx+1 L0080
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sta [L0080]
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dey
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bit #$80
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txa
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phb
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sty+2 L0086
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sta+2 L0086
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stx+2 L0086
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sta+3 L0089
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bcc @L115B
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@L115B sta (L0080),y
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sta (L0080)
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sta ($80,S),y
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sty+1 L0080,x
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sta+1 L0080,x
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stx+1 L0080,y
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sta [L0080],y
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tya
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sta L0086,y
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txs
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txy
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stz+2 L0086
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sta+2 L0086,x
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stz+2 L0086,x
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sta+3 L0089,x
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ldy #$80
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lda (L0080,x)
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ldx #$80
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lda $80,S
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ldy+1 L0080
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lda+1 L0080
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ldx+1 L0080
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lda [L0080]
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tay
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lda #$80
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tax
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plb
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ldy+2 L0086
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lda+2 L0086
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ldx+2 L0086
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lda+3 L0089
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bcs @L11A0
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@L11A0 lda (L0080),y
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lda (L0080)
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lda ($80,S),y
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ldy+1 L0080,x
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lda+1 L0080,x
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ldx+1 L0080,y
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lda [L0080],y
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clv
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lda L0086,y
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tsx
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tyx
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ldy+2 L0086,x
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lda+2 L0086,x
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ldx+2 L0086,y
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lda+3 L0089,x
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cpy #$80
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cmp (L0080,x)
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rep #$00
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cmp $80,S
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cpy+1 L0080
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cmp+1 L0080
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dec+1 L0080
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cmp [L0080]
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iny
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cmp #$80
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dex
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wai
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cpy+2 L0086
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cmp+2 L0086
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dec+2 L0086
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cmp+3 L0089
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bne @L11E5
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@L11E5 cmp (L0080),y
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cmp (L0080)
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cmp ($80,S),y
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pei (L0080)
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cmp+1 L0080,x
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dec+1 L0080,x
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cmp [L0080],y
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cld
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cmp L0086,y
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phx
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stp
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L11F9 jml [L0086]
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L11FC cmp+2 L0086,x
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dec+2 L0086,x
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cmp+3 L0089,x
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cpx #$80
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sbc (L0080,x)
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sep #$00
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sbc $80,S
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cpx+1 L0080
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sbc+1 L0080
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inc+1 L0080
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sbc [L0080]
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inx
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sbc #$80
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nop
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xba
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cpx+2 L0086
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sbc+2 L0086
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inc+2 L0086
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sbc+3 L0089
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beq @L122A
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@L122A sbc (L0080),y
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sbc (L0080)
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sbc ($80,S),y
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pea L0086
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sbc+1 L0080,x
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inc+1 L0080,x
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sbc [L0080],y
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sed
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sbc L0086,y
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plx
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xce
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jsr (L0086,x)
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sbc+2 L0086,x
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inc+2 L0086,x
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sbc+3 L0089,x
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} ;!pseudopc
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!pseudopc $0080 {
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L0080 bit+1 @L0082
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@L0082 bit+1 @L0082
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bit+1 @L0082
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L0086 bit+2 L0086
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L0089 lda+3 L0089
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} ;!pseudopc
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