mirror of https://github.com/fadden/6502bench.git
827 lines
37 KiB
C#
827 lines
37 KiB
C#
/*
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* Copyright 2018 faddenSoft
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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using System;
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using System.Collections.Generic;
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using System.Text;
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namespace Asm65 {
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/// <summary>
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/// Human-readable text describing instructions.
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///
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/// The expectation is that the long description will include information about all
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/// address modes and any differences in behavior between CPUs. So there will be one
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/// entry per instruction mnemonic, and one global table for all CPUs, rather than one
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/// entry per opcode and one instance per CpuDef.
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///
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/// There may, however, be different instances for different Cultures. Also, the 65816
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/// traditionally splits JSR/JSL and JMP/JML, so in that case there will be two entries
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/// for the same instruction.
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/// </summary>
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public class OpDescription {
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private Dictionary<string, string> mShortDescriptions;
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private Dictionary<string, string> mLongDescriptions;
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private Dictionary<OpDef.AddressMode, string> mAddressModeDescriptions;
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private Dictionary<OpDef.CycleMod, string> mCycleModDescriptions;
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private OpDescription(Dictionary<string, string> sd, Dictionary<string, string> ld,
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Dictionary<OpDef.AddressMode, string> am, Dictionary<OpDef.CycleMod, string> cm) {
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mShortDescriptions = sd;
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mLongDescriptions = ld;
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mAddressModeDescriptions = am;
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mCycleModDescriptions = cm;
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}
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/// <summary>
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/// Returns an OpDescription instance for the requested region.
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/// </summary>
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/// <param name="region">TBD</param>
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public static OpDescription GetOpDescription(string region) {
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// ignoring region for now
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return new OpDescription(sShort_enUS, sLong_enUS, sAddrMode_enUS, sCycleMod_enUS);
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}
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/// <summary>
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/// Short description of instruction, e.g. "Load Accumulator".
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/// </summary>
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/// <param name="mnemonic">Instruction mnemonic.</param>
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/// <returns>Short description string, or empty string if not found.</returns>
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public string GetShortDescription(string mnemonic) {
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if (mShortDescriptions.TryGetValue(mnemonic, out string desc)) {
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return desc;
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} else {
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return string.Empty;
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}
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}
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/// <summary>
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/// Long description of instruction. May span multiple lines, with embedded CRLF at
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/// paragraph breaks.
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/// </summary>
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/// <param name="mnemonic">Instruction mnemonic.</param>
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/// <returns>Long description string, or empty string if not found.</returns>
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public string GetLongDescription(string mnemonic) {
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if (mLongDescriptions.TryGetValue(mnemonic, out string desc)) {
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return desc;
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} else {
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return string.Empty;
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}
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}
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/// <summary>
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/// Address mode short description.
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/// </summary>
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/// <param name="addrMode">Address mode to look up.</param>
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/// <returns>Description string, or an empty string for instructions
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/// with implied address modes.</returns>
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public string GetAddressModeDescription(OpDef.AddressMode addrMode) {
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if (mAddressModeDescriptions.TryGetValue(addrMode, out string desc)) {
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return desc;
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} else {
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return string.Empty;
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}
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}
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/// <summary>
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/// Cycle modifier description.
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/// </summary>
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/// <param name="modBit">A single-bit item from the CycleMod enum.</param>
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/// <returns>Description string, or question marks if not found.</returns>
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public string GetCycleModDescription(OpDef.CycleMod modBit) {
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if (mCycleModDescriptions.TryGetValue(modBit, out string desc)) {
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return desc;
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} else {
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return "???";
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}
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}
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/// <summary>
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/// Short descriptions, USA English.
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///
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/// Text is adapted from instruction summaries in Eyes & Lichty, which are slightly
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/// shorter than those in the CPU data sheet.
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/// </summary>
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private static Dictionary<string, string> sShort_enUS = new Dictionary<string, string>() {
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// 65816 instructions.
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{ OpName.ADC, "Add With Carry" },
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{ OpName.AND, "AND Accumulator With Memory" },
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{ OpName.ASL, "Shift Memory or Accumulator Left" },
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{ OpName.BCC, "Branch If Carry Clear" },
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{ OpName.BCS, "Branch If Carry Set" },
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{ OpName.BEQ, "Branch If Equal" },
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{ OpName.BIT, "Test Memory Against Accumulator" },
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{ OpName.BMI, "Branch If Minus" },
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{ OpName.BNE, "Branch If Not Equal" },
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{ OpName.BPL, "Branch If Plus" },
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{ OpName.BRA, "Branch Always" },
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{ OpName.BRK, "Software Break" },
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{ OpName.BRL, "Branch Always Long" },
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{ OpName.BVC, "Branch If Overflow Clear" },
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{ OpName.BVS, "Branch If Overflow Set" },
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{ OpName.CLC, "Clear Carry Flag" },
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{ OpName.CLD, "Clear Decimal Flag" },
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{ OpName.CLI, "Clear Interrupt Disable Flag" },
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{ OpName.CLV, "Clear Overflow Flag" },
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{ OpName.CMP, "Compare Accumulator With Memory" },
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{ OpName.COP, "Co-Processor" },
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{ OpName.CPX, "Compare Index X With Memory" },
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{ OpName.CPY, "Compare Index Y With Memory" },
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{ OpName.DEC, "Decrement Accumulator" },
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{ OpName.DEX, "Decrement Index X" },
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{ OpName.DEY, "Decrement Index Y" },
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{ OpName.EOR, "XOR Accumulator With Memory" },
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{ OpName.INC, "Increment Accumulator" },
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{ OpName.INX, "Increment Index X" },
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{ OpName.INY, "Increment Index Y" },
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{ OpName.JML, "Jump Long" },
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{ OpName.JMP, "Jump" },
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{ OpName.JSL, "Jump to Subroutine Long" },
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{ OpName.JSR, "Jump to Subroutine" },
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{ OpName.LDA, "Load Accumulator from Memory" },
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{ OpName.LDX, "Load Index X from Memory" },
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{ OpName.LDY, "Load Index Y from Memory" },
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{ OpName.LSR, "Logical Shift Memory or Accumulator Right" },
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{ OpName.MVN, "Block Move Next" },
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{ OpName.MVP, "Block Move Previous" },
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{ OpName.NOP, "No Operation" },
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{ OpName.ORA, "OR Accumulator With Memory" },
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{ OpName.PEA, "Push Effective Absolute Address" },
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{ OpName.PEI, "Push Effective Indirect Address" },
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{ OpName.PER, "Push Effective Relative Indirect Address" },
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{ OpName.PHA, "Push Accumulator" },
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{ OpName.PHB, "Push Data Bank Register" },
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{ OpName.PHD, "Push Direct Page Register" },
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{ OpName.PHK, "Push Program Bank Register" },
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{ OpName.PHP, "Push Processor Status Register" },
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{ OpName.PHX, "Push Index Register X" },
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{ OpName.PHY, "Push Index Register Y" },
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{ OpName.PLA, "Pull Accumulator" },
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{ OpName.PLB, "Pull Data Bank Register" },
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{ OpName.PLD, "Pull Direct Page Register" },
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{ OpName.PLP, "Pull Processor Status Register" },
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{ OpName.PLX, "Pull Index Register X" },
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{ OpName.PLY, "Pull Index Register Y" },
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{ OpName.REP, "Reset Status Bits" },
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{ OpName.ROL, "Rotate Memory or Accumulator Left" },
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{ OpName.ROR, "Rotate Memory or Accumulator Right" },
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{ OpName.RTI, "Return from Interrupt" },
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{ OpName.RTL, "Return from Subroutine Long" },
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{ OpName.RTS, "Return from Subroutine" },
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{ OpName.SBC, "Subtract With Borrow" },
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{ OpName.SEC, "Set Carry Flag" },
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{ OpName.SED, "Set Decimal Flag" },
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{ OpName.SEI, "Set Interrupt Disable Flag" },
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{ OpName.SEP, "Set Status Bits" },
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{ OpName.STA, "Store Accumulator to Memory" },
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{ OpName.STP, "Stop Processor" },
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{ OpName.STX, "Store Index X to Memory" },
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{ OpName.STY, "Store Index Y to Memory" },
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{ OpName.STZ, "Store Zero to Memory" },
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{ OpName.TAX, "Transfer Accumulator to Index X" },
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{ OpName.TAY, "Transfer Accumulator to Index Y" },
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{ OpName.TCD, "Transfer 16-Bit Accumulator to Direct Page Register" },
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{ OpName.TCS, "Transfer Accumulator to Stack Pointer" },
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{ OpName.TDC, "Transfer Direct Page Register to 16-Bit Accumulator" },
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{ OpName.TRB, "Test and Reset Memory Bits" },
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{ OpName.TSB, "Test and Set Memory Bits" },
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{ OpName.TSC, "Transfer Stack Pointer to 16-Bit Accumulator" },
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{ OpName.TSX, "Transfer Stack Pointer to Index X" },
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{ OpName.TXA, "Transfer Index X to Accumulator" },
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{ OpName.TXS, "Transfer Index X to Stack Pointer" },
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{ OpName.TXY, "Transfer Index X to Index Y" },
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{ OpName.TYA, "Transfer Index Y to Accumulator" },
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{ OpName.TYX, "Transfer Index Y to Index X" },
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{ OpName.WAI, "Wait for Interrupt" },
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{ OpName.WDM, "Future Expansion" },
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{ OpName.XBA, "Exchange Accumulator B and A" },
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{ OpName.XCE, "Exchange Carry and Emulation Bits" },
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// MOS 6502 undocumented ops
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{ OpName.ALR, "AND and Shift Right" },
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{ OpName.ANC, "AND Accumulator With Value and Set Carry" },
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{ OpName.ANE, "Transfer Index X to Accumulator and AND" },
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{ OpName.ARR, "AND and Rotate Right" },
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{ OpName.DCP, "Decrement and Compare" },
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{ OpName.DOP, "Double-Byte NOP" },
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{ OpName.ISC, "Increment and Subtract" },
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{ OpName.JAM, "Halt CPU" },
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{ OpName.LAS, "Load Acc, X, and Stack Pointer with Memory AND Stack Pointer" },
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{ OpName.LAX, "Load Accumulator and Index X" },
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//{ OpName.LXA, "OR, AND, and Transfer to X" },
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{ OpName.RLA, "Rotate Left and AND" },
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{ OpName.RRA, "Rotate Right and Add" },
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{ OpName.SAX, "Store Accumulator AND Index X" }, // AXS
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{ OpName.SBX, "AND Acc With Index X, Subtract, and Store in X" }, // SAX
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{ OpName.SHA, "AND Acc With Index X and High Byte, and Store" }, // AXA
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{ OpName.SHX, "AND Acc With Index X and High Byte, and Store" }, // XAS
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{ OpName.SHY, "AND Acc With Index Y and High Byte, and Store" }, // SAY
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{ OpName.SLO, "Shift Left and OR" },
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{ OpName.SRE, "Shift right and EOR" },
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{ OpName.TAS, "AND Acc with Index X, Transfer to Stack, AND High Byte" },
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{ OpName.TOP, "Triple-Byte NOP" },
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// WDC 65C02 undocumented
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{ OpName.LDD, "Load and Discard" },
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// Rockwell 65C02 extensions
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{ OpName.BBR0, "Branch on Bit Reset" },
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{ OpName.BBR1, "Branch on Bit Reset" },
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{ OpName.BBR2, "Branch on Bit Reset" },
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{ OpName.BBR3, "Branch on Bit Reset" },
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{ OpName.BBR4, "Branch on Bit Reset" },
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{ OpName.BBR5, "Branch on Bit Reset" },
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{ OpName.BBR6, "Branch on Bit Reset" },
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{ OpName.BBR7, "Branch on Bit Reset" },
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{ OpName.BBS0, "Branch on Bit Set" },
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{ OpName.BBS1, "Branch on Bit Set" },
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{ OpName.BBS2, "Branch on Bit Set" },
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{ OpName.BBS3, "Branch on Bit Set" },
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{ OpName.BBS4, "Branch on Bit Set" },
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{ OpName.BBS5, "Branch on Bit Set" },
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{ OpName.BBS6, "Branch on Bit Set" },
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{ OpName.BBS7, "Branch on Bit Set" },
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{ OpName.RMB0, "Reset Memory Bit" },
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{ OpName.RMB1, "Reset Memory Bit" },
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{ OpName.RMB2, "Reset Memory Bit" },
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{ OpName.RMB3, "Reset Memory Bit" },
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{ OpName.RMB4, "Reset Memory Bit" },
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{ OpName.RMB5, "Reset Memory Bit" },
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{ OpName.RMB6, "Reset Memory Bit" },
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{ OpName.RMB7, "Reset Memory Bit" },
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{ OpName.SMB0, "Set Memory Bit" },
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{ OpName.SMB1, "Set Memory Bit" },
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{ OpName.SMB2, "Set Memory Bit" },
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{ OpName.SMB3, "Set Memory Bit" },
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{ OpName.SMB4, "Set Memory Bit" },
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{ OpName.SMB5, "Set Memory Bit" },
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{ OpName.SMB6, "Set Memory Bit" },
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{ OpName.SMB7, "Set Memory Bit" },
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};
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/// <summary>
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/// Long descriptions, USA English.
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/// </summary>
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private static Dictionary<string, string> sLong_enUS = new Dictionary<string, string>() {
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{ OpName.ADC,
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"Adds the accumulator and a value in memory, storing the result in the " +
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"accumulator. Adds one if the carry is set."
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},
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{ OpName.AND,
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"Performs a bitwise AND of the accumulator with a value in memory, storing " +
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"the result in the accumulator."
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},
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{ OpName.ASL,
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"Shifts memory or the accumulator one bit left. The low bit is set to zero, " +
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"and the carry flag receives the high bit."
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},
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{ OpName.BCC,
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"Branches to a relative address if the processor carry flag (C) is zero. " +
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"Sometimes referred to as Branch If Less Than, or BLT."
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},
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{ OpName.BCS,
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"Branches to a relative address if the processor carry flag (C) is one. " +
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"Sometimes referred to as Branch If Greater Than or Equal, or BGE."
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},
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{ OpName.BEQ,
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"Branches to a relative address if the processor zero flag (Z) is one."
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},
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{ OpName.BIT,
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"Sets processor flags based on the result of two operations. The N and V flags " +
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"are set according to bits 7 and 6, and the Z flag is set based on an AND of " +
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"the accumulator and memory. However, when used with immediate addressing, " +
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"the N and V flags are not affected."
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},
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{ OpName.BMI,
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"Branches to a relative address if the processor negative flag (N) is one."
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},
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{ OpName.BNE,
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"Branches to a relative address if the processor zero flag (Z) is zero."
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},
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{ OpName.BPL,
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"Branches to a relative address if the processor negative flag (N) is zero."
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},
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{ OpName.BRA,
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"Branches to a relative address."
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},
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{ OpName.BRK,
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"Pushes state onto the stack, and jumps to the software break vector at " +
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"$fffe-ffff. While this is technically a single-byte instruction, the " +
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"program counter pushed onto the stack is incremented by two. The interrupt " +
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"flag is set, and on 65C02/65816 the D flag is cleared. " +
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"On 6502, 65C02, and 65816 in emulation mode, the status flags pushed onto " +
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"the stack will have the 'B' flag (which overlaps the 'X' flag) set so the " +
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"interrupt handler can tell the difference between hardware and software " +
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"interrupts."
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},
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{ OpName.BRL,
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"Branches to a long relative address."
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},
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{ OpName.BVC,
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"Branches to a relative address if the processor overflow flag (V) is zero."
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},
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{ OpName.BVS,
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"Branches to a relative address if the processor overflow flag (V) is one."
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},
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{ OpName.CLC,
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"Sets the processor carry flag (C) to zero."
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},
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{ OpName.CLD,
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"Sets the processor decimal flag (D) to zero."
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},
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{ OpName.CLI,
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"Sets the processor interrupt disable flag (I) to zero."
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},
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{ OpName.CLV,
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"Sets the processor overflow flag (V) to zero."
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},
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{ OpName.CMP,
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"Subtracts the value specified by the operand from the contents of the " +
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"accumulator. Sets the carry, zero, and negative flags, but does not alter " +
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"memory or the accumulator."
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},
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{ OpName.COP,
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"Pushes state onto the stack, and jumps to the software interrupt vector at " +
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"$fff4-fff5."
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},
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{ OpName.CPX,
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"Subtracts the value specified by the operand from the contents of the " +
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"X register. Sets the carry, zero, and negative flags, but does not alter " +
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"memory or the X register."
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},
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{ OpName.CPY,
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"Subtracts the value specified by the operand from the contents of the " +
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"Y register. Sets the carry, zero, and negative flags, but does not alter " +
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"memory or the Y register."
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},
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{ OpName.DEC,
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"Decrements the contents of the location specified by the operand by one."
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},
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{ OpName.DEX,
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"Decrements the X register by one."
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},
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{ OpName.DEY,
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"Decrements the Y register by one."
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},
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{ OpName.EOR,
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"Performs a bitwise EOR of the accumulator with a value in memory, storing " +
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"the result in the accumulator."
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},
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{ OpName.INC,
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"Increments the contents of the location specified by the operand by one."
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},
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{ OpName.INX,
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"Increments the X register by one."
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},
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{ OpName.INY,
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"Increments the Y register by one."
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},
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{ OpName.JML,
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"Branches to a long absolute address."
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},
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{ OpName.JMP,
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"Branches to an absolute address."
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},
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{ OpName.JSL,
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"Branches to a long absolute address after pushing the current address onto " +
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"the stack. The value pushed is the address of the last operand byte."
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},
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{ OpName.JSR,
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"Branches to an absolute address after pushing the current address onto " +
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"the stack. The value pushed is the address of the last operand byte."
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},
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{ OpName.LDA,
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"Loads the accumulator from memory."
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},
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{ OpName.LDX,
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"Loads the X register from memory."
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},
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{ OpName.LDY,
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"Loads the Y register from memory."
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},
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{ OpName.LSR,
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"Shifts memory or the accumulator one bit right. The high bit is set to zero, " +
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"and the carry flag receives the low bit."
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},
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{ OpName.MVN,
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"Moves a block of memory, starting from a low address and incrementing. " +
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"The source and destination addresses are in the X and Y registers, " +
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"respectively. The accumulator holds the number of bytes to move minus 1, " +
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"and the source and destination banks are specified by the operands."
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},
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{ OpName.MVP,
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"Moves a block of memory, starting from a high address and decrementing. " +
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"The source and destination addresses are in the X and Y registers, " +
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"respectively. The accumulator holds the number of bytes to move minus 1, " +
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"and the source and destination banks are specified by the operands."
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},
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{ OpName.NOP,
|
|
"No operation."
|
|
},
|
|
{ OpName.ORA,
|
|
"Performs a bitwise OR of the accumulator with a value in memory, storing " +
|
|
"the result in the accumulator."
|
|
},
|
|
{ OpName.PEA,
|
|
"Pushes the 16-bit operand onto the stack. This always pushes two bytes, " +
|
|
"regardless of the M/X processor flags."
|
|
},
|
|
{ OpName.PEI,
|
|
"Pushes a 16-bit value from the direct page onto the stack."
|
|
},
|
|
{ OpName.PER,
|
|
"Converts a relative offset to an absolute address, and pushes it onto the stack."
|
|
},
|
|
{ OpName.PHA,
|
|
"Pushes the accumulator onto the stack."
|
|
},
|
|
{ OpName.PHB,
|
|
"Pushes the data bank register onto the stack."
|
|
},
|
|
{ OpName.PHD,
|
|
"Pushes the direct page register onto the stack."
|
|
},
|
|
{ OpName.PHK,
|
|
"Pushes the program bank register onto the stack."
|
|
},
|
|
{ OpName.PHP,
|
|
"Pushes the processor status register onto the stack."
|
|
},
|
|
{ OpName.PHX,
|
|
"Pushes the X register onto the stack."
|
|
},
|
|
{ OpName.PHY,
|
|
"Pushes the Y register onto the stack."
|
|
},
|
|
{ OpName.PLA,
|
|
"Pulls the accumulator off of the stack."
|
|
},
|
|
{ OpName.PLB,
|
|
"Pulls the data bank register off of the stack."
|
|
},
|
|
{ OpName.PLD,
|
|
"Pulls the direct page register off of the stack."
|
|
},
|
|
{ OpName.PLP,
|
|
"Pulls the processor status register off of the stack."
|
|
},
|
|
{ OpName.PLX,
|
|
"Pulls the X register off of the stack."
|
|
},
|
|
{ OpName.PLY,
|
|
"Pulls the Y register off of the stack."
|
|
},
|
|
{ OpName.REP,
|
|
"Sets specific bits in the processor status register to zero."
|
|
},
|
|
{ OpName.ROL,
|
|
"Rotates memory or the accumulator one bit left. The low bit is set to the " +
|
|
"carry flag, and the carry flag receives the high bit."
|
|
},
|
|
{ OpName.ROR,
|
|
"Rotates memory or the accumulator one bit right. The high bit is set to the " +
|
|
"carry flag, and the carry flag receives the low bit."
|
|
},
|
|
{ OpName.RTI,
|
|
"Pulls the status register and return address from the stack, and jumps " +
|
|
"to the exact address pulled (note this is different from RTL/RTS)."
|
|
},
|
|
{ OpName.RTL,
|
|
"Pulls the 24-bit return address from the stack, increments it, and jumps to it."
|
|
},
|
|
{ OpName.RTS,
|
|
"Pulls the 16-bit return address from the stack, increments it, and jumps to it."
|
|
},
|
|
{ OpName.SBC,
|
|
"Subtracts the value specified by the operand from the contents of the " +
|
|
"accumulator, and leaves the result in the accumulator. Sets the carry, " +
|
|
"zero, and negative flags."
|
|
},
|
|
{ OpName.SEC,
|
|
"Sets the processor carry flag (C) to one."
|
|
},
|
|
{ OpName.SED,
|
|
"Sets the processor decimal flag (D) to one."
|
|
},
|
|
{ OpName.SEI,
|
|
"Sets the processor interrupt disable flag (I) to one."
|
|
},
|
|
{ OpName.SEP,
|
|
"Sets specific bits in the processor status register to one."
|
|
},
|
|
{ OpName.STA,
|
|
"Stores the value in the accumulator into memory."
|
|
},
|
|
{ OpName.STP,
|
|
"Stops the processor until a CPU reset occurs."
|
|
},
|
|
{ OpName.STX,
|
|
"Stores the value in the X register into memory."
|
|
},
|
|
{ OpName.STY,
|
|
"Stores the value in the Y register into memory."
|
|
},
|
|
{ OpName.STZ,
|
|
"Stores zero into memory."
|
|
},
|
|
{ OpName.TAX,
|
|
"Transfers the contents of the accumulator to the X register."
|
|
},
|
|
{ OpName.TAY,
|
|
"Transfers the contents of the accumulator to the Y register."
|
|
},
|
|
{ OpName.TCD,
|
|
"Transfers the 16-bit accumulator to the direct page register."
|
|
},
|
|
{ OpName.TCS,
|
|
"Transfers the 16-bit accumulator to the stack pointer register."
|
|
},
|
|
{ OpName.TDC,
|
|
"Transfers the direct page register to the 16-bit accumulator."
|
|
},
|
|
{ OpName.TRB,
|
|
"Logically ANDs the complement of the value in the accumulator with a value " +
|
|
"in memory, and stores it in memory. This can be used to clear specific bits " +
|
|
"in memory."
|
|
},
|
|
{ OpName.TSB,
|
|
"Logically ORs the value in the accumulator with a value in memory, and " +
|
|
"stores it in memory. This can be used to set specific bits in memory."
|
|
},
|
|
{ OpName.TSC,
|
|
"Transfers the stack pointer register to the 16-bit accumulator."
|
|
},
|
|
{ OpName.TSX,
|
|
"Transfers the stack pointer register to the X register."
|
|
},
|
|
{ OpName.TXA,
|
|
"Transfers the X register to the accumulator."
|
|
},
|
|
{ OpName.TXS,
|
|
"Transfers the X register to the stack pointer register."
|
|
},
|
|
{ OpName.TXY,
|
|
"Transfers the X register to the Y register."
|
|
},
|
|
{ OpName.TYA,
|
|
"Transfers the Y register to the accumulator."
|
|
},
|
|
{ OpName.TYX,
|
|
"Transfers the Y register to the X register."
|
|
},
|
|
{ OpName.WAI,
|
|
"Stalls the processor until an interrupt is received. If the interrupt " +
|
|
"disable flag (I) is set to one, execution will continue with the next " +
|
|
"instruction rather than calling through an interrupt vector."
|
|
},
|
|
{ OpName.WDM,
|
|
"Reserved for future expansion. (Behaves as a two-byte NOP.)"
|
|
},
|
|
{ OpName.XBA,
|
|
"Swaps the high and low bytes in the 16-bit accumulator. Sometimes referred " +
|
|
"to as SWA."
|
|
},
|
|
{ OpName.XCE,
|
|
"Exchanges carry and emulation bits."
|
|
},
|
|
|
|
//
|
|
// 6502 undocumented instructions.
|
|
//
|
|
// (See OpDef for a list of references.)
|
|
//
|
|
{ OpName.ANC,
|
|
"AND byte with accumulator. If result is negative then carry is set." +
|
|
"\r\n\r\nAlt mnemonic: AAC"
|
|
},
|
|
{ OpName.ANE,
|
|
"Transfer X register to accumulator, then AND accumulator with value. " +
|
|
"This opcode is unstable." +
|
|
"\r\n\r\nAlt mnemonic: XAA"
|
|
},
|
|
{ OpName.ARR,
|
|
"AND byte with accumulator, then rotate one bit right. Equivalent to " +
|
|
"AND + ROR."
|
|
},
|
|
{ OpName.ALR,
|
|
"AND byte with accumulator, then shift right one bit. Equivalent to AND + LSR." +
|
|
"\r\n\r\nAlt mnemonic: ASR"
|
|
},
|
|
{ OpName.DCP,
|
|
"Decrement memory location, then compare result to accumulator. Equivalent " +
|
|
"to DEC + CMP." +
|
|
"\r\n\r\nAlt mnemonic: DCM"
|
|
},
|
|
{ OpName.DOP,
|
|
"Double-byte no-operation." +
|
|
"\r\n\r\nAlt mnemonic: NOP / SKB"
|
|
},
|
|
{ OpName.ISC,
|
|
"Increment memory, then subtract memory from accumulator with borrow. " +
|
|
"Equivalent to INC + SBC." +
|
|
"\r\n\r\nAlt mnemonic: ISC / INS"
|
|
},
|
|
{ OpName.JAM,
|
|
"Crash the CPU, halting execution and ignoring interrupts." +
|
|
"\r\n\r\nAlt mnemonic: KIL / JAM"
|
|
},
|
|
{ OpName.LAS,
|
|
"AND memory with stack pointer, then transfer result to accumulator, " +
|
|
"X register, and stack pointer. (Note: possibly unreliable.)" +
|
|
"\r\n\r\nAlt mnemonic: LAE / LAR"
|
|
},
|
|
{ OpName.LAX,
|
|
"Load accumulator and X register from memory. Equivalent to LDA + LDX." +
|
|
"\r\n\r\nThe immediate mode is unstable. It " +
|
|
/*},
|
|
{ OpName.LXA,*/
|
|
"ORs accumulator with a value, ANDs result with immediate value, then stores " +
|
|
"the result in accumulator and X register. " +
|
|
"Equivalent to ORA + AND + TAX." +
|
|
"\r\n\r\nAlt mnemonic: LXA / ATX / OAL"
|
|
},
|
|
{ OpName.RLA,
|
|
"Rotate memory one bit left, then AND accumulator with memory. Equivalent " +
|
|
"to ROL + AND."
|
|
},
|
|
{ OpName.RRA,
|
|
"Rotate memory one bit right, then add accumulator to memory with carry. " +
|
|
"Equivalent to ROR + ADC."
|
|
},
|
|
{ OpName.SAX,
|
|
"AND X register with accumulator, without changing the contents of either " +
|
|
"register, subtract an immediate value, then store result in X register." +
|
|
"\r\n\r\nAlt mnemonic: AAX / AXS"
|
|
},
|
|
{ OpName.SBX,
|
|
"AND X register with accumulator and transfer to X register, then " +
|
|
"subtract byte from X register without borrow." +
|
|
"\r\n\r\nAlt mnemonic: AXS / SAX"
|
|
},
|
|
{ OpName.SHA,
|
|
"AND X register with accumulator, then AND result with 7 and store." +
|
|
"\r\n\r\nAlt mnemonic: AHX, AXA"
|
|
},
|
|
{ OpName.SHX,
|
|
"AND X register with the high byte of the argument + 1, and store the result." +
|
|
"\r\n\r\nAlt mnemonic: SXA / XAS"
|
|
},
|
|
{ OpName.SHY,
|
|
"AND Y register with the high byte of the argument + 1, and store the result." +
|
|
"\r\n\r\nAlt mnemonic: SYA / SAY"
|
|
},
|
|
{ OpName.SLO,
|
|
"Shift memory left one bit, then OR accumulator with memory. Equivalent to " +
|
|
"ASL + ORA." +
|
|
"\r\n\r\nAlt mnemonic: ASO"
|
|
},
|
|
{ OpName.SRE,
|
|
"Shift memory right one bit, then EOR accumulator with memory. Equivalent to " +
|
|
"LSR + EOR." +
|
|
"\r\n\r\nAlt mnemonic: LSE"
|
|
},
|
|
{ OpName.TAS,
|
|
"AND X register with accumulator, without changing the contents of either " +
|
|
"register, and transfer to stack pointer. Then " +
|
|
"AND stack pointer with high byte of operand + 1." +
|
|
"\r\n\r\nAlt mnemonic: SHS / XAS"
|
|
},
|
|
{ OpName.TOP,
|
|
"Triple-byte no-operation. This actually performs a load." +
|
|
"\r\n\r\nAlt mnemonic: NOP / SKW"
|
|
},
|
|
|
|
//
|
|
// 65C02 undocumented instructions.
|
|
//
|
|
{ OpName.LDD,
|
|
"Load and Discard. Usually a no-op, but the activity on the address bus " +
|
|
"can affect memory-mapped I/O."
|
|
},
|
|
|
|
//
|
|
// Rockwell 65C02 extensions.
|
|
//
|
|
{ OpName.BBR0, BBR_DESC },
|
|
{ OpName.BBR1, BBR_DESC },
|
|
{ OpName.BBR2, BBR_DESC },
|
|
{ OpName.BBR3, BBR_DESC },
|
|
{ OpName.BBR4, BBR_DESC },
|
|
{ OpName.BBR5, BBR_DESC },
|
|
{ OpName.BBR6, BBR_DESC },
|
|
{ OpName.BBR7, BBR_DESC },
|
|
{ OpName.BBS0, BBS_DESC },
|
|
{ OpName.BBS1, BBS_DESC },
|
|
{ OpName.BBS2, BBS_DESC },
|
|
{ OpName.BBS3, BBS_DESC },
|
|
{ OpName.BBS4, BBS_DESC },
|
|
{ OpName.BBS5, BBS_DESC },
|
|
{ OpName.BBS6, BBS_DESC },
|
|
{ OpName.BBS7, BBS_DESC },
|
|
{ OpName.RMB0, RMB_DESC },
|
|
{ OpName.RMB1, RMB_DESC },
|
|
{ OpName.RMB2, RMB_DESC },
|
|
{ OpName.RMB3, RMB_DESC },
|
|
{ OpName.RMB4, RMB_DESC },
|
|
{ OpName.RMB5, RMB_DESC },
|
|
{ OpName.RMB6, RMB_DESC },
|
|
{ OpName.RMB7, RMB_DESC },
|
|
{ OpName.SMB0, SMB_DESC },
|
|
{ OpName.SMB1, SMB_DESC },
|
|
{ OpName.SMB2, SMB_DESC },
|
|
{ OpName.SMB3, SMB_DESC },
|
|
{ OpName.SMB4, SMB_DESC },
|
|
{ OpName.SMB5, SMB_DESC },
|
|
{ OpName.SMB6, SMB_DESC },
|
|
{ OpName.SMB7, SMB_DESC },
|
|
};
|
|
|
|
private const string BBR_DESC =
|
|
"Branches to a relative address if the specified bit in memory is zero.";
|
|
private const string BBS_DESC =
|
|
"Branches to a relative address if the specified bit in memory is one.";
|
|
private const string RMB_DESC =
|
|
"Clears a bit in memory.";
|
|
private const string SMB_DESC =
|
|
"Sets a bit in memory.";
|
|
|
|
|
|
/// <summary>
|
|
/// Address mode short descriptions, USA English.
|
|
/// </summary>
|
|
private static Dictionary<OpDef.AddressMode, string> sAddrMode_enUS =
|
|
new Dictionary<OpDef.AddressMode, string>() {
|
|
{ OpDef.AddressMode.Abs, "Absolute" },
|
|
{ OpDef.AddressMode.AbsInd, "Absolute Indirect" },
|
|
{ OpDef.AddressMode.AbsIndLong, "Absolute Indirect Long" },
|
|
{ OpDef.AddressMode.AbsIndexX, "Absolute Indexed X" },
|
|
{ OpDef.AddressMode.AbsIndexXInd, "Absolute Indexed X Indirect" },
|
|
{ OpDef.AddressMode.AbsIndexXLong, "Absolute Indexed X Long" },
|
|
{ OpDef.AddressMode.AbsIndexY, "Absolute Indexed Y" },
|
|
{ OpDef.AddressMode.AbsLong, "Absolute Long" },
|
|
{ OpDef.AddressMode.Acc, "Accumulator" },
|
|
{ OpDef.AddressMode.BlockMove, "Block Move" },
|
|
{ OpDef.AddressMode.DP, "Direct Page" },
|
|
{ OpDef.AddressMode.DPInd, "Direct Page Indirect" },
|
|
{ OpDef.AddressMode.DPIndIndexY, "Direct Page Indirect Indexed Y" },
|
|
{ OpDef.AddressMode.DPIndIndexYLong, "Direct Page Indirect Indexed Y Long" },
|
|
{ OpDef.AddressMode.DPIndLong, "Direct Page Indirect Long" },
|
|
{ OpDef.AddressMode.DPIndexX, "Direct Page Indexed X" },
|
|
{ OpDef.AddressMode.DPIndexXInd, "Direct Page Indexed X Indirect" },
|
|
{ OpDef.AddressMode.DPIndexY, "Direct Page Indexed Y" },
|
|
{ OpDef.AddressMode.DPPCRel, "Direct Page / PC Relative" },
|
|
{ OpDef.AddressMode.Imm, "Immediate" },
|
|
{ OpDef.AddressMode.ImmLongA, "Immediate" },
|
|
{ OpDef.AddressMode.ImmLongXY, "Immediate" },
|
|
{ OpDef.AddressMode.Implied, "" },
|
|
{ OpDef.AddressMode.PCRel, "PC Relative" },
|
|
{ OpDef.AddressMode.PCRelLong, "PC Relative Long" },
|
|
{ OpDef.AddressMode.StackAbs, "Stack Absolute" },
|
|
{ OpDef.AddressMode.StackDPInd, "Stack Direct Page Indirect" },
|
|
{ OpDef.AddressMode.StackInt, "" },
|
|
{ OpDef.AddressMode.StackPCRelLong, "Stack PC Relative Long" },
|
|
{ OpDef.AddressMode.StackPull, "" },
|
|
{ OpDef.AddressMode.StackPush, "" },
|
|
{ OpDef.AddressMode.StackRTI, "" },
|
|
{ OpDef.AddressMode.StackRTL, "" },
|
|
{ OpDef.AddressMode.StackRTS, "" },
|
|
{ OpDef.AddressMode.StackRel, "Stack Relative" },
|
|
{ OpDef.AddressMode.StackRelIndIndexY, "Stack Relative Indirect Index Y" },
|
|
{ OpDef.AddressMode.WDM, "" }
|
|
};
|
|
|
|
/// <summary>
|
|
/// Cycle modifier descriptions. These are intended to be very terse.
|
|
/// </summary>
|
|
private static Dictionary<OpDef.CycleMod, string> sCycleMod_enUS =
|
|
new Dictionary<OpDef.CycleMod, string>() {
|
|
{ OpDef.CycleMod.OneIfM0, "+1 if M=0" },
|
|
{ OpDef.CycleMod.TwoIfM0, "+2 if M=0" },
|
|
{ OpDef.CycleMod.OneIfX0, "+1 if X=0" },
|
|
{ OpDef.CycleMod.OneIfDpNonzero, "+1 if DL != 0" },
|
|
{ OpDef.CycleMod.OneIfIndexPage, "+1 if index across page" },
|
|
{ OpDef.CycleMod.OneIfD1, "+1 if D=1 on 65C02" },
|
|
{ OpDef.CycleMod.OneIfBranchTaken, "+1 if branch taken" },
|
|
{ OpDef.CycleMod.OneIfBranchPage, "+1 if branch across page unless E=0" },
|
|
{ OpDef.CycleMod.OneIfE0, "+1 if E=0" },
|
|
{ OpDef.CycleMod.OneIf65C02, "+1 if 65C02" },
|
|
{ OpDef.CycleMod.MinusOneIfNoPage, "-1 if 65C02 and not across page" },
|
|
{ OpDef.CycleMod.BlockMove, "+7 per byte" },
|
|
};
|
|
}
|
|
}
|