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https://github.com/fadden/6502bench.git
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99cd0d3ac1
C64 PRG files are pretty common. Their salient feature is that they start with a 16-bit value that is used as the load address. The value is commonly generated by the assembler itself, rather than explicitly added to the source file. Not all assemblers know what a PRG file is, and some of them handle it in ways that are difficult to guarantee in SourceGen. ACME adds the 16-bit header when the output file name ends in ".prg", cc65 uses a modified config file, 64tass uses a different command-line option, and Merlin 32 has no idea what they are. This change adds PRG file detection and handling to the 64tass code generator. Doing so required making a few changes to the gen/asm interfaces, because we now need to have the generator pass additional flags to the assembler, and sometimes we need code generation to start somewhere other than offset zero. Overall the changes were pretty minor. The 20042-address-changes test needed a 6502-only variant. A new test (20040-address-changes) has been added and given a PRG header. As part of this change the 65816 variant was changed to use addresses in bank 2, which uncovered a code generation bug that this change also fixes. The 64tass --long-address flag doesn't appear to be necessary for files <= 65536 bytes long, so we no longer emit it for those. (issue #90)
125 lines
2.4 KiB
ArmAsm
125 lines
2.4 KiB
ArmAsm
!cpu 6502
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* = $0000
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!pseudopc $1000 {
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!word $1000 ;PRG-style header
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} ;!pseudopc
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!pseudopc $1000 {
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jsr L1100
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jsr L1107
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jmp L2000
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} ;!pseudopc
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!pseudopc $1100 {
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L1100 bit L1100
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L1103 lda #$11
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ldx #$11
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L1107 ldy #$11
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clv
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bvc L1103
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} ;!pseudopc
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!pseudopc $1100 {
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@L1100_0 bit @L1100_0
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lda #$22
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@L1105 ldx #$22
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ldy #$22
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jmp @L1105
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} ;!pseudopc
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!pseudopc $1100 {
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@L1100_1 bit @L1100_1
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lda #$33
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ldx #$33
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@L1107_0 ldy #$33
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sec
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bcs @L1107_0
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} ;!pseudopc
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!pseudopc $2000 {
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L2000 bit L2000
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beq $2018
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bne @L2020
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} ;!pseudopc
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!pseudopc $2020 {
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@L2020 bit @L2020
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beq $2028
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bne L2080
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offend nop
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} ;!pseudopc
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!pseudopc $2080 {
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L2080 bit L2080
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lda offend
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jsr offend
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lda $2028
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jsr $2028
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lda L2080-1
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jsr L2080-1
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lda L2080
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jsr L2080
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lda $00
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beq @L2100
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!byte $ad
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} ;!pseudopc
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!pseudopc $2100 {
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@L2100 nop
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nop
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jmp @L3000
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} ;!pseudopc
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!pseudopc $2800 {
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!byte $00
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!byte $28
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!fill 14,$00
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} ;!pseudopc
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!pseudopc $2820 {
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!fill 18,$00
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} ;!pseudopc
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!pseudopc $3000 {
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@L3000 bit @L3000
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lda #$44
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ldx #$44
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ldy #$44
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jmp fwd
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ulabel !byte $00
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!byte $01
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} ;!pseudopc
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!pseudopc $3100 {
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!byte $02
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fwd bit fwd
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lda ulabel
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lda ulabel+1
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lda $300e
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lda $300f
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lda fwd-1
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beq @L3182
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!byte $ea
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!byte $ea
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} ;!pseudopc
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!pseudopc $3180 {
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!byte $00
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!byte $01
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@L3182 bit @L3182
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lda label1
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lda label1+1
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lda L3200
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clv
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bvc L3200
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label1 !byte $ea
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!byte $ea
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} ;!pseudopc
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!pseudopc $3200 {
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L3200 bit L3200
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!byte $00
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!byte $01 ;execution continues off end of file
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} ;!pseudopc
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