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6502bench/SourceGen/SGTestData/Expected/20162-cycle-counts-65816_cc65.S
Andy McFadden 39b7b20144 ORG rework, part 1
This is the first step toward changing the address region map from a
linear list to a hierarchy.  See issue #107 for the plan.

The AddressMap class has been rewritten to support the new approach.
The rest of the project has been updated to conform to the new API,
but feature-wise is unchanged.  While the map class supports
nested regions with explicit lengths, the rest of the application
still assumes a series of non-overlapping regions with "floating"
lengths.

The Set Address dialog is currently non-functional.

All of the output for cc65 changed because generation of segment
comments has been removed.  Some of the output for ACME changed as
well, because we no longer follow "* = addr" with a redundant
pseudopc statement.  ACME and 65tass have similar approaches to
placing things in memory, and so now have similar implementations.
2021-09-16 17:02:19 -07:00

80 lines
2.0 KiB
ArmAsm

.setcpu "65816"
.org $10f0
.a8
.i8
L10F0: sec ;2
xce ;2
bra @L1108 ;4 crosses page boundary
.res 20,$00
@L1108: bra @L110A ;3
@L110A: lda #$00 ;2
beq @L1110 ;3 branch always
.byte $00
.byte $00
@L1110: bne @L1110 ;2 branch never
lda $1234 ;4
beq @L1119 ;2+ branch maybe
brk ;7 BRK with E=1
.byte $01
@L1119: lda $22,S ;4
trb $02 ;5+
asl $03,x ;6+
clc ;2
xce ;2
rep #$30 ;3
.a16
.i16
lda #$0011 ;3
ldy #$0022 ;3
trb $04 ;7+
asl $05,x ;8+
ldx $1235 ;5
beq @L1134 ;2+
brk ;8 BRK with E=0
.byte $02
@L1134: lda $33,S ;5
beq @L113A ;2+
bra L10F0 ;3
@L113A: rep #$20 ;3
sep #$10 ;3
.i8
sta $10 ;4+
stx $11 ;3+
sty $12 ;3+
rep #$10 ;3
.i16
sep #$20 ;3
.a8
sta $11 ;3+
stx $12 ;4+
sty $13 ;4+
rep #$30 ;3
.a16
lda $1234 ;5
adc #$0066 ;3
adc $1235 ;5
sed ;2 should have no effect on cycle counts on 65816
adc #$0077 ;3
adc $1236 ;5
sec ;2
xce ;2
.a8
.i8
sbc #$88 ;2
sbc $1237 ;4
cld ;2
sbc #$99 ;2
sbc $1238 ;4
rts ;6