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17dc908420
Tests 10022-embedded-instructions and 10032-flags-and-branches were a mix of 6502 and 65816 code. The 6502 code has been separated into its own file, so that the tests can be run on 8-bit-only assemblers.
165 lines
3.7 KiB
ArmAsm
165 lines
3.7 KiB
ArmAsm
; Copyright 2018 faddenSoft. All Rights Reserved.
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; See the LICENSE.txt file for distribution terms (Apache 2.0).
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;
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; Assembler: Merlin 32
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; 6502 version
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org $1000
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; clear individual flags with instructions
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; (this has no effect on the assembled output, but you can see the
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; effects on the "status" column in the display list)
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clv
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cld
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cli
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clc
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lda #$80 ;clear Z
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lda #$01 ;clear N
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sed
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sei
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sec
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lda #$ff ;set N
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adc #$00 ;set V, Z (actually scrambles NVZC)
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; check branch instructions as best we can; NVMXDIZC
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lda #$00
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pha
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plp ;without a nearby PHP, flags will be scrambled
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ok_bmi clv
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bvc ok_bvc
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bvs ok_bvs
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brk $00
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ok_bvc
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ok_bvs clc
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bcc ok_bcc
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brk $00
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ok_bcc sec
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bcs ok_bcs
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brk $00
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ok_bcs
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; check NZ flags set by immediate load
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lda #$01
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bne ok_nzero
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brk $db
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ok_nzero
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lda #$00
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beq ok_zero
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brk $db
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ok_zero
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bpl ok_pos
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brk $db
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ok_pos
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lda #$80
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bmi ok_neg
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brk $db
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ok_neg
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; check NZ flags set by immediate AND; only $00 / <=$7f have meaning
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lda #$ff
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and #$00
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beq ok_andZ1
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brk $db
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ok_andZ1
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lda #$00
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ldx #$80
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and #$ff
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beq ok_andZ1A
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bne ok_andZ1A
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ok_andZ1A
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lda #$ff
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ldx #$00
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and #$7f
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beq ok_andZ0
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bne ok_andZ0
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ok_andZ0
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bpl ok_andN0
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brk $db
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ok_andN0
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lda #$ff
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and #$80
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bpl ok_andN1
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bmi ok_andN1
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brk $db
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ok_andN1
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; check NZ flags set by immediate ORA; only nonzero / >=$80 have meaning
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lda #$00
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ldx #$80
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bne :next1
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brk $db
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:next1 ora #$00 ;can't know what A-reg holds, so Z=indeterminate
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beq ok_oraZ1
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bne ok_oraZ1
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ok_oraZ1
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ora #$01
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bne ok_oraZ0
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brk $db
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ok_oraZ0
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lda #$00
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ldx #$80
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bmi :next2
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brk $db
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:next2 ora #$7f ;N-flag clear, but analyzer doesn't know,
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bpl ok_oraN0 ; so both of these are considered viable
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bmi ok_oraN0
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brk $db
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ok_oraN0
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ora #$80
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bmi ok_oraN1
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brk $db
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ok_oraN1
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; check rol/ror
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:foo lda :foo ;scramble N/V
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sec
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ror A ;rotates the carry into the hi bit (N)
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bmi ok_ror1
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brk $dc
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ok_ror1
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clc
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ror A ;now try with carry clear
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bpl ok_ror2
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brk $dc
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ok_ror2
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lda #$00 ;set Z=1
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sec
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rol A ;set Z=0 (could also set C=0)
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bne ok_rol1
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brk $dc
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ok_rol1
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; check lsr
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lda #$ff
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lsr A ;lsr always clears the high bit
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bpl ok_lsr
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brk $dd
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ok_lsr
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; simple "smart" plp test, changes state according to default
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clc
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php
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sec
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plp ;"smart" restores carry
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bcc ok_plp ; and makes this a branch-always
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nop ;non-smart is indeterminate
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ok_plp
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; regression test for bug in analyzer
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sec ;here carry is clear
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bcs flg2
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flg1 clc
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flg2 lda $33
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beq flg1
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bcs flg3 ;this should NOT be branch-always
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lda $44
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flg3 nop
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done
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rts
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