mirror of
https://github.com/fadden/6502bench.git
synced 2024-08-20 11:28:58 +00:00
Added support for "relative" address regions to the Merlin 32 and cc65 code generators. These generate "flat" address directives, and so were a little more complicated. Suppressed generation of relative operands for non-addressable regions. Also, tweaked the 20250-nested-regions test to include a negative relative region offset.
94 lines
1.8 KiB
ArmAsm
94 lines
1.8 KiB
ArmAsm
.setcpu "6502"
|
|
.org $0000
|
|
.word $3000 ;load address
|
|
|
|
.org $1000
|
|
.org *+$1000
|
|
.org *+$1000
|
|
L3000: bit L3000
|
|
@L3003: lda @L3003
|
|
and @LE003
|
|
jmp @L200C
|
|
|
|
.org $200c
|
|
@L200C: bit @L200C
|
|
jmp @L1012
|
|
|
|
.org $1012
|
|
@L1012: bit @L1012
|
|
jsr @L4000
|
|
.org $0000
|
|
.byte $00
|
|
.byte $ce,$55,$4c,$4c,$2d,$54,$45,$52,$4d,$20,$d0,$c5,$d4,$d3,$c3,$c9
|
|
.byte $c9,$20,$53,$54,$52,$49,$4e,$47,$00
|
|
.byte $80
|
|
.word @L3003
|
|
.word @LE003
|
|
.byte $80
|
|
|
|
.org $4000
|
|
@L4000: bit @L4000
|
|
bit @L5000
|
|
bit @L500F
|
|
bit @L500F
|
|
nop
|
|
jmp @L4020
|
|
|
|
.org $5000
|
|
@L5000: bit @L5000
|
|
bit @L4000
|
|
nop
|
|
nop
|
|
@L5008: bit @L5008
|
|
bit @L5017
|
|
nop
|
|
@L500F: rts
|
|
|
|
.org $4020
|
|
@L4020: bit @L4020
|
|
bit @L500F
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
jmp @L4040
|
|
|
|
.org $5008
|
|
@L5008_0: bit @L5008_0
|
|
bit @L5000
|
|
nop
|
|
@L500F_0: bit @L500F_0
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
@L5017: rts
|
|
|
|
.org $4040
|
|
@L4040: bit @L4040
|
|
bit @L5017
|
|
nop
|
|
jmp @LE000
|
|
|
|
.org $1082
|
|
.org *+$cf7e
|
|
@LE000: bit @L200C
|
|
@LE003: nop
|
|
jmp @LD000
|
|
|
|
.org *-$1007
|
|
@LD000: bit @LD000
|
|
jmp @LF000
|
|
|
|
.org $f000
|
|
@LF000: bit @LF000
|
|
lda @L3003
|
|
and @LE003
|
|
nop
|
|
rts
|
|
|