mirror of
https://github.com/fadden/6502bench.git
synced 2024-05-31 22:41:37 +00:00
f3d255c1a9
Added an address mask to support mirroring of I/O registers. Changed to specify the access direction of address. Fixed a definition with different addresses but duplicate label names. (`OAMDATA`, `VMDATAL`, `VMDATAH`, `CGDATA`)
249 lines
18 KiB
Plaintext
249 lines
18 KiB
Plaintext
; 6502bench SNES CPU, PPU registers symbol
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; Reference:
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; Super Nintendo Entertainment System Development Manual
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; Registers | Super Famicom Development Wiki
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; https://wiki.superfamicom.org/registers
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; Memory map - SNESdev Wiki
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; https://snes.nesdev.org/wiki/Memory_map
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; Copyright 2021-2022 absindx
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; Follow the original license. (Apache 2.0)
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*SYNOPSIS Super NES registers
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; I/O registers $xx2000
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; bank = $00-$3F, $80-$BF
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; page = $2000-$6F00
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; %?0??????xxxxxxxxxxxxxxxx
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; %010000000000000000000000 CompareMask (0/1)
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; %000000000000000000000000 CompareValue (1)
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; %000000001111111111111111 AddressMask (x)
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*MULTI_MASK %010000000000000000000000 %000000000000000000000000 %000000001111111111111111
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; PPU registers (Address Bus B)
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INIDISP > $2100 ;W B--- FFFF Initial settings for screen
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OBJSEL > $2101 ;W SSSN NAAA Object size & Object data area designation
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OAMADDL > $2102 ;W AAAA AAAA Address for accessing OAM (Low)
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OAMADDH > $2103 ;W P--- ---A Address for accessing OAM (High)
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OAMDATA > $2104 ;W DDDD DDDD Data for OAM write
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BGMODE > $2105 ;W SSSS PMMM BG mode & Character size settings
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MOSAIC > $2106 ;W MMMM EEEE Size & Screen designation for mosaic display
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BG1SC > $2107 ;W AAAA AASS Address for storing SC-data of each BG & SC size designation (Mode 0-6) (BG-1)
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BG2SC > $2108 ;W AAAA AASS Address for storing SC-data of each BG & SC size designation (Mode 0-6) (BG-2)
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BG3SC > $2109 ;W AAAA AASS Address for storing SC-data of each BG & SC size designation (Mode 0-6) (BG-3)
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BG4SC > $210A ;W AAAA AASS Address for storing SC-data of each BG & SC size designation (Mode 0-6) (BG-4)
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BG12NBA > $210B ;W 2222 1111 BG character data area designation (BG-1, 2)
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BG34NBA > $210C ;W 4444 3333 BG character data area designation (BG-3, 4)
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BG1HOFS > $210D ;WW XXXX XXXX, ---X XXXX H scroll value designation for BG-1
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BG1VOFS > $210E ;WW XXXX XXXX, ---X XXXX V scroll value designation for BG-1
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BG2HOFS > $210F ;WW XXXX XXXX, ---- --XX H scroll value designation for BG-2
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BG2VOFS > $2110 ;WW XXXX XXXX, ---- --XX V scroll value designation for BG-2
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BG3HOFS > $2111 ;WW XXXX XXXX, ---- --XX H scroll value designation for BG-3
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BG3VOFS > $2112 ;WW XXXX XXXX, ---- --XX V scroll value designation for BG-3
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BG4HOFS > $2113 ;WW XXXX XXXX, ---- --XX H scroll value designation for BG-4
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BG4VOFS > $2114 ;WW XXXX XXXX, ---- --XX V scroll value designation for BG-4
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VMAINC > $2115 ;W T--- GGII VRAM address increment value designation
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VMADDL > $2116 ;W AAAA AAAA Address for VRAM read and write (Low)
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VMADDH > $2117 ;W AAAA AAAA Address for VRAM read and write (High)
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VMDATAL > $2118 ;W AAAA AAAA Data for VRAM write (Low)
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VMDATAH > $2119 ;W AAAA AAAA Data for VRAM write (High)
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M7SEL > $211A ;W SS-- --VH Initial setting in screen Mode-7
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M7A > $211B ;WW AAAA AAAA, AAAA AAAA Rotation/Enlargement/Reduction in Mode-7, Matrix parameter A (Low, High)
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M7B > $211C ;WW BBBB BBBB, BBBB BBBB Rotation/Enlargement/Reduction in Mode-7, Matrix parameter B (Low, High)
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M7C > $211D ;WW CCCC CCCC, CCCC CCCC Rotation/Enlargement/Reduction in Mode-7, Matrix parameter C (Low, High)
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M7D > $211E ;WW DDDD DDDD, DDDD DDDD Rotation/Enlargement/Reduction in Mode-7, Matrix parameter D (Low, High)
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M7X > $211F ;WW XXXX XXXX, ---X XXXX Rotation/Enlargement/Reduction in Mode-7, Center position X0 (Low, High)
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M7Y > $2120 ;WW YYYY YYYY, ---Y YYYY Rotation/Enlargement/Reduction in Mode-7, Center position Y0 (Low, High)
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CGADD > $2121 ;W AAAA AAAA Address for CG-RAM read and write
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CGDATA > $2122 ;WW DDDD DDDD, -DDD DDDD Data for CG-RAM write
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W12SEL > $2123 ;W EIEI EIEI Window mask settings (BG-1, 2)
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W34SEL > $2124 ;W EIEI EIEI Window mask settings (BG-3, 4)
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WOBJSEL > $2125 ;W EIEI EIEI Window mask settings (OBJ, Color)
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WH0 > $2126 ;W PPPP PPPP Window position designation (Window-1 left position)
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WH1 > $2127 ;W PPPP PPPP Window position designation (Window-1 right position)
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WH2 > $2128 ;W PPPP PPPP Window position designation (Window-2 left position)
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WH3 > $2129 ;W PPPP PPPP Window position designation (Window-2 right position)
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WBGLOG > $212A ;W 4433 2211 Mask logic settings for Window-1 & 2 on each screen
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WOBJLOG > $212B ;W ---- CCOO Mask logic settings for Window-1 & 2 on each screen
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TM > $212C ;W ---O 4321 Main screen designation
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TS > $212D ;W ---O 4321 Sub screen designation
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TMW > $212E ;W ---O 4321 Window mask designation for main screen
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TSW > $212F ;W ---O 4321 Window mask designation for sub screen
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CGSWSEL > $2130 ;W MMSS --CD Initial settings for fixed color addition on screen addition
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CGADSUB > $2131 ;W SEBO 4321 Addition/Subtraction & Subtraction designation for each BG screen OBJ & Background color
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COLDATA > $2132 ;W BGRD DDDD Fixed color data for fixed color addition/subtraction
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SETINI > $2133 ;W SI-- PBOI Screen initial setting
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MPYL < $2134 ;R MMMM MMMM Multiplication result (Low)
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MPYM < $2135 ;R MMMM MMMM Multiplication result (Middle)
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MPYH < $2136 ;R MMMM MMMM Multiplication result (High)
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SLHV < $2137 ;R ---- ---- Software latch for H/V counter
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OAMDATAREAD < $2138 ;RR DDDD DDDD, DDDD DDDD Read data from OAM
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VMDATALREAD < $2139 ;R DDDD DDDD Read data from VRAM (Low)
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VMDATAHREAD < $213A ;R DDDD DDDD Read data from VRAM (High)
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CGDATAREAD < $213B ;RR DDDD DDDD, -DDD DDDD Read data from CG-RAM
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OPHCT < $213C ;RR HHHH HHHH, ---- ---H H counter data by external or software latch
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OPVCT < $213D ;RR VVVV VVVV, ---- ---V V counter data by external or software latch
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STAT77 < $213E ;R TRM- VVVV PPU status flag & Version number (5C77)
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STAT78 < $213F ;R FL-D VVVV PPU status flag & Version number (5C78)
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APUIO0 @ $2140 ;RW DDDD DDDD Communication port with APU
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APUIO1 @ $2141 ;RW DDDD DDDD Communication port with APU
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APUIO2 @ $2142 ;RW DDDD DDDD Communication port with APU
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APUIO3 @ $2143 ;RW DDDD DDDD Communication port with APU
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WMDATA @ $2180 ;RW DDDD DDDD DATA to consecutively read from and write to WRAM
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WMADDL > $2181 ;W AAAA AAAA Address to consecutively read and write WRAM (Low)
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WMADDM > $2182 ;W AAAA AAAA Address to consecutively read and write WRAM (Middle)
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WMADDH > $2183 ;W ---- ---A Address to consecutively read and write WRAM (High)
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; CPU registers (Internal)
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NMITIMEN > $4200 ;W N-VH ---C Enable flag for V-Blank, Timer interrupt & Standard controller read
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WRIO > $4201 ;W DDDD DDDD Programmable I/O port (Out port)
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WRMPYA > $4202 ;W AAAA AAAA Multiplicand by multiplication
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WRMPYB > $4203 ;W BBBB BBBB Multiplier by multiplication
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WRDIVL > $4204 ;W CCCC CCCC Dividend by divide (Low)
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WRDIVH > $4205 ;W CCCC CCCC Dividend by divide (High)
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WRDIVB > $4206 ;W BBBB BBBB Divisor by divide
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HTIMEL > $4207 ;W HHHH HHHH H-count timer settings (Low)
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HTIMEH > $4208 ;W ---- ---H H-count timer settings (High)
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VTIMEL > $4209 ;W VVVV VVVV V-count timer settings (Low)
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VTIMEH > $420A ;W ---- ---V V-count timer settings (High)
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MDMAEN > $420B ;W 7654 3210 Channel designation for general purpose DMA & Trigger (start)
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HDMAEN > $420C ;W 7654 3210 Channel designation for H-DMA
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MEMSEL > $420D ;W ---- ---A Access cycle designation in memory [2] area
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RDNMI < $4210 ;R N--- VVVV NMI flag by V-Blank & Version number
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TIMEUP < $4211 ;R T--- ---- IRQ flag by H/V count timer
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HVBJOY < $4212 ;R VH-- ---C H/V Blank flag & Standard controller enable flag
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RDIO < $4213 ;R DDDD DDDD Programmable I/O port (In port)
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RDDIVL < $4214 ;R AAAA AAAA Quotient of divide result (Low)
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RDDIVH < $4215 ;R AAAA AAAA Quotient of divide result (High)
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RDMPYL < $4216 ;R CCCC CCCC Product of multiplication result or remainder of divide result (Low)
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RDMPYH < $4217 ;R CCCC CCCC Product of multiplication result or remainder of divide result (High)
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STDCNTRL1L < $4218 ;R AXLR ---- Data for standard controller 1 (Low)
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STDCNTRL1H < $4219 ;R BYST UDLR Data for standard controller 1 (High)
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STDCNTRL2L < $421A ;R AXLR ---- Data for standard controller 2 (Low)
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STDCNTRL2H < $421B ;R BYST UDLR Data for standard controller 2 (High)
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STDCNTRL3L < $421C ;R AXLR ---- Data for standard controller 3 (Low)
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STDCNTRL3H < $421D ;R BYST UDLR Data for standard controller 3 (High)
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STDCNTRL4L < $421E ;R AXLR ---- Data for standard controller 4 (Low)
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STDCNTRL4H < $421F ;R BYST UDLR Data for standard controller 4 (High)
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; Old Style Joypad Registers
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JOYSER0 @ $4016 ;R:---- --31 W:---- -xxL
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JOYSER1 < $4017 ;R ---- --42
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; DMA / HDMA Registers
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DMAP0 @ $4300 ;RW DT-I FDDD Parameter for DMA transfer (Channel 0)
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BBAD0 @ $4301 ;RW AAAA AAAA B-bus address for DMA (Channel 0)
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A1T0L @ $4302 ;RW AAAA AAAA Table address of A-bus for DMA (Low) (Channel 0)
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A1T0H @ $4303 ;RW AAAA AAAA Table address of A-bus for DMA (High) (Channel 0)
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A1B0 @ $4304 ;RW BBBB BBBB Table address of A-bus for DMA (Bank) (Channel 0)
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DAS0L @ $4305 ;RW AAAA AAAA Data address store by H-DMA & Number of byte to be transferred settings by general purpose DMA (Low) (Channel 0)
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DAS0H @ $4306 ;RW AAAA AAAA Data address store by H-DMA & Number of byte to be transferred settings by general purpose DMA (High) (Channel 0)
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DASB0 @ $4307 ;RW BBBB BBBB Data address store by H-DMA (Bank) (Channel 0)
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A2A0L @ $4308 ;RW AAAA AAAA Table address of A-bus by DMA (Low) (Channel 0)
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A2A0H @ $4309 ;RW AAAA AAAA Table address of A-bus by DMA (High) (Channel 0)
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NTLR0 @ $430A ;RW CLLL LLLL The number of lines to be transferred by H-DMA (Channel 0)
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;DMAUNKNOWN00 @ $430B ;RW ???? ???? Unknown (Channel 0)
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;DMAUNKNOWN01 @ $430F ;RW ???? ???? Unknown (Channel 0)
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DMAP1 @ $4310 ;RW DT-I FDDD Parameter for DMA transfer (Channel 1)
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BBAD1 @ $4311 ;RW AAAA AAAA B-bus address for DMA (Channel 1)
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A1T1L @ $4312 ;RW AAAA AAAA Table address of A-bus for DMA (Low) (Channel 1)
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A1T1H @ $4313 ;RW AAAA AAAA Table address of A-bus for DMA (High) (Channel 1)
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A1B1 @ $4314 ;RW BBBB BBBB Table address of A-bus for DMA (Bank) (Channel 1)
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DAS1L @ $4315 ;RW AAAA AAAA Data address store by H-DMA & Number of byte to be transferred settings by general purpose DMA (Low) (Channel 1)
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DAS1H @ $4316 ;RW AAAA AAAA Data address store by H-DMA & Number of byte to be transferred settings by general purpose DMA (High) (Channel 1)
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DASB1 @ $4317 ;RW BBBB BBBB Data address store by H-DMA (Bank) (Channel 1)
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A2A1L @ $4318 ;RW AAAA AAAA Table address of A-bus by DMA (Low) (Channel 1)
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A2A1H @ $4319 ;RW AAAA AAAA Table address of A-bus by DMA (High) (Channel 1)
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NTLR1 @ $431A ;RW CLLL LLLL The number of lines to be transferred by H-DMA (Channel 1)
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;DMAUNKNOWN10 @ $431B ;RW ???? ???? Unknown (Channel 1)
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;DMAUNKNOWN11 @ $431F ;RW ???? ???? Unknown (Channel 1)
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DMAP2 @ $4320 ;RW DT-I FDDD Parameter for DMA transfer (Channel 2)
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BBAD2 @ $4321 ;RW AAAA AAAA B-bus address for DMA (Channel 2)
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A1T2L @ $4322 ;RW AAAA AAAA Table address of A-bus for DMA (Low) (Channel 2)
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A1T2H @ $4323 ;RW AAAA AAAA Table address of A-bus for DMA (High) (Channel 2)
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A1B2 @ $4324 ;RW BBBB BBBB Table address of A-bus for DMA (Bank) (Channel 2)
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DAS2L @ $4325 ;RW AAAA AAAA Data address store by H-DMA & Number of byte to be transferred settings by general purpose DMA (Low) (Channel 2)
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DAS2H @ $4326 ;RW AAAA AAAA Data address store by H-DMA & Number of byte to be transferred settings by general purpose DMA (High) (Channel 2)
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DASB2 @ $4327 ;RW BBBB BBBB Data address store by H-DMA (Bank) (Channel 2)
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A2A2L @ $4328 ;RW AAAA AAAA Table address of A-bus by DMA (Low) (Channel 2)
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A2A2H @ $4329 ;RW AAAA AAAA Table address of A-bus by DMA (High) (Channel 2)
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NTLR2 @ $432A ;RW CLLL LLLL The number of lines to be transferred by H-DMA (Channel 2)
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;DMAUNKNOWN20 @ $432B ;RW ???? ???? Unknown (Channel 2)
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;DMAUNKNOWN21 @ $432F ;RW ???? ???? Unknown (Channel 2)
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DMAP3 @ $4330 ;RW DT-I FDDD Parameter for DMA transfer (Channel 3)
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BBAD3 @ $4331 ;RW AAAA AAAA B-bus address for DMA (Channel 3)
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A1T3L @ $4332 ;RW AAAA AAAA Table address of A-bus for DMA (Low) (Channel 3)
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A1T3H @ $4333 ;RW AAAA AAAA Table address of A-bus for DMA (High) (Channel 3)
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A1B3 @ $4334 ;RW BBBB BBBB Table address of A-bus for DMA (Bank) (Channel 3)
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DAS3L @ $4335 ;RW AAAA AAAA Data address store by H-DMA & Number of byte to be transferred settings by general purpose DMA (Low) (Channel 3)
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DAS3H @ $4336 ;RW AAAA AAAA Data address store by H-DMA & Number of byte to be transferred settings by general purpose DMA (High) (Channel 3)
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DASB3 @ $4337 ;RW BBBB BBBB Data address store by H-DMA (Bank) (Channel 3)
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A2A3L @ $4338 ;RW AAAA AAAA Table address of A-bus by DMA (Low) (Channel 3)
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A2A3H @ $4339 ;RW AAAA AAAA Table address of A-bus by DMA (High) (Channel 3)
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NTLR3 @ $433A ;RW CLLL LLLL The number of lines to be transferred by H-DMA (Channel 3)
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;DMAUNKNOWN30 @ $433B ;RW ???? ???? Unknown (Channel 3)
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;DMAUNKNOWN31 @ $433F ;RW ???? ???? Unknown (Channel 3)
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DMAP4 @ $4340 ;RW DT-I FDDD Parameter for DMA transfer (Channel 4)
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BBAD4 @ $4341 ;RW AAAA AAAA B-bus address for DMA (Channel 4)
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A1T4L @ $4342 ;RW AAAA AAAA Table address of A-bus for DMA (Low) (Channel 4)
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A1T4H @ $4343 ;RW AAAA AAAA Table address of A-bus for DMA (High) (Channel 4)
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A1B4 @ $4344 ;RW BBBB BBBB Table address of A-bus for DMA (Bank) (Channel 4)
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DAS4L @ $4345 ;RW AAAA AAAA Data address store by H-DMA & Number of byte to be transferred settings by general purpose DMA (Low) (Channel 4)
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DAS4H @ $4346 ;RW AAAA AAAA Data address store by H-DMA & Number of byte to be transferred settings by general purpose DMA (High) (Channel 4)
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DASB4 @ $4347 ;RW BBBB BBBB Data address store by H-DMA (Bank) (Channel 4)
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A2A4L @ $4348 ;RW AAAA AAAA Table address of A-bus by DMA (Low) (Channel 4)
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A2A4H @ $4349 ;RW AAAA AAAA Table address of A-bus by DMA (High) (Channel 4)
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NTLR4 @ $434A ;RW CLLL LLLL The number of lines to be transferred by H-DMA (Channel 4)
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;DMAUNKNOWN40 @ $434B ;RW ???? ???? Unknown (Channel 4)
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;DMAUNKNOWN41 @ $434F ;RW ???? ???? Unknown (Channel 4)
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DMAP5 @ $4350 ;RW DT-I FDDD Parameter for DMA transfer (Channel 5)
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BBAD5 @ $4351 ;RW AAAA AAAA B-bus address for DMA (Channel 5)
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A1T5L @ $4352 ;RW AAAA AAAA Table address of A-bus for DMA (Low) (Channel 5)
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A1T5H @ $4353 ;RW AAAA AAAA Table address of A-bus for DMA (High) (Channel 5)
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A1B5 @ $4354 ;RW BBBB BBBB Table address of A-bus for DMA (Bank) (Channel 5)
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DAS5L @ $4355 ;RW AAAA AAAA Data address store by H-DMA & Number of byte to be transferred settings by general purpose DMA (Low) (Channel 5)
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DAS5H @ $4356 ;RW AAAA AAAA Data address store by H-DMA & Number of byte to be transferred settings by general purpose DMA (High) (Channel 5)
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DASB5 @ $4357 ;RW BBBB BBBB Data address store by H-DMA (Bank) (Channel 5)
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A2A5L @ $4358 ;RW AAAA AAAA Table address of A-bus by DMA (Low) (Channel 5)
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A2A5H @ $4359 ;RW AAAA AAAA Table address of A-bus by DMA (High) (Channel 5)
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NTLR5 @ $435A ;RW CLLL LLLL The number of lines to be transferred by H-DMA (Channel 5)
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;DMAUNKNOWN50 @ $435B ;RW ???? ???? Unknown (Channel 5)
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;DMAUNKNOWN51 @ $435F ;RW ???? ???? Unknown (Channel 5)
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DMAP6 @ $4360 ;RW DT-I FDDD Parameter for DMA transfer (Channel 6)
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BBAD6 @ $4361 ;RW AAAA AAAA B-bus address for DMA (Channel 6)
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A1T6L @ $4362 ;RW AAAA AAAA Table address of A-bus for DMA (Low) (Channel 6)
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A1T6H @ $4363 ;RW AAAA AAAA Table address of A-bus for DMA (High) (Channel 6)
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A1B6 @ $4364 ;RW BBBB BBBB Table address of A-bus for DMA (Bank) (Channel 6)
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DAS6L @ $4365 ;RW AAAA AAAA Data address store by H-DMA & Number of byte to be transferred settings by general purpose DMA (Low) (Channel 6)
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DAS6H @ $4366 ;RW AAAA AAAA Data address store by H-DMA & Number of byte to be transferred settings by general purpose DMA (High) (Channel 6)
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DASB6 @ $4367 ;RW BBBB BBBB Data address store by H-DMA (Bank) (Channel 6)
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A2A6L @ $4368 ;RW AAAA AAAA Table address of A-bus by DMA (Low) (Channel 6)
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A2A6H @ $4369 ;RW AAAA AAAA Table address of A-bus by DMA (High) (Channel 6)
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NTLR6 @ $436A ;RW CLLL LLLL The number of lines to be transferred by H-DMA (Channel 6)
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;DMAUNKNOWN60 @ $436B ;RW ???? ???? Unknown (Channel 6)
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;DMAUNKNOWN61 @ $436F ;RW ???? ???? Unknown (Channel 6)
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DMAP7 @ $4370 ;RW DT-I FDDD Parameter for DMA transfer (Channel 7)
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BBAD7 @ $4371 ;RW AAAA AAAA B-bus address for DMA (Channel 7)
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A1T7L @ $4372 ;RW AAAA AAAA Table address of A-bus for DMA (Low) (Channel 7)
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A1T7H @ $4373 ;RW AAAA AAAA Table address of A-bus for DMA (High) (Channel 7)
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A1B7 @ $4374 ;RW BBBB BBBB Table address of A-bus for DMA (Bank) (Channel 7)
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DAS7L @ $4375 ;RW AAAA AAAA Data address store by H-DMA & Number of byte to be transferred settings by general purpose DMA (Low) (Channel 7)
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DAS7H @ $4376 ;RW AAAA AAAA Data address store by H-DMA & Number of byte to be transferred settings by general purpose DMA (High) (Channel 7)
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DASB7 @ $4377 ;RW BBBB BBBB Data address store by H-DMA (Bank) (Channel 7)
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A2A7L @ $4378 ;RW AAAA AAAA Table address of A-bus by DMA (Low) (Channel 7)
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A2A7H @ $4379 ;RW AAAA AAAA Table address of A-bus by DMA (High) (Channel 7)
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NTLR7 @ $437A ;RW CLLL LLLL The number of lines to be transferred by H-DMA (Channel 7)
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;DMAUNKNOWN70 @ $437B ;RW ???? ???? Unknown (Channel 7)
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;DMAUNKNOWN71 @ $437F ;RW ???? ???? Unknown (Channel 7)
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