2021-07-07 16:06:22 +00:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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2021-07-08 15:06:47 +00:00
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/* verilator lint_off UNDRIVEN */
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2021-07-07 16:06:22 +00:00
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module t (/*AUTOARG*/);
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// IEEE: integer_atom_type
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byte d_byte;
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shortint d_shortint;
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int d_int;
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longint d_longint;
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integer d_integer;
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time d_time;
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chandle d_chandle;
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// IEEE: integer_atom_type
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bit d_bit;
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logic d_logic;
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reg d_reg;
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bit [1:0] d_bit2;
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logic [1:0] d_logic2;
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reg [1:0] d_reg2;
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// IEEE: non_integer_type
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//UNSUP shortreal d_shortreal;
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real d_real;
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realtime d_realtime;
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// Declarations using var
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var byte v_b;
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`ifndef VCS
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var [2:0] v_b3;
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var signed [2:0] v_bs;
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`endif
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// verilator lint_off WIDTH
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localparam p_implicit = {96{1'b1}};
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localparam [89:0] p_explicit = {96{1'b1}};
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localparam byte p_byte = {96{1'b1}};
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localparam shortint p_shortint = {96{1'b1}};
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localparam int p_int = {96{1'b1}};
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localparam longint p_longint = {96{1'b1}};
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localparam integer p_integer = {96{1'b1}};
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localparam reg p_reg = {96{1'b1}};
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localparam bit p_bit = {96{1'b1}};
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localparam logic p_logic = {96{1'b1}};
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localparam reg [0:0] p_reg1 = {96{1'b1}};
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localparam bit [0:0] p_bit1 = {96{1'b1}};
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localparam logic [0:0] p_logic1= {96{1'b1}};
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localparam reg [1:0] p_reg2 = {96{1'b1}};
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localparam bit [1:0] p_bit2 = {96{1'b1}};
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localparam logic [1:0] p_logic2= {96{1'b1}};
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// verilator lint_on WIDTH
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byte v_byte[2];
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shortint v_shortint[2];
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int v_int[2];
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longint v_longint[2];
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integer v_integer[2];
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time v_time[2];
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chandle v_chandle[2];
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bit v_bit[2];
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logic v_logic[2];
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reg v_reg[2];
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real v_real[2];
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realtime v_realtime[2];
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// We do this in two steps so we can check that initialization inside functions works properly
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// verilator lint_off WIDTH
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function f_implicit; reg lv_implicit; f_implicit = lv_implicit; endfunction
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function [89:0] f_explicit; reg [89:0] lv_explicit; f_explicit = lv_explicit; endfunction
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function byte f_byte; byte lv_byte; f_byte = lv_byte; endfunction
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function shortint f_shortint; shortint lv_shortint; f_shortint = lv_shortint; endfunction
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function int f_int; int lv_int; f_int = lv_int; endfunction
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function longint f_longint; longint lv_longint; f_longint = lv_longint; endfunction
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function integer f_integer; integer lv_integer; f_integer = lv_integer; endfunction
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function reg f_reg; reg lv_reg; f_reg = lv_reg; endfunction
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function bit f_bit; bit lv_bit; f_bit = lv_bit; endfunction
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function logic f_logic; logic lv_logic; f_logic = lv_logic; endfunction
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function reg [0:0] f_reg1; reg [0:0] lv_reg1; f_reg1 = lv_reg1; endfunction
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function bit [0:0] f_bit1; bit [0:0] lv_bit1; f_bit1 = lv_bit1; endfunction
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function logic [0:0] f_logic1; logic [0:0] lv_logic1; f_logic1 = lv_logic1; endfunction
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function reg [1:0] f_reg2; reg [1:0] lv_reg2; f_reg2 = lv_reg2; endfunction
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function bit [1:0] f_bit2; bit [1:0] lv_bit2; f_bit2 = lv_bit2; endfunction
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function logic [1:0] f_logic2; logic [1:0] lv_logic2; f_logic2 = lv_logic2; endfunction
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function time f_time; time lv_time; f_time = lv_time; endfunction
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function chandle f_chandle; chandle lv_chandle; f_chandle = lv_chandle; endfunction
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// verilator lint_on WIDTH
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2021-07-08 15:06:47 +00:00
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`define XINIT 1'b0
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2021-07-07 16:06:22 +00:00
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`define ALL_TWOSTATE 1'b1
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`define CHECK_ALL(name,nbits,issigned,twostate,zeroinit) \
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if (zeroinit ? ((name & 1'b1)!==1'b0) : ((name & 1'b1)!==`XINIT)) \
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begin $display("%%Error: Bad zero/X init for %s: %b",`"name`",name); $stop; end \
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name = {96{1'b1}}; \
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if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \
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if (issigned ? (name > 0) : (name < 0)) begin $display("%%Error: Bad signed for %s",`"name`"); $stop; end \
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name = {96{1'bx}}; \
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if (name !== {(nbits){`ALL_TWOSTATE ? `XINIT : (twostate ? 1'b0 : `XINIT)}}) \
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begin $display("%%Error: Bad twostate for %s: %b",`"name`",name); $stop; end \
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initial begin
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// verilator lint_off WIDTH
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// verilator lint_off UNSIGNED
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// name b sign twost 0init
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`CHECK_ALL(d_byte ,8 ,1'b1,1'b1,1'b1);
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`CHECK_ALL(d_shortint ,16,1'b1,1'b1,1'b1);
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`CHECK_ALL(d_int ,32,1'b1,1'b1,1'b1);
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`CHECK_ALL(d_longint ,64,1'b1,1'b1,1'b1);
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`CHECK_ALL(d_integer ,32,1'b1,1'b0,1'b0);
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2021-07-08 21:27:06 +00:00
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//`CHECK_ALL(d_time ,64,1'b0,1'b0,1'b0);
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2021-07-07 16:06:22 +00:00
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`CHECK_ALL(d_bit ,1 ,1'b0,1'b1,1'b1);
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`CHECK_ALL(d_logic ,1 ,1'b0,1'b0,1'b0);
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`CHECK_ALL(d_reg ,1 ,1'b0,1'b0,1'b0);
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`CHECK_ALL(d_bit2 ,2 ,1'b0,1'b1,1'b1);
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`CHECK_ALL(d_logic2 ,2 ,1'b0,1'b0,1'b0);
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`CHECK_ALL(d_reg2 ,2 ,1'b0,1'b0,1'b0);
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// verilator lint_on WIDTH
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// verilator lint_on UNSIGNED
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// Can't CHECK_ALL(d_chandle), as many operations not legal on chandles
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`ifdef VERILATOR // else indeterminate
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if ($bits(d_chandle) !== 64) $stop;
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`endif
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`define CHECK_P(name,nbits) \
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if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \
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// name b
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`CHECK_P(p_implicit ,96);
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`CHECK_P(p_implicit[0] ,1 );
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`CHECK_P(p_explicit ,90);
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`CHECK_P(p_explicit[0] ,1 );
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`CHECK_P(p_byte ,8 );
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`CHECK_P(p_byte[0] ,1 );
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`CHECK_P(p_shortint ,16);
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`CHECK_P(p_shortint[0] ,1 );
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`CHECK_P(p_int ,32);
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`CHECK_P(p_int[0] ,1 );
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`CHECK_P(p_longint ,64);
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`CHECK_P(p_longint[0] ,1 );
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`CHECK_P(p_integer ,32);
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`CHECK_P(p_integer[0] ,1 );
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`CHECK_P(p_bit ,1 );
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`CHECK_P(p_logic ,1 );
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`CHECK_P(p_reg ,1 );
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`CHECK_P(p_bit1 ,1 );
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`CHECK_P(p_logic1 ,1 );
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`CHECK_P(p_reg1 ,1 );
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`CHECK_P(p_bit1[0] ,1 );
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`CHECK_P(p_logic1[0] ,1 );
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`CHECK_P(p_reg1[0] ,1 );
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`CHECK_P(p_bit2 ,2 );
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`CHECK_P(p_logic2 ,2 );
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`CHECK_P(p_reg2 ,2 );
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`define CHECK_B(varname,nbits) \
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if ($bits(varname) !== nbits) begin $display("%%Error: Bad size for %s",`"varname`"); $stop; end \
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`CHECK_B(v_byte[1] ,8 );
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`CHECK_B(v_shortint[1] ,16);
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`CHECK_B(v_int[1] ,32);
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`CHECK_B(v_longint[1] ,64);
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`CHECK_B(v_integer[1] ,32);
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`CHECK_B(v_time[1] ,64);
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//`CHECK_B(v_chandle[1]
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`CHECK_B(v_bit[1] ,1 );
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`CHECK_B(v_logic[1] ,1 );
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`CHECK_B(v_reg[1] ,1 );
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//`CHECK_B(v_real[1] ,64); // $bits not allowed
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//`CHECK_B(v_realtime[1] ,64); // $bits not allowed
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`define CHECK_F(fname,nbits,zeroinit) \
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if ($bits(fname()) !== nbits) begin $display("%%Error: Bad size for %s",`"fname`"); $stop; end \
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// name b 0init
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`CHECK_F(f_implicit ,1 ,1'b0); // Note 1 bit, not 96
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`CHECK_F(f_explicit ,90,1'b0);
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`CHECK_F(f_byte ,8 ,1'b1);
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`CHECK_F(f_shortint ,16,1'b1);
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`CHECK_F(f_int ,32,1'b1);
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`CHECK_F(f_longint ,64,1'b1);
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`CHECK_F(f_integer ,32,1'b0);
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`CHECK_F(f_time ,64,1'b0);
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`ifdef VERILATOR // else indeterminate
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`CHECK_F(f_chandle ,64,1'b0);
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`endif
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`CHECK_F(f_bit ,1 ,1'b1);
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`CHECK_F(f_logic ,1 ,1'b0);
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`CHECK_F(f_reg ,1 ,1'b0);
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`CHECK_F(f_bit1 ,1 ,1'b1);
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`CHECK_F(f_logic1 ,1 ,1'b0);
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`CHECK_F(f_reg1 ,1 ,1'b0);
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`CHECK_F(f_bit2 ,2 ,1'b1);
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`CHECK_F(f_logic2 ,2 ,1'b0);
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`CHECK_F(f_reg2 ,2 ,1'b0);
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// For unpacked types we don't want width warnings for unsized numbers that fit
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d_byte = 2;
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d_shortint= 2;
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d_int = 2;
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d_longint = 2;
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d_integer = 2;
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// Special check
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d_time = $time;
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if ($time !== d_time) $stop;
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// Null checks
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d_chandle = null;
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if (d_chandle != null) $stop;
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if (d_chandle) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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