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8bitworkshop/gen/arm32-IVL2WI33.js.map

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{
"version": 3,
"sources": ["../src/common/cpu/ARM.ts", "../src/machine/arm32.ts", "../src/platform/arm32.ts"],
"sourcesContent": ["/*\nFrom: https://github.com/endrift/gbajs\n\nCopyright \u00A9 2012 \u2013 2013, Jeffrey Pfau\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n* Redistributions of source code must retain the above copyright notice, this\n list of conditions and the following disclaimer.\n\n* Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n*/\n\nimport { Bus, Bus32, CPU, InstructionBased, SavesState } from \"../devices\";\nimport { EmuHalt } from \"../emu\";\nimport { hex } from \"../util\";\n\ninterface AddressFunction extends Function {\n writesPC? : boolean;\n fixedJump? : boolean;\n}\n\ninterface ARMIRQInterface {\n\tclear() : void;\n\tswi(opcode : number) : void;\n\tswi32(opcode : number) : void;\n\tupdateTimers() : void;\n\ttestIRQ() : void;\n}\n\ninterface ARMMemoryRegion {\n\tPAGE_MASK : number;\n\tICACHE_PAGE_BITS : number;\n\ticache : ARMMemoryPage[];\n}\n\ninterface ARMOperation {\n\tnext : ARMOperation;\n\tpage : ARMMemoryPage;\n\taddress : number;\n\topcode : number;\n}\n\ninterface ARMMemoryPage {\n\tarm : ARMOperation[];\n\tthumb : ARMOperation[];\n\tinvalid : boolean;\n}\n\ninterface ARMMMUInterface {\n\tmemory : ARMMemoryRegion[];\n\tBASE_OFFSET : number;\n\tOFFSET_MASK : number;\n\n\tload8(a: number) : number;\n\tloadU8(a: number) : number;\n\tload16(a: number) : number;\n\tloadU16(a: number) : number;\n\tload32(a: number) : number;\n\tstore8(a: number, v: number) : void;\n\tstore16(a: number, v: number) : void;\n\tstore32(a: number, v: number) : void;\n\n\twait(a: number) : void;\n\twait32(a: number) : void;\n\twaitSeq32(a: number) : void;\n\twaitMul(a: number) : void;\n\twaitMulti32(a: number, total: number) : void;\n\twaitPrefetch(a: number) : void;\n\twaitPrefetch32(a: number) : void;\n\n\taddressToPage(region: number, address: number) : number;\n\taccessPage(region: number, pageId: number) : ARMMemoryPage;\n}\n\nexport interface ARMCoreState {\n\tPC: number,\n\tSP: number,\n\tgprs: number[],\n\tmode: number,\n\tcpsrI: boolean,\n\tcpsrF: boolean,\n\tcpsrV: boolean,\n\tcpsrC: boolean,\n\tcpsrZ: boolean,\n\tcpsrN: boolean,\n\tbankedRegisters: number[][],\n\tspsr: number,\n\tbankedSPSRs: number[],\n\tsfprs: number[],\n\tdfprs: number[],\n\tifprs: number[],\n\tcycles: number,\n\tinstructionWidth: 2 | 4\n}\n\ninterface ARMCoreType {\n\tgprs: Int32Array;\n\tsfprs: Float32Array;\n\tdfprs: Float64Array;\n\tifprs: Int32Array;\n\tPC: number;\n\tSP: number;\n\tLR: number;\n\tcycles: number;\n\tmode: number;\n\tshifterOperand: number;\n\tshifterCarryOut: number|boolean;\n\tcpsrN: number|boolean;\n\tcpsrC: number|boolean;\n\tcpsrZ: number|boolean;\n\tcpsrV: number|boolean;\n\tcpsrI: number|boolean;\n\tcpsrF: number|boolean;\n\tspsr: number;\n\tmmu: ARMMMUInterface;\n\tirq : ARMIRQInterface;\n\tinstructionWidth: 2 | 4;\n\n\thasSPSR() : boolean;\n\tunpackCPSR(v : number) : void;\n\tswitchMode(mode : number) : void;\n\tswitchExecMode(mode : number) : void;\n\tpackCPSR() : number;\n\n\tstep() : void;\n\tresetCPU(startOffset : number) : void;\n\tfreeze() : ARMCoreState
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