mirror of
https://github.com/sehugg/8bitworkshop.git
synced 2024-08-26 15:28:57 +00:00
229 lines
3.8 KiB
Coq
229 lines
3.8 KiB
Coq
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`define __BAUD__ '0
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module darksocv_top
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(
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input b,
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c,
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output d,
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[3:0] LED,
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DEBUG
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);
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wire e = b;
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`ifdef g
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`else
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wire CLK = e;
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wire h [];
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reg [31:0] i [7];
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`endif
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wire [31:0] IADDR;
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wire [31:0] aa;
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wire [31:0] j;
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wire [31:0] DATAO;
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wire [31:0] k;
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wire l,m;
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wire [3:0] ab;
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wire n [];
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reg [5:0] o = 0;
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`ifdef p
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`else
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reg [31:0] q
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`ifdef r
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`else
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;
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assign j = q;
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`endif
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always@(posedge CLK)
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begin
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`ifdef d
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`else
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q <= i;
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`endif
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end
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reg [31:0] s;
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`ifdef r
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`endif
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always@(posedge CLK)
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begin
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`ifdef d
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`else
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s <= i;
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`ifdef d
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`else
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i[aa][ 7: 0 ] <= DATAO[ 7: 0 ];
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`endif
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`endif
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end
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assign k = s;
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`endif
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wire [7:0] u;
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ae
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v
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(
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CLK,
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h,
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m,
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l,
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ab,
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k,
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n,
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u[1],
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c,
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d,
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DEBUG
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);
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af
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w
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(
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`ifdef ag
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`else
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CLK,
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`endif
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h,
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c,
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j,
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IADDR,
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.aa,
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`ifdef x
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`else
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.k,
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.DATAO,
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ab,
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l,
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m,
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`endif
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y,
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DEBUG
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);
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wire y ;
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assign LED = o[3:0];
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endmodule
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`define UART_STATE_IDLE 6
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`define UART_STATE_START 7
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module ae
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(
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input CLK,
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h,
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m,
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l,
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[ 3:0] z,
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[31:0] k,
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output [31:0] DATAO,
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output IRQ,
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input RXD,
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output TXD,
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[3:0] DEBUG
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);
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reg [15:0] UART_TIMER = `__BAUD__;
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`ifdef ah
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`else
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reg UART_XACK = 0;
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`endif
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reg [ 3:0] UART_XSTATE= 0;
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`ifdef ah
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`else
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reg [ 7:0] UART_RFIFO = 0;
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reg UART_RACK = 0;
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`endif
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reg [ 3:0] UART_RSTATE= 0;
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`ifdef ah
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`else
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wire [7:0] UART_STATE = { 6'd0, UART_RACK, UART_XACK };
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`endif
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assign IRQ = 0;
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`ifdef a
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`else
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assign DATAO = { UART_TIMER, UART_RFIFO, UART_STATE };
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assign TXD = UART_XSTATE==`UART_STATE_START ;
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`endif
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assign DEBUG = { RXD, TXD, UART_XSTATE!=`UART_STATE_IDLE, UART_RSTATE!=`UART_STATE_IDLE };
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endmodule
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`define LCC 'b00000_11
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module af
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(
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input CLK,
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h,
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c,
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[31:0] j,
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output [31:0] IADDR,
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input [31:0] k,
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output [31:0] DATAO,
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aa,
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`ifdef x
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`else
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[ 3:0] ab,
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output l,
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m,
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`endif
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y,
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[3:0] DEBUG
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);
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wire [31:0] aj = 0;
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reg [31:0] al;
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reg XLCC, am , an=1;
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reg [31:0] ao;
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reg [31:0] ap;
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always@(posedge CLK)
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begin
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al <= an ? al : j;
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XLCC <= an ? XLCC : j==`LCC;
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am <= aq
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;
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ao <=
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aj;
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ap <= aj;
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end
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`ifdef ag
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`else
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reg ar ;
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`ifdef as
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`else
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reg [4:0] DPTR = al[19:15];
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wire [4:0] at = al[24:20];
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`endif
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`endif
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wire [31:0] au =
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ap;
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wire LCC = XLCC;
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wire aq = am;
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`ifdef av
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`else
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`ifdef as
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`else
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reg aw [];
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reg [31:0] ax [031];
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`endif
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`endif
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reg [31:0] ay= aw;
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wire [31:0] az = ax[at]
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;
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`ifdef x
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`else
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wire [31:0] ba = az
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`endif
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;
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wire [31:0] bb = az;
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wire [31:0] bc = `ifdef d
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`else
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bb;
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`endif
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always@(posedge CLK)
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begin
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`ifdef ag
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`else
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ar <= 0;
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ax[DPTR] <=
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4;
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`endif
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end
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assign DATAO = ba;
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assign aa = au;
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`ifdef x
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`else
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assign m = LCC;
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assign l = aq;
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assign ab = 'b1111;
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assign IADDR = ay;
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`endif
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assign y = ar;
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assign DEBUG = { an, ar, aq, LCC };
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endmodule
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