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63 lines
1.6 KiB
Coq
63 lines
1.6 KiB
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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// IEEE: integer_atom_type
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wire byte w_byte;
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wire shortint w_shortint;
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wire int w_int;
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wire longint w_longint;
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wire integer w_integer;
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// IEEE: integer_atom_type
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wire bit w_bit;
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wire logic w_logic;
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wire bit [1:0] w_bit2;
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wire logic [1:0] w_logic2;
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// IEEE: non_integer_type
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//UNSUP shortreal w_shortreal;
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wire real w_real;
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assign w_byte = 8'h12;
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assign w_shortint = 16'h1234;
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assign w_int = -123456;
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assign w_longint = -1234567;
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assign w_integer = -123456;
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assign w_bit = 1'b1;
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assign w_logic = 1'b1;
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assign w_bit2 = 2'b10;
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assign w_logic2 = 2'b10;
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assign w_real = 3.14;
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always @ (posedge clk) begin
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`checkh(w_byte, 8'h12);
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`checkh(w_shortint, 16'h1234);
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`checkh(w_int, -123456);
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`checkh(w_longint, -1234567);
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`checkh(w_integer, -123456);
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`checkh(w_bit, 1'b1);
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`checkh(w_logic, 1'b1);
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`checkh(w_bit2, 2'b10);
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`checkh(w_logic2, 2'b10);
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`checkr(w_real, 3.14);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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