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24 lines
570 B
Coq
24 lines
570 B
Coq
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`include "hvsync_generator.v"
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module RAM(clk, addr, din, dout, we);
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parameter A = 10; // # of address bits
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parameter D = 8; // # of data bits
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input clk; // clock
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input [A-1:0] addr; // 10-bit address
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input [D-1:0] din; // 8-bit data input
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output [D-1:0] dout; // 8-bit data output
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input we; // write enable
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reg [D-1:0] mem [0:(1<<A)-1]; // 1024x8 bit memory
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always @(posedge clk) begin
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if (we) // if write enabled
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mem[addr] <= din; // write memory from din
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dout <= mem[addr]; // read memory to dout
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end
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endmodule
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