fixed verilog 6502 CPU
This commit is contained in:
Steven Hugg
parent
912123ea64
commit
187bcfc2e2
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@ -1,16 +1,20 @@
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/* verilator lint_off CASEX */
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/* verilator lint_off CASEINCOMPLETE */
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/* verilator lint_off CASEOVERLAP */
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/* verilator lint_off SYNCASYNCNET */
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/*
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* verilog model of 6502 CPU.
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*
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* (C) Arlet Ottens, <arlet@c-scape.nl>
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*
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* https://github.com/Arlet/verilog-6502/
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*
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* Feel free to use this code in any project (commercial or not), as long as you
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* keep this message, and the copyright notice. This code is provided "as is",
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* without any warranties of any kind.
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*
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*/
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/*
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* Note that not all 6502 interface signals are supported (yet). The goal
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* is to create an Acorn Atom model, and the Atom didn't use all signals on
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* the main board.
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@ -500,8 +504,8 @@ reg [3:0] ADJH;
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// adc_bcd: '1' if doing ADC with D=1
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// HC : half carry bit from ALU
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always @* begin
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casez( {adj_bcd, adc_bcd, HC} )
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3'b0??: ADJL = 4'd0; // no BCD instruction
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casex( {adj_bcd, adc_bcd, HC} )
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3'b0xx: ADJL = 4'd0; // no BCD instruction
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3'b100: ADJL = 4'd10; // SBC, and digital borrow
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3'b101: ADJL = 4'd0; // SBC, but no borrow
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3'b110: ADJL = 4'd0; // ADC, but no carry
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@ -514,8 +518,8 @@ end
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// adc_bcd: '1' if doing ADC with D=1
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// CO : carry out bit from ALU
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always @* begin
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casez( {adj_bcd, adc_bcd, CO} )
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3'b0??: ADJH = 4'd0; // no BCD instruction
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casex( {adj_bcd, adc_bcd, CO} )
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3'b0xx: ADJH = 4'd0; // no BCD instruction
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3'b100: ADJH = 4'd10; // SBC, and digital borrow
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3'b101: ADJH = 4'd0; // SBC, but no borrow
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3'b110: ADJH = 4'd0; // ADC, but no carry
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@ -857,15 +861,16 @@ always @(posedge clk )
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assign DIMUX = ~RDY ? DIHOLD : DI;
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/*
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* Microcode state machine
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*/
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always @(posedge clk)
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always @(posedge clk or posedge reset)
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if( reset )
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state <= BRK0;
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else if( RDY ) case( state )
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DECODE :
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casez ( IR )
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casex ( IR )
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8'b0000_0000: state <= BRK0;
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8'b0010_0000: state <= JSR0;
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8'b0010_1100: state <= ABS0; // BIT abs
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@ -873,24 +878,23 @@ always @(posedge clk)
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8'b0100_1100: state <= JMP0;
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8'b0110_0000: state <= RTS0;
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8'b0110_1100: state <= JMPI0;
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8'b0?00_1000: state <= PUSH0;
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8'b0?10_1000: state <= PULL0;
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8'b0??1_1000: state <= REG; // CLC, SEC, CLI, SEI
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8'b1??0_00?0: state <= FETCH; // IMM
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8'b1??0_1100: state <= ABS0; // X/Y abs
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8'b1???_1000: state <= REG; // DEY, TYA, ...
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8'b???0_0001: state <= INDX0;
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8'b???0_01??: state <= ZP0;
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8'b???0_1001: state <= FETCH; // IMM
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8'b???0_1101: state <= ABS0; // even E column
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8'b???0_1110: state <= ABS0; // even E column
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8'b???1_0000: state <= BRA0; // odd 0 column
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8'b???1_0001: state <= INDY0; // odd 1 column
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8'b???1_01??: state <= ZPX0; // odd 4,5,6,7 columns
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8'b???1_1001: state <= ABSX0; // odd 9 column
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8'b???1_11??: state <= ABSX0; // odd C, D, E, F columns
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8'b????_1010: state <= REG; // <shift> A, TXA, ... NOP
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default: state <= BRK0; // TODO
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8'b0x00_1000: state <= PUSH0;
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8'b0x10_1000: state <= PULL0;
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8'b0xx1_1000: state <= REG; // CLC, SEC, CLI, SEI
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8'b1xx0_00x0: state <= FETCH; // IMM
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8'b1xx0_1100: state <= ABS0; // X/Y abs
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8'b1xxx_1000: state <= REG; // DEY, TYA, ...
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8'bxxx0_0001: state <= INDX0;
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8'bxxx0_01xx: state <= ZP0;
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8'bxxx0_1001: state <= FETCH; // IMM
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8'bxxx0_1101: state <= ABS0; // even E column
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8'bxxx0_1110: state <= ABS0; // even E column
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8'bxxx1_0000: state <= BRA0; // odd 0 column
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8'bxxx1_0001: state <= INDY0; // odd 1 column
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8'bxxx1_01xx: state <= ZPX0; // odd 4,5,6,7 columns
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8'bxxx1_1001: state <= ABSX0; // odd 9 column
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8'bxxx1_11xx: state <= ABSX0; // odd C, D, E, F columns
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8'bxxxx_1010: state <= REG; // <shift> A, TXA, ... NOP
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endcase
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ZP0 : state <= write_back ? READ : FETCH;
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@ -958,7 +962,6 @@ always @(posedge clk)
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BRK1 : state <= BRK2;
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BRK2 : state <= BRK3;
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BRK3 : state <= JMP0;
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default : state <= BRK0;
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endcase
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@ -974,16 +977,16 @@ always @(posedge clk)
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always @(posedge clk)
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if( state == DECODE && RDY )
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casez( IR )
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8'b0??01010, // ASLA, ROLA, LSRA, RORA
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8'b0?????01, // ORA, AND, EOR, ADC
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8'b100?10?0, // DEY, TYA, TXA, TXS
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8'b1010???0, // LDA/LDX/LDY
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casex( IR )
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8'b0xx01010, // ASLA, ROLA, LSRA, RORA
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8'b0xxxxx01, // ORA, AND, EOR, ADC
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8'b100x10x0, // DEY, TYA, TXA, TXS
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8'b1010xxx0, // LDA/LDX/LDY
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8'b10111010, // TSX
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8'b1011?1?0, // LDX/LDY
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8'b1011x1x0, // LDX/LDY
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8'b11001010, // DEX
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8'b1?1???01, // LDA, SBC
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8'b11?01000: // DEY, TAY, INY, INX (88,a8,c8,e8)
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8'b1x1xxx01, // LDA, SBC
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8'bxxx01000: // DEY, TAY, INY, INX
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load_reg <= 1;
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default: load_reg <= 0;
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@ -991,19 +994,19 @@ always @(posedge clk)
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always @(posedge clk)
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if( state == DECODE && RDY )
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casez( IR )
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casex( IR )
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8'b1110_1000, // INX
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8'b1100_1010, // DEX
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8'b101?_??10: // LDX, TAX, TSX
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8'b101x_xx10: // LDX, TAX, TSX
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dst_reg <= SEL_X;
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8'b0?00_1000, // PHP, PHA
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8'b0x00_1000, // PHP, PHA
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8'b1001_1010: // TXS
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dst_reg <= SEL_S;
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8'b1?00_1000, // DEY, DEX
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8'b101?_?100, // LDY
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8'b1010_?000: // LDY #imm, TAY
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8'b1x00_1000, // DEY, DEX
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8'b101x_x100, // LDY
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8'b1010_x000: // LDY #imm, TAY
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dst_reg <= SEL_Y;
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default: dst_reg <= SEL_A;
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@ -1011,22 +1014,20 @@ always @(posedge clk)
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always @(posedge clk)
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if( state == DECODE && RDY )
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casez( IR )
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casex( IR )
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8'b1011_1010: // TSX
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src_reg <= SEL_S;
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8'b100?_?110, // STX
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8'b100?_1010, // TXA, TXS
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8'b1110_??00, // INX, CPX
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8'b100x_x110, // STX
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8'b100x_1x10, // TXA, TXS
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8'b1110_xx00, // INX, CPX
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8'b1100_1010: // DEX
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src_reg <= SEL_X;
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8'b100?_?100, // STY
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8'b100x_x100, // STY
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8'b1001_1000, // TYA
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8'b1100_0000, // CPY
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8'b1100_0010, // CPY
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8'b1100_1110, // CPY
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8'b1?00_1000: // DEY, INY
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8'b1100_xx00, // CPY
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8'b1x00_1000: // DEY, INY
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src_reg <= SEL_Y;
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default: src_reg <= SEL_A;
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@ -1034,10 +1035,10 @@ always @(posedge clk)
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always @(posedge clk)
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if( state == DECODE && RDY )
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casez( IR )
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8'b???1_0001, // INDY
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8'b10?1_?110, // LDX/STX zpg/abs, Y
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8'b????_1001: // abs, Y
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casex( IR )
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8'bxxx1_0001, // INDY
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8'b10x1_x110, // LDX/STX zpg/abs, Y
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8'bxxxx_1001: // abs, Y
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index_y <= 1;
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default: index_y <= 0;
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@ -1046,9 +1047,9 @@ always @(posedge clk)
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always @(posedge clk)
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if( state == DECODE && RDY )
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casez( IR )
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8'b100?_?1?0, // STX, STY
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8'b100?_??01: // STA
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casex( IR )
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8'b100x_x1x0, // STX, STY
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8'b100x_xx01: // STA
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store <= 1;
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default: store <= 0;
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@ -1057,9 +1058,9 @@ always @(posedge clk)
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always @(posedge clk )
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if( state == DECODE && RDY )
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casez( IR )
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8'b0???_?110, // ASL, ROL, LSR, ROR
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8'b11??_?110: // DEC/INC
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casex( IR )
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8'b0xxx_x110, // ASL, ROL, LSR, ROR
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8'b11xx_x110: // DEC/INC
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write_back <= 1;
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default: write_back <= 0;
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@ -1068,17 +1069,17 @@ always @(posedge clk )
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always @(posedge clk )
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if( state == DECODE && RDY )
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casez( IR )
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8'b101?_????: // LDA, LDX, LDY
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casex( IR )
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8'b101x_xxxx: // LDA, LDX, LDY
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load_only <= 1;
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default: load_only <= 0;
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endcase
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always @(posedge clk )
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if( state == DECODE && RDY )
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casez( IR )
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8'b111?_?110, // INC
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8'b11?0_1000: // INX, INY
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casex( IR )
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8'b111x_x110, // INC
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8'b11x0_1000: // INX, INY
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inc <= 1;
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default: inc <= 0;
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@ -1086,8 +1087,8 @@ always @(posedge clk )
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always @(posedge clk )
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if( (state == DECODE || state == BRK0) && RDY )
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casez( IR )
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8'b?11?_??01: // SBC, ADC
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casex( IR )
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8'bx11x_xx01: // SBC, ADC
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adc_sbc <= 1;
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default: adc_sbc <= 0;
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@ -1095,8 +1096,8 @@ always @(posedge clk )
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always @(posedge clk )
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if( (state == DECODE || state == BRK0) && RDY )
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casez( IR )
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8'b011?_??01: // ADC
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casex( IR )
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8'b011x_xx01: // ADC
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adc_bcd <= D;
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default: adc_bcd <= 0;
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@ -1104,9 +1105,9 @@ always @(posedge clk )
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always @(posedge clk )
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if( state == DECODE && RDY )
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casez( IR )
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8'b0???_?110, // ASL, ROL, LSR, ROR (abs, abs?, zpg, zpg?)
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8'b0???_1010: // ASL, ROL, LSR, ROR (acc)
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casex( IR )
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8'b0xxx_x110, // ASL, ROL, LSR, ROR (abs, absx, zpg, zpgx)
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8'b0xxx_1010: // ASL, ROL, LSR, ROR (acc)
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shift <= 1;
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default: shift <= 0;
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@ -1114,10 +1115,10 @@ always @(posedge clk )
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always @(posedge clk )
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if( state == DECODE && RDY )
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casez( IR )
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8'b11?0_0?00, // CPX, CPY (imm/zp)
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8'b11?0_1100, // CPX, CPY (abs)
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8'b110?_??01: // CMP
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casex( IR )
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8'b11x0_0x00, // CPX, CPY (imm/zp)
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8'b11x0_1100, // CPX, CPY (abs)
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8'b110x_xx01: // CMP
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compare <= 1;
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default: compare <= 0;
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@ -1125,8 +1126,8 @@ always @(posedge clk )
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always @(posedge clk )
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if( state == DECODE && RDY )
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casez( IR )
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8'b01??_??10: // ROR, LSR
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casex( IR )
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8'b01xx_xx10: // ROR, LSR
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shift_right <= 1;
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default: shift_right <= 0;
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@ -1134,9 +1135,9 @@ always @(posedge clk )
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always @(posedge clk )
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if( state == DECODE && RDY )
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casez( IR )
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8'b0?1?_1010, // ROL A, ROR A
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8'b0?1?_?110: // ROR, ROL
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casex( IR )
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8'b0x1x_1010, // ROL A, ROR A
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8'b0x1x_x110: // ROR, ROL
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rotate <= 1;
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default: rotate <= 0;
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@ -1144,25 +1145,25 @@ always @(posedge clk )
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always @(posedge clk )
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if( state == DECODE && RDY )
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casez( IR )
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8'b00??_??10: // ROL, ASL
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casex( IR )
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8'b00xx_xx10: // ROL, ASL
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op <= OP_ROL;
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8'b0010_?100: // BIT zp/abs
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8'b0010_x100: // BIT zp/abs
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op <= OP_AND;
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8'b01??_??10: // ROR, LSR
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8'b01xx_xx10: // ROR, LSR
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op <= OP_A;
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8'b1000_1000, // DEY
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8'b1100_1010, // DEX
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8'b110?_?110, // DEC
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8'b11??_??01, // CMP, SBC
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8'b11?0_0?00, // CPX, CPY (imm, zpg)
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8'b11?0_1100: op <= OP_SUB;
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8'b110x_x110, // DEC
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8'b11xx_xx01, // CMP, SBC
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8'b11x0_0x00, // CPX, CPY (imm, zpg)
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8'b11x0_1100: op <= OP_SUB;
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8'b010?_??01, // EOR
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8'b00??_??01: // ORA, AND
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8'b010x_xx01, // EOR
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8'b00xx_xx01: // ORA, AND
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op <= { 2'b11, IR[6:5] };
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default: op <= OP_ADD;
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@ -1170,13 +1171,12 @@ always @(posedge clk )
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always @(posedge clk )
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if( state == DECODE && RDY )
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casez( IR )
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8'b0010_?100: // BIT zp/abs
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casex( IR )
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8'b0010_x100: // BIT zp/abs
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bit_ins <= 1;
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default: bit_ins <= 0;
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endcase
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/*
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* special instructions
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*/
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