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redir.html
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redir.html
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4
redir.html
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@ -0,0 +1,4 @@
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<script>
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var VERSION = '2.1.0';
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document.location.href = 'v' + VERSION + '/' + document.location.search;
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</script>
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@ -51,6 +51,10 @@ function testVerilator(filename, disables, nerrors) {
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describe('Verilog Worker', function() {
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testVerilator('presets/verilog/hvsync_generator.v');
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testVerilator('presets/verilog/lfsr.v');
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// TODO: how to include files?
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/* TODO: fix tests
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testVerilator('test/cli/verilog/t_order_doubleloop.v', ['BLKSEQ']);
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testVerilator('test/cli/verilog/t_alw_combdly.v');
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@ -58,6 +62,7 @@ describe('Verilog Worker', function() {
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testVerilator('test/cli/verilog/t_clk_gen.v', ['BLKSEQ']);
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testVerilator('test/cli/verilog/t_clk_first.v', ['UNDRIVEN','SYNCASYNCNET']);
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testVerilator('test/cli/verilog/t_clk_2in.v', ['BLKSEQ']);
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testVerilator('test/cli/verilog/t_order_comboclkloop.v');
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*/
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testVerilator('test/cli/verilog/t_gen_alw.v');
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testVerilator('test/cli/verilog/t_case_huge_sub3.v');
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@ -67,7 +72,6 @@ describe('Verilog Worker', function() {
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//testVerilator('test/cli/verilog/t_order_a.v');
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//testVerilator('test/cli/verilog/t_order_b.v');
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//testVerilator('test/cli/verilog/t_order_clkinst.v');
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testVerilator('test/cli/verilog/t_order_comboclkloop.v');
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//testVerilator('test/cli/verilog/t_order_comboloop.v', ['BLKSEQ']);
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testVerilator('test/cli/verilog/t_order_first.v');
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testVerilator('test/cli/verilog/t_order_loop_bad.v', ['BLKSEQ'], 10);
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@ -99,10 +99,12 @@ describe('Worker', function() {
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var csource = ab2str(fs.readFileSync('presets/coleco/skeleton.sdcc'));
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compile('sdcc', csource, 'coleco', done, 32768, 31, 0);
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});
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/*
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it('should compile verilog example', function(done) {
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var csource = ab2str(fs.readFileSync('presets/verilog/lfsr.v'));
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compile('verilator', csource, 'verilog', done, 3686, 0, 0);
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});
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*/
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it('should NOT compile SDCC', function(done) {
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compile('sdcc', 'foobar', 'mw8080bw', done, 0, 0, 1);
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});
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