From 34d18858514d5d80e64f1038acae94efbdf66b2c Mon Sep 17 00:00:00 2001 From: Steven Hugg Date: Mon, 16 Sep 2019 19:24:51 -0500 Subject: [PATCH] apple2: load/save slots; fixed printFlags() --- src/machine/apple2.ts | 77 +++++++++++++++++++++++++++++++++++++----- src/platform/apple2.ts | 1 - src/util.ts | 4 +-- 3 files changed, 70 insertions(+), 12 deletions(-) diff --git a/src/machine/apple2.ts b/src/machine/apple2.ts index 6c96d821..2ab938cb 100644 --- a/src/machine/apple2.ts +++ b/src/machine/apple2.ts @@ -1,8 +1,8 @@ import { MOS6502, MOS6502State } from "../cpu/MOS6502"; -import { Bus, BasicScanlineMachine, xorshift32 } from "../devices"; +import { Bus, BasicScanlineMachine, xorshift32, SavesState } from "../devices"; import { KeyFlags } from "../emu"; // TODO -import { lzgmini, stringToByteArray, RGBA } from "../util"; +import { lzgmini, stringToByteArray, RGBA, printFlags } from "../util"; const cpuFrequency = 1023000; const cpuCyclesPerLine = 65; // approx: http://www.cs.columbia.edu/~sedwards/apple2fpga/ @@ -28,6 +28,7 @@ interface AppleIIControlsState { interface AppleIIState extends AppleIIStateBase, AppleIIControlsState { c : MOS6502State; grswitch : number; + slots: any[]; } interface SlotDevice extends Bus { @@ -105,6 +106,7 @@ export class AppleII extends BasicScanlineMachine { auxRAMselected: this.auxRAMselected, auxRAMbank: this.auxRAMbank, writeinhibit: this.writeinhibit, + slots: this.slots.map((slot) => { return slot && slot['saveState'] && slot['saveState']() }), inputs: null }; } @@ -119,6 +121,9 @@ export class AppleII extends BasicScanlineMachine { this.auxRAMbank = s.auxRAMbank; this.writeinhibit = s.writeinhibit; this.setupLanguageCardConstants(); + for (var i=0; i 0x10000-0x10fff } + + getDebugCategories() { + return ['CPU','Stack','I/O','Disk']; + } + getDebugInfo(category:string, state:AppleIIState) { + switch (category) { + case 'I/O': return "AUX RAM Bank: " + state.auxRAMbank + + "\nAUX RAM Select: " + state.auxRAMselected + + "\nAUX RAM Write: " + !state.writeinhibit + + "\n\nGR Switches: " + printFlags(state.grswitch, ["Graphics","Mixed","Page2","Hires"], false) + + "\n"; + case 'Disk': return (this.slots[6] && this.slots[6]['toLongString'] && this.slots[6]['toLongString']()) || "\n"; + } + } } const GR_TXMODE = 1; @@ -984,20 +1006,21 @@ const APPLEIIGO_LZG = `TFpHAAAwAAAABYxwdy2NARUZHjRBUFBMRUlJR08gUk9NMS4wADQfNB80H ,0x3D,0xCD,0x00,0x08,0xA6,0x2B,0x90,0xDB,0x4C,0x01,0x08,0x00,0x00,0x00,0x00,0x00 ]; -class DiskII implements SlotDevice { - - emu : AppleII; +class DiskIIState { data : Uint8Array[]; - track_data : Uint8Array; track : number = 0; read_mode : boolean = true; write_protect : boolean = false; motor : boolean = false; track_index : number = 0; - - // TODO: load, saveState +} +class DiskII extends DiskIIState implements SlotDevice, SavesState { + emu : AppleII; + track_data : Uint8Array; + constructor(emu : AppleII, image : Uint8Array) { + super(); this.emu = emu; this.data = new Array(NUM_TRACKS); for (var i=0; i>1]; + else + this.track_data = null; + } + + toLongString() { + return "Track: " + (this.track / 2) + + "\nOffset: " + (this.track_index) + + "\nMode: " + (this.read_mode ? "READ" : "WRITE") + + "\nMotor: " + this.motor + + "\n"; + } + read_latch() : number { this.track_index = (this.track_index + 1) % TRACK_SIZE; if (this.track_data) { @@ -1299,6 +1358,6 @@ class DiskII implements SlotDevice { while (out_pos < TRACK_SIZE) out[out_pos++] = (0xff); return out; - } + } diff --git a/src/platform/apple2.ts b/src/platform/apple2.ts index 7ebf10ab..78a959c9 100644 --- a/src/platform/apple2.ts +++ b/src/platform/apple2.ts @@ -66,7 +66,6 @@ class NewApple2Platform extends Base6502MachinePlatform implements Plat {name:'I/O',start:0xc000,size:0x1000,type:'io'}, {name:'ROM',start:0xd000,size:0x3000-6,type:'rom'}, ] } }; - } PLATFORMS['apple2.mame'] = Apple2MAMEPlatform; diff --git a/src/util.ts b/src/util.ts index c5157a0e..d8ef62f2 100644 --- a/src/util.ts +++ b/src/util.ts @@ -401,9 +401,9 @@ export function printFlags(val:number, names:string[], r2l:boolean) { var s = ''; for (var i=0; i 0) s += " "; - s += (val & (1<