diff --git a/images/book_a2600.png b/images/book_a2600.png
index 591b1ddb..d7a9831d 100644
Binary files a/images/book_a2600.png and b/images/book_a2600.png differ
diff --git a/images/book_verilog.png b/images/book_verilog.png
new file mode 100644
index 00000000..56767a79
Binary files /dev/null and b/images/book_verilog.png differ
diff --git a/index.html b/index.html
index 9d5818f4..b71271cb 100644
--- a/index.html
+++ b/index.html
@@ -118,14 +118,12 @@ if (window.location.host.endsWith('8bitworkshop.com')) {
Williams Sound (Z80)
-
diff --git a/presets/verilog/binary_counter.v b/presets/verilog/binary_counter.v
new file mode 100644
index 00000000..c180d576
--- /dev/null
+++ b/presets/verilog/binary_counter.v
@@ -0,0 +1,50 @@
+
+/*
+A clock divider in Verilog, using both the cascading
+flip-flop method and the binary counter method.
+*/
+
+module clock_divider(
+ input clk,
+ input reset,
+ output reg clk_div2,
+ output reg clk_div4,
+ output reg clk_div8,
+ output reg clk_div16,
+ output reg [3:0] counter,
+ output cntr_div2,
+ output cntr_div4,
+ output cntr_div8,
+ output cntr_div16
+);
+
+ // simple ripple clock divider
+
+ always @(posedge clk)
+ clk_div2 <= ~clk_div2;
+
+ always @(posedge clk_div2)
+ clk_div4 <= ~clk_div4;
+
+ always @(posedge clk_div4)
+ clk_div8 <= ~clk_div8;
+
+ always @(posedge clk_div8)
+ clk_div16 <= ~clk_div16;
+
+ // use bits of (4-bit) counter to divide clocks
+
+ always @(posedge clk or posedge reset)
+ begin
+ if (reset)
+ counter <= 0;
+ else
+ counter <= counter + 1;
+ end
+
+ assign cntr_div2 = counter[0];
+ assign cntr_div4 = counter[1];
+ assign cntr_div8 = counter[2];
+ assign cntr_div16 = counter[3];
+
+endmodule
diff --git a/presets/verilog/clock_divider.v b/presets/verilog/clock_divider.v
index b1f4b56f..29f7c250 100644
--- a/presets/verilog/clock_divider.v
+++ b/presets/verilog/clock_divider.v
@@ -1,7 +1,7 @@
/*
-A clock divider in Verilog, using both the cascading
-flip-flop method and the counter method.
+A clock divider in Verilog, using the cascading
+flip-flop method.
*/
module clock_divider(
@@ -10,12 +10,7 @@ module clock_divider(
output reg clk_div2,
output reg clk_div4,
output reg clk_div8,
- output reg clk_div16,
- output reg [3:0] counter,
- output cntr_div2,
- output cntr_div4,
- output cntr_div8,
- output cntr_div16
+ output reg clk_div16
);
// simple ripple clock divider
@@ -32,17 +27,4 @@ module clock_divider(
always @(posedge clk_div8)
clk_div16 <= ~clk_div16;
- // use bits of (4-bit) counter to divide clocks
-
- always @(posedge clk or posedge reset)
- if (reset)
- counter <= 0;
- else
- counter <= counter + 1;
-
- assign cntr_div2 = counter[0];
- assign cntr_div4 = counter[1];
- assign cntr_div8 = counter[2];
- assign cntr_div16 = counter[3];
-
endmodule
diff --git a/src/platform/verilog.ts b/src/platform/verilog.ts
index 09a85524..2b55b9cf 100644
--- a/src/platform/verilog.ts
+++ b/src/platform/verilog.ts
@@ -10,6 +10,7 @@ declare var Split;
var VERILOG_PRESETS = [
{id:'clock_divider.v', name:'Clock Divider'},
+ {id:'binary_counter.v', name:'Binary Counter'},
{id:'hvsync_generator.v', name:'Video Sync Generator'},
{id:'test_hvsync.v', name:'Test Pattern'},
{id:'7segment.v', name:'7-Segment Decoder'},
- -->
Making 8-bit Arcade Games in C
-