From 85bf12a9704a7688667e2fb80ec56328615ffafd Mon Sep 17 00:00:00 2001 From: Steven Hugg Date: Tue, 2 May 2017 09:09:53 -0400 Subject: [PATCH] added libcv/libcvu for coleco --- presets/coleco/cursorsmooth.c | 100 + presets/coleco/hello.c | 85 + presets/coleco/huffman.c | 323 + presets/coleco/siegegame.c | 289 + presets/coleco/simplemusic.c | 23 + presets/coleco/stars.c | 81 + presets/coleco/text.c | 29 + presets/coleco/text32.c | 88 + presets/vicdual/hello.c | 4 +- src/emu.js | 13 +- src/platform/coleco.js | 12 +- src/ui.js | 28 +- src/worker/fssdcc.data | 25881 ++++++++++++++++++++++++++++---- src/worker/fssdcc.js | 13 +- src/worker/fssdcc.js.metadata | 2 +- src/worker/workermain.js | 70 +- 16 files changed, 24143 insertions(+), 2898 deletions(-) create mode 100644 presets/coleco/cursorsmooth.c create mode 100644 presets/coleco/hello.c create mode 100644 presets/coleco/huffman.c create mode 100644 presets/coleco/siegegame.c create mode 100644 presets/coleco/simplemusic.c create mode 100644 presets/coleco/stars.c create mode 100644 presets/coleco/text.c create mode 100644 presets/coleco/text32.c diff --git a/presets/coleco/cursorsmooth.c b/presets/coleco/cursorsmooth.c new file mode 100644 index 00000000..b0d60fd6 --- /dev/null +++ b/presets/coleco/cursorsmooth.c @@ -0,0 +1,100 @@ + +#include + +const uint8_t sprite[0x1][0x20] = { + {0xa0, 0x40, 0xa0, 0x10, 0xa, 0x4, 0xa, 0, 0, 0xa, 0x4, 0xa, 0x10, 0xa0, 0x40, 0xa0, 0x5, 0x2, 0x5, 0x8, 0x50, 0x20, 0x50, 0, 0, 0x50, 0x20, 0x50, 0x8, 0x5, 0x2, 0x5} +}; + +#include "cv.h" +#include "cvu.h" + +/* VRAM map + 0x0000 - 0x17ff character pattern table + 0x1800 - 0x1aff image table + 0x2000 - 0x37ff color table + 0x3800 - 0x3bff sprite pattern table + 0x3c00 - 0x3fff sprite attribute table +*/ + +const cv_vmemp IMAGE = 0x1800; +const cv_vmemp SPRITES = 0x3c00; +const cv_vmemp SPRITE_PATTERNS = 0x3800; + +volatile bool step; // Has to be volatile since it's modified in the NMI handler. + +void move_cursor(struct cvu_sprite *s) +{ + int x, y; + struct cv_controller_state cs; + + cv_get_controller_state(&cs, 0); // Read the controller. + + x = cvu_get_sprite_x(s); + y = cvu_get_sprite_y(s); + + if(cs.joystick & CV_RIGHT) // Move cursor to the right by one pixel. + x++; + else if(cs.joystick & CV_LEFT) // Move the cursor to the left by one pixel. + x--; + if(cs.joystick & CV_DOWN) // Move the cursor down by one pixel. + y++; + else if(cs.joystick & CV_UP) // Move the cursor up by one pixel. + y--; + + // Move cursor by how much the wheels on the super action controllers or the ball in the roller controller indicate. + x += cvu_get_spinner(0); + y += cvu_get_spinner(1); + + // Limit to area. + if(x > 239) + x = 239; + else if(x < 0) + x = 0; + if(y > 152) + y = 152; + else if(y < 0) + y = 0; + + cvu_set_sprite_xy(s, x, y); + + cvu_set_sprite(SPRITES, 0, s); // Update the cursor on the screen. +} + +void nmi(void) +{ + step = true; +} + +void main(void) +{ + struct cvu_sprite s; // The sprite used for the cursor. + + cv_set_screen_active(false); // Switch screen off. + + cv_set_color_table(0x3fff); + cv_set_character_pattern_t(0x1fff); + cv_set_image_table(IMAGE); + cv_set_sprite_pattern_table(SPRITE_PATTERNS); + cv_set_sprite_attribute_table(SPRITES); + cv_set_screen_mode(CV_SCREENMODE_BITMAP); // Doesn't really matter much here. We only need a screen mode that supports sprites. + cvu_vmemset(0x2000, (CV_COLOR_BLACK << 4) | CV_COLOR_BLACK, 6144); // Set both colors for all characters to black to get a black background. + + cv_set_sprite_magnification(false); + cv_set_sprite_big(true); // 16x16 pixel sprites. + + cvu_set_sprite_x(&s, 60); // Set initial cursor position. + cvu_set_sprite_y(&s, 60); // Set initial cursor position. + cvu_set_sprite_color(&s, CV_COLOR_WHITE); + s.name = 0; // Use sprite pattern number 0. + cvu_memtovmemcpy(SPRITE_PATTERNS, sprite, 0x20); // Copy sprite pattern number 0 to graphics memory. + + cv_set_screen_active(true); // Switch screen on. + + cv_set_vint_handler(nmi); + for(;;) + { + step = false; + while(!step); // Wait until the NMI handler sets step to true. + move_cursor(&s); + } +} diff --git a/presets/coleco/hello.c b/presets/coleco/hello.c new file mode 100644 index 00000000..775fb243 --- /dev/null +++ b/presets/coleco/hello.c @@ -0,0 +1,85 @@ + +#include +#include +#include + +#include "cv.h" +#include "cvu.h" + +#define IMAGE ((const cv_vmemp)0x1c00) + +#define COLS 40 +#define ROWS 24 + +uintptr_t __at(0x6a) font_bitmap_a; +uintptr_t __at(0x6c) font_bitmap_0; + +void setup_40_column_font() { + cv_set_image_table(IMAGE); + cvu_memtovmemcpy(0x1800, (void *)(font_bitmap_0 - 0x30*8), 2048); + cv_set_character_pattern_t(0x1800); + cv_set_screen_mode(CV_SCREENMODE_TEXT); +} + +char cursor_x; +char cursor_y; + +void clrscr() { + cvu_vmemset(IMAGE, ' ', COLS*ROWS); +} + +void setup_stdio() { + cursor_x = 0; + cursor_y = 0; + clrscr(); +} + +void scrollup() { + char buf[COLS]; + char y; + for (y=0; y= ROWS-1) { + scrollup(); + } else { + cursor_y++; + } +} + +int putchar(int ch) { + switch (ch) { + case '\n': + newline(); // TODO: scrolling + case '\r': + cursor_x = 0; + return 0; + } + cvu_voutb(ch, IMAGE + COLS*cursor_y + cursor_x); + cursor_x++; + if (cursor_x >= COLS) { + newline(); + cursor_x = 0; + } +} + +void main() { + unsigned char byteval = 123; + signed char charval = 123; + short shortval = 12345; + + setup_40_column_font(); + setup_stdio(); + cv_set_colors(CV_COLOR_LIGHT_GREEN, CV_COLOR_BLACK); + cv_set_screen_active(true); + printf("HELLO WORLD!\n"); + while (1) { + printf("char %d byte %u sh %d\n", + charval++, byteval++, shortval++); + } +} diff --git a/presets/coleco/huffman.c b/presets/coleco/huffman.c new file mode 100644 index 00000000..056c8d1b --- /dev/null +++ b/presets/coleco/huffman.c @@ -0,0 +1,323 @@ + +// Huffman tree generated by ColecoVision huffman_analyzer. +// Nodes below HUFFMAN_LS are inner nodes. +// Nodes from HUFFMAN_LS to HUFFMAN_BS - 1 only have a right child node. +// Nodes from HUFFMAN_BS to HUFFMAN_RS - 1 do not have child nodes. +// Nodes from HUFFMAN_RS onward only have a left child node. + +#include "cvu_compression.h" + +#include "cvu.h" + +#define RLE_ESCAPE (const uint8_t)(253) + +#define PATTERN ((const cv_vmemp)0x0000) +#define COLOR ((const cv_vmemp)0x2000) +#define IMAGE ((const cv_vmemp)0x1c00) +#define SPRITES ((const cv_vmemp)0x3c00) + +extern const unsigned char color[]; +extern const unsigned char pattern[]; + +extern const uint8_t HUFFMAN_ROOT; +extern const uint8_t HUFFMAN_LS, HUFFMAN_BS, HUFFMAN_RS; +extern const struct cvu_huffman_node huffman_tree[255]; + +void main(void) +{ + unsigned int i; + struct cvu_compression_state state; + + cv_set_screen_active(false); + cv_set_image_table(IMAGE); + cv_set_color_table(0x3fff); + cv_set_character_pattern_t(0x1fff); + cv_set_screen_mode(CV_SCREENMODE_BITMAP); + + // Make all sprites transparent. + cv_set_sprite_attribute_table(SPRITES); + for(i = 0; i < 32; i++) + { + struct cvu_sprite s; + cvu_set_sprite_color(&s, CV_COLOR_TRANSPARENT); + cvu_set_sprite(SPRITES, i, &s); + } + + // Decompress image data to video memory. + cvu_init_compression(pattern, &state, huffman_tree, HUFFMAN_ROOT, HUFFMAN_LS, HUFFMAN_BS, HUFFMAN_RS, RLE_ESCAPE); + cvu_memtovmemcpy_compression(PATTERN,& state, 6144); + cvu_init_compression(color, &state, huffman_tree, HUFFMAN_ROOT, HUFFMAN_LS, HUFFMAN_BS, HUFFMAN_RS, RLE_ESCAPE); + cvu_memtovmemcpy_compression(COLOR, &state, 6144); + + for(i = 0; i < 768; i++) + cvu_voutb(i % 256, IMAGE + i); + + cv_set_screen_active(true); + + for(;;); +} + +const uint8_t HUFFMAN_ROOT = 108; +const uint8_t HUFFMAN_LS = 109, HUFFMAN_BS = 124, HUFFMAN_RS = 234; +const struct cvu_huffman_node huffman_tree[255] = { + +/* Node 0 */ {125, 126}, +/* Node 1 */ {127, 128}, +/* Node 2 */ {129, 130}, +/* Node 3 */ {131, 132}, +/* Node 4 */ {133, 134}, +/* Node 5 */ {135, 136}, +/* Node 6 */ {137, 138}, +/* Node 7 */ {139, 140}, +/* Node 8 */ {141, 142}, +/* Node 9 */ {143, 144}, +/* Node 10 */ {145, 146}, +/* Node 11 */ {147, 148}, +/* Node 12 */ {149, 150}, +/* Node 13 */ {151, 152}, +/* Node 14 */ {153, 154}, +/* Node 15 */ {155, 156}, +/* Node 16 */ {157, 158}, +/* Node 17 */ {159, 160}, +/* Node 18 */ {161, 162}, +/* Node 19 */ {163, 164}, +/* Node 20 */ {165, 166}, +/* Node 21 */ {167, 168}, +/* Node 22 */ {169, 170}, +/* Node 23 */ {171, 172}, +/* Node 24 */ {173, 174}, +/* Node 25 */ {175, 176}, +/* Node 26 */ {177, 178}, +/* Node 27 */ {179, 180}, +/* Node 28 */ {181, 182}, +/* Node 29 */ {183, 184}, +/* Node 30 */ {109, 0}, +/* Node 31 */ {1, 2}, +/* Node 32 */ {3, 4}, +/* Node 33 */ {5, 6}, +/* Node 34 */ {7, 8}, +/* Node 35 */ {9, 10}, +/* Node 36 */ {11, 12}, +/* Node 37 */ {13, 14}, +/* Node 38 */ {15, 16}, +/* Node 39 */ {17, 18}, +/* Node 40 */ {19, 20}, +/* Node 41 */ {21, 22}, +/* Node 42 */ {23, 24}, +/* Node 43 */ {25, 26}, +/* Node 44 */ {27, 28}, +/* Node 45 */ {29, 30}, +/* Node 46 */ {31, 32}, +/* Node 47 */ {33, 34}, +/* Node 48 */ {35, 36}, +/* Node 49 */ {37, 38}, +/* Node 50 */ {39, 40}, +/* Node 51 */ {41, 42}, +/* Node 52 */ {43, 44}, +/* Node 53 */ {45, 46}, +/* Node 54 */ {47, 48}, +/* Node 55 */ {49, 50}, +/* Node 56 */ {51, 52}, +/* Node 57 */ {53, 54}, +/* Node 58 */ {55, 56}, +/* Node 59 */ {57, 58}, +/* Node 60 */ {185, 186}, +/* Node 61 */ {187, 188}, +/* Node 62 */ {189, 190}, +/* Node 63 */ {191, 192}, +/* Node 64 */ {193, 194}, +/* Node 65 */ {195, 196}, +/* Node 66 */ {197, 198}, +/* Node 67 */ {199, 200}, +/* Node 68 */ {201, 202}, +/* Node 69 */ {203, 204}, +/* Node 70 */ {205, 206}, +/* Node 71 */ {207, 208}, +/* Node 72 */ {209, 210}, +/* Node 73 */ {60, 61}, +/* Node 74 */ {62, 63}, +/* Node 75 */ {64, 65}, +/* Node 76 */ {66, 67}, +/* Node 77 */ {212, 213}, +/* Node 78 */ {214, 215}, +/* Node 79 */ {216, 217}, +/* Node 80 */ {218, 219}, +/* Node 81 */ {220, 221}, +/* Node 82 */ {68, 69}, +/* Node 83 */ {70, 71}, +/* Node 84 */ {72, 73}, +/* Node 85 */ {74, 75}, +/* Node 86 */ {223, 224}, +/* Node 87 */ {226, 110}, +/* Node 88 */ {77, 78}, +/* Node 89 */ {81, 82}, +/* Node 90 */ {83, 84}, +/* Node 91 */ {87, 88}, +/* Node 92 */ {239, 230}, +/* Node 93 */ {89, 90}, +/* Node 94 */ {244, 117}, +/* Node 95 */ {91, 231}, +/* Node 96 */ {118, 93}, +/* Node 97 */ {119, 232}, +/* Node 98 */ {248, 233}, +/* Node 99 */ {249, 250}, +/* Node 100 */ {95, 120}, +/* Node 101 */ {121, 251}, +/* Node 102 */ {122, 97}, +/* Node 103 */ {98, 99}, +/* Node 104 */ {252, 100}, +/* Node 105 */ {123, 102}, +/* Node 106 */ {104, 253}, +/* Node 107 */ {105, 254}, +/* Node 108 */ {106, 107}, +/* Node 109 */ {250, 124}, +/* Node 110 */ {247, 211}, +/* Node 111 */ {243, 222}, +/* Node 112 */ {60, 225}, +/* Node 113 */ {249, 237}, +/* Node 114 */ {8, 80}, +/* Node 115 */ {241, 228}, +/* Node 116 */ {227, 111}, +/* Node 117 */ {135, 112}, +/* Node 118 */ {240, 114}, +/* Node 119 */ {254, 242}, +/* Node 120 */ {4, 92}, +/* Node 121 */ {31, 245}, +/* Node 122 */ {127, 247}, +/* Node 123 */ {3, 96}, +/* Node 124 */ {10, 32}, +/* Node 125 */ {33, 36}, +/* Node 126 */ {37, 38}, +/* Node 127 */ {41, 42}, +/* Node 128 */ {43, 44}, +/* Node 129 */ {50, 52}, +/* Node 130 */ {54, 58}, +/* Node 131 */ {64, 67}, +/* Node 132 */ {68, 69}, +/* Node 133 */ {70, 71}, +/* Node 134 */ {72, 73}, +/* Node 135 */ {74, 75}, +/* Node 136 */ {76, 77}, +/* Node 137 */ {78, 80}, +/* Node 138 */ {81, 82}, +/* Node 139 */ {83, 84}, +/* Node 140 */ {85, 86}, +/* Node 141 */ {87, 88}, +/* Node 142 */ {90, 91}, +/* Node 143 */ {92, 93}, +/* Node 144 */ {94, 95}, +/* Node 145 */ {96, 97}, +/* Node 146 */ {98, 100}, +/* Node 147 */ {101, 102}, +/* Node 148 */ {104, 105}, +/* Node 149 */ {106, 107}, +/* Node 150 */ {108, 109}, +/* Node 151 */ {110, 114}, +/* Node 152 */ {117, 122}, +/* Node 153 */ {125, 130}, +/* Node 154 */ {137, 141}, +/* Node 155 */ {144, 146}, +/* Node 156 */ {147, 148}, +/* Node 157 */ {149, 150}, +/* Node 158 */ {151, 154}, +/* Node 159 */ {160, 161}, +/* Node 160 */ {162, 163}, +/* Node 161 */ {164, 165}, +/* Node 162 */ {166, 167}, +/* Node 163 */ {168, 169}, +/* Node 164 */ {170, 171}, +/* Node 165 */ {172, 173}, +/* Node 166 */ {174, 175}, +/* Node 167 */ {176, 177}, +/* Node 168 */ {178, 179}, +/* Node 169 */ {180, 181}, +/* Node 170 */ {182, 183}, +/* Node 171 */ {184, 186}, +/* Node 172 */ {187, 188}, +/* Node 173 */ {194, 200}, +/* Node 174 */ {201, 202}, +/* Node 175 */ {209, 210}, +/* Node 176 */ {211, 212}, +/* Node 177 */ {213, 214}, +/* Node 178 */ {215, 216}, +/* Node 179 */ {217, 218}, +/* Node 180 */ {219, 221}, +/* Node 181 */ {228, 229}, +/* Node 182 */ {233, 234}, +/* Node 183 */ {235, 237}, +/* Node 184 */ {244, 245}, +/* Node 185 */ {13, 35}, +/* Node 186 */ {39, 40}, +/* Node 187 */ {45, 46}, +/* Node 188 */ {48, 49}, +/* Node 189 */ {53, 66}, +/* Node 190 */ {79, 89}, +/* Node 191 */ {103, 111}, +/* Node 192 */ {116, 133}, +/* Node 193 */ {134, 138}, +/* Node 194 */ {139, 145}, +/* Node 195 */ {153, 155}, +/* Node 196 */ {158, 185}, +/* Node 197 */ {189, 190}, +/* Node 198 */ {191, 196}, +/* Node 199 */ {198, 205}, +/* Node 200 */ {208, 236}, +/* Node 201 */ {11, 14}, +/* Node 202 */ {17, 19}, +/* Node 203 */ {20, 34}, +/* Node 204 */ {59, 61}, +/* Node 205 */ {65, 99}, +/* Node 206 */ {112, 113}, +/* Node 207 */ {120, 140}, +/* Node 208 */ {157, 203}, +/* Node 209 */ {204, 220}, +/* Node 210 */ {226, 238}, +/* Node 211 */ {26, 47}, +/* Node 212 */ {56, 119}, +/* Node 213 */ {123, 129}, +/* Node 214 */ {132, 136}, +/* Node 215 */ {152, 197}, +/* Node 216 */ {223, 232}, +/* Node 217 */ {246, 251}, +/* Node 218 */ {22, 25}, +/* Node 219 */ {27, 51}, +/* Node 220 */ {55, 118}, +/* Node 221 */ {222, 242}, +/* Node 222 */ {12, 21}, +/* Node 223 */ {29, 57}, +/* Node 224 */ {156, 239}, +/* Node 225 */ {16, 23}, +/* Node 226 */ {28, 131}, +/* Node 227 */ {124, 206}, +/* Node 228 */ {121, 142}, +/* Node 229 */ {230, 30}, +/* Node 230 */ {115, 126}, +/* Node 231 */ {6, 195}, +/* Node 232 */ {224, 252}, +/* Node 233 */ {15, 143}, +/* Node 234 */ {59, 2}, +/* Node 235 */ {234, 9}, +/* Node 236 */ {235, 18}, +/* Node 237 */ {236, 193}, +/* Node 238 */ {76, 24}, +/* Node 239 */ {79, 62}, +/* Node 240 */ {227, 1}, +/* Node 241 */ {85, 225}, +/* Node 242 */ {238, 231}, +/* Node 243 */ {229, 207}, +/* Node 244 */ {86, 159}, +/* Node 245 */ {240, 0}, +/* Node 246 */ {113, 199}, +/* Node 247 */ {241, 128}, +/* Node 248 */ {115, 192}, +/* Node 249 */ {243, 248}, +/* Node 250 */ {116, 5}, +/* Node 251 */ {246, 63}, +/* Node 252 */ {94, 7}, +/* Node 253 */ {101, 255}, +/* Node 254 */ {103, 253}}; +// Huffman-encoded data encoded by ColecoVision huffman encoder. + +const uint8_t color[] = { 151, 179, 58, 64, 86, 231, 40, 158, 15, 165, 207, 91, 28, 149, 102, 253, 148, 210, 39, 226, 112, 89, 127, 32, 14, 159, 205, 57, 138, 71, 54, 223, 183, 159, 229, 240, 109, 219, 207, 177, 245, 251, 246, 71, 154, 83, 219, 79, 165, 121, 203, 91, 143, 105, 224, 159, 239, 52, 111, 89, 235, 101, 120, 248, 203, 173, 173, 173, 223, 211, 158, 145, 190, 34, 237, 131, 216, 169, 180, 87, 16, 75, 247, 149, 216, 229, 116, 233, 46, 19, 16, 16, 124, 7, 56, 83, 190, 2, 224, 177, 120, 10, 224, 138, 69, 241, 117, 241, 178, 184, 44, 46, 139, 203, 226, 178, 0}; + +const uint8_t pattern[] = { 151, 125, 0, 247, 9, 253, 221, 40, 77, 190, 155, 3, 40, 190, 221, 227, 184, 126, 247, 163, 188, 2, 78, 146, 254, 187, 101, 25, 191, 187, 239, 79, 89, 150, 241, 148, 7, 201, 23, 173, 210, 207, 222, 221, 88, 159, 114, 209, 118, 211, 244, 253, 186, 206, 66, 104, 253, 40, 125, 115, 202, 226, 49, 205, 243, 114, 121, 244, 122, 180, 126, 106, 125, 170, 28, 157, 28, 93, 142, 110, 142, 158, 62, 25, 155, 230, 148, 31, 19, 66, 16, 33, 125, 116, 51, 207, 15, 80, 235, 146, 12, 190, 91, 250, 201, 113, 52, 140, 86, 191, 27, 63, 25, 143, 94, 143, 206, 242, 104, 60, 156, 207, 234, 177, 115, 119, 166, 203, 195, 79, 173, 79, 149, 103, 233, 70, 178, 163, 161, 105, 122, 136, 9, 162, 55, 103, 213, 167, 214, 179, 194, 231, 75, 72, 140, 208, 36, 132, 214, 178, 152, 85, 154, 222, 208, 210, 53, 169, 62, 104, 8, 138, 179, 234, 192, 238, 215, 164, 90, 221, 208, 180, 52, 167, 245, 123, 111, 151, 114, 166, 149, 171, 213, 46, 73, 214, 181, 105, 250, 94, 49, 52, 196, 43, 229, 148, 165, 199, 106, 223, 63, 20, 107, 223, 200, 107, 99, 23, 148, 97, 103, 250, 97, 60, 66, 253, 154, 84, 171, 27, 154, 150, 230, 180, 126, 239, 87, 151, 114, 166, 183, 41, 25, 120, 54, 133, 114, 247, 61, 57, 156, 199, 239, 245, 216, 149, 239, 186, 120, 237, 251, 230, 204, 165, 104, 45, 38, 186, 251, 238, 102, 149, 37, 37, 103, 80, 232, 226, 135, 152, 166, 89, 237, 206, 170, 27, 26, 154, 78, 173, 201, 248, 144, 224, 243, 75, 153, 100, 173, 133, 152, 176, 150, 62, 172, 216, 82, 39, 8, 34, 164, 105, 229, 46, 57, 115, 175, 24, 4, 77, 111, 170, 213, 193, 122, 170, 95, 19, 233, 153, 46, 197, 126, 244, 77, 243, 112, 250, 124, 33, 62, 38, 241, 148, 79, 85, 149, 107, 91, 161, 120, 172, 173, 245, 250, 112, 225, 202, 90, 139, 7, 168, 249, 167, 32, 148, 105, 122, 83, 173, 14, 86, 137, 239, 253, 154, 72, 207, 116, 41, 94, 143, 147, 244, 152, 212, 71, 139, 43, 233, 110, 252, 94, 219, 229, 187, 126, 202, 253, 209, 248, 201, 235, 209, 250, 232, 241, 232, 233, 232, 228, 104, 125, 116, 127, 244, 244, 201, 120, 120, 131, 159, 92, 31, 157, 246, 232, 250, 232, 230, 104, 249, 232, 114, 52, 30, 189, 30, 45, 61, 186, 62, 90, 124, 242, 216, 185, 27, 207, 234, 135, 92, 30, 250, 41, 139, 7, 88, 233, 92, 115, 5, 50, 17, 81, 123, 124, 180, 13, 12, 188, 36, 253, 88, 158, 57, 85, 137, 225, 225, 51, 19, 145, 44, 5, 24, 88, 50, 83, 166, 71, 11, 30, 197, 100, 36, 219, 11, 103, 206, 150, 71, 50, 195, 153, 225, 0, 115, 35, 119, 102, 178, 121, 100, 202, 116, 230, 10, 182, 73, 230, 120, 102, 173, 249, 252, 51, 67, 233, 51, 242, 155, 135, 103, 30, 143, 212, 119, 205, 133, 193, 206, 44, 42, 186, 176, 112, 102, 40, 125, 70, 254, 153, 135, 121, 60, 82, 103, 134, 203, 62, 183, 202, 182, 219, 246, 252, 88, 158, 185, 146, 233, 179, 19, 32, 104, 107, 46, 12, 118, 102, 130, 133, 5, 78, 103, 206, 177, 194, 128, 128, 167, 220, 52, 103, 30, 206, 192, 227, 157, 153, 196, 3, 118, 56, 215, 245, 216, 185, 27, 107, 173, 203, 195, 69, 159, 185, 121, 248, 12, 72, 126, 184, 221, 94, 200, 43, 255, 15, 47, 151, 45, 37, 191, 121, 248, 108, 184, 126, 204, 143, 146, 145, 211, 195, 15, 82, 68, 68, 15, 231, 53, 24, 40, 56, 63, 76, 156, 248, 12, 130, 15, 147, 109, 113, 75, 22, 242, 126, 184, 133, 45, 210, 165, 60, 156, 173, 210, 214, 202, 84, 254, 225, 71, 35, 185, 124, 248, 193, 207, 48, 61, 60, 52, 196, 227, 145, 121, 248, 12, 54, 61, 76, 53, 77, 198, 233, 225, 7, 63, 195, 244, 240, 208, 16, 143, 7, 61, 156, 123, 238, 106, 27, 248, 225, 179, 37, 233, 135, 9, 7, 67, 128, 74, 124, 248, 1, 227, 226, 195, 153, 51, 47, 44, 108, 123, 248, 49, 68, 66, 126, 248, 209, 72, 86, 232, 225, 40, 37, 59, 232, 225, 7, 140, 28, 153, 163, 203, 179, 240, 89, 61, 118, 238, 206, 116, 121, 62, 29, 95, 122, 252, 94, 143, 93, 249, 174, 203, 51, 187, 27, 191, 215, 118, 249, 174, 159, 120, 236, 220, 141, 103, 245, 67, 46, 15, 253, 196, 117, 61, 118, 238, 198, 90, 235, 242, 112, 209, 79, 124, 86, 143, 157, 187, 51, 93, 190, 229, 241, 123, 61, 118, 229, 187, 46, 207, 236, 110, 252, 94, 219, 229, 187, 126, 226, 177, 115, 55, 158, 213, 15, 185, 60, 244, 19, 215, 245, 216, 185, 27, 107, 173, 203, 195, 69, 63, 241, 89, 61, 118, 238, 206, 116, 249, 150, 199, 239, 245, 216, 149, 239, 186, 156, 147, 123, 197, 214, 153, 99, 109, 190, 27, 124, 136, 87, 204, 224, 12, 62, 63, 110, 142, 198, 135, 122, 18, 110, 183, 85, 117, 249, 152, 159, 178, 120, 128, 118, 211, 63, 172, 76, 192, 45, 229, 225, 181, 225, 115, 23, 31, 206, 95, 126, 23, 181, 126, 120, 173, 8, 113, 33, 30, 230, 11, 49, 207, 15, 111, 171, 20, 52, 207, 15, 235, 121, 169, 182, 31, 166, 42, 254, 160, 31, 22, 149, 27, 6, 90, 31, 38, 4, 148, 232, 251, 135, 27, 133, 98, 40, 231, 135, 211, 109, 182, 56, 115, 126, 56, 121, 44, 231, 135, 243, 92, 4, 57, 112, 120, 248, 76, 44, 62, 220, 13, 131, 90, 63, 220, 23, 13, 206, 15, 183, 194, 79, 66, 60, 92, 132, 152, 231, 103, 225, 68, 93, 206, 243, 153, 138, 144, 170, 62, 188, 110, 218, 203, 249, 97, 13, 46, 85, 245, 97, 138, 60, 173, 170, 15, 139, 60, 200, 111, 54, 15, 79, 155, 205, 96, 240, 112, 63, 216, 106, 171, 15, 139, 101, 123, 107, 48, 47, 85, 181, 189, 25, 244, 167, 220, 60, 250, 60, 129, 128, 184, 92, 159, 42, 92, 130, 239, 139, 92, 174, 196, 81, 115, 159, 18, 199, 121, 58, 53, 67, 132, 223, 55, 170, 58, 31, 85, 232, 251, 218, 247, 77, 47, 63, 92, 248, 176, 92, 114, 105, 188, 197, 203, 57, 17, 33, 85, 126, 40, 6, 227, 152, 52, 32, 56, 67, 22, 211, 244, 88, 14, 127, 95, 124, 136, 83, 90, 12, 127, 159, 65, 161, 159, 18, 79, 205, 79, 249, 187, 152, 231, 163, 10, 225, 92, 63, 102, 85, 221, 168, 248, 48, 81, 123, 121, 84, 161, 227, 134, 62, 14, 170, 223, 213, 246, 230, 212, 96, 107, 163, 62, 101, 233, 39, 43, 31, 189, 30, 189, 237, 104, 234, 232, 248, 238, 198, 100, 191, 207, 82, 235, 163, 229, 79, 38, 60, 122, 235, 104, 60, 154, 220, 209, 220, 163, 227, 232, 238, 232, 254, 104, 234, 232, 248, 228, 228, 232, 28, 142, 94, 143, 214, 71, 75, 143, 174, 143, 30, 143, 150, 56, 90, 28, 13}; diff --git a/presets/coleco/siegegame.c b/presets/coleco/siegegame.c new file mode 100644 index 00000000..1dcf12fe --- /dev/null +++ b/presets/coleco/siegegame.c @@ -0,0 +1,289 @@ + +#include +#include + +#include "cv.h" +#include "cvu.h" + +#define COLOR ((const cv_vmemp)0x2000) +#define IMAGE ((const cv_vmemp)0x1c00) + +#define COLS 32 +#define ROWS 24 + +typedef unsigned char byte; +typedef signed char sbyte; +typedef unsigned short word; + +uintptr_t __at(0x6a) font_bitmap_a; +uintptr_t __at(0x6c) font_bitmap_0; + +volatile bool vint; +volatile uint_fast8_t vint_counter; + +void vint_handler(void) +{ + vint = true; + vint_counter++; +} + +void setup_32_column_font() { + cv_set_image_table(IMAGE); + cvu_memtovmemcpy(0x1800, (void *)(font_bitmap_0 - '0'*8), 256*8); + cv_set_character_pattern_t(0x1800); + cv_set_screen_mode(CV_SCREENMODE_STANDARD); + cv_set_color_table(COLOR); + cvu_vmemset(COLOR, 0x36, 8); // set color for chars 0-63 + cvu_vmemset(COLOR+8, 0x06, 32-8); // set chars 63-255 +} + +char cursor_x; +char cursor_y; + +void clrscr() { + cvu_vmemset(IMAGE, ' ', COLS*ROWS); +} + +#define LOCHAR 0x0 +#define HICHAR 0xff + +#define CHAR(ch) (ch-LOCHAR) + +byte getchar(byte x, byte y) { + return cvu_vinb(IMAGE + y*COLS + x); +} + +void putchar(byte x, byte y, byte attr) { + cvu_voutb(attr, IMAGE + y*COLS + x); +} + +void putstring(byte x, byte y, const char* string) { + while (*string) { + putchar(x++, y, CHAR(*string++)); + } +} + +void wait_vsync() { + vint = false; + while (!vint) ; +} + +void delay(byte i) { + while (i--) { + wait_vsync(); + } +} + +////////// GAME DATA + +typedef struct { + byte x; + byte y; + byte dir; + word score; + char head_attr; + char tail_attr; + char collided:1; + char human:1; +} Player; + +Player players[2]; + +byte credits = 0; +byte frames_per_move; + +#define START_SPEED 12 +#define MAX_SPEED 5 +#define MAX_SCORE 7 + +/////////// + +const char BOX_CHARS[8] = { '+', '+', '+', '+', '-', '-', '!', '!' }; + +void draw_box(byte x, byte y, byte x2, byte y2, const char* chars) { + byte x1 = x; + putchar(x, y, chars[2]); + putchar(x2, y, chars[3]); + putchar(x, y2, chars[0]); + putchar(x2, y2, chars[1]); + while (++x < x2) { + putchar(x, y, chars[5]); + putchar(x, y2, chars[4]); + } + while (++y < y2) { + putchar(x1, y, chars[6]); + putchar(x2, y, chars[7]); + } +} + +void draw_playfield() { + draw_box(0,1,COLS-1,ROWS-1,BOX_CHARS); + putstring(0,0,"Plyr1:"); + putstring(20,0,"Plyr2:"); + putchar(7,0,CHAR(players[0].score+'0')); + putchar(27,0,CHAR(players[1].score+'0')); +} + +typedef enum { D_RIGHT, D_DOWN, D_LEFT, D_UP } dir_t; +const char DIR_X[4] = { 1, 0, -1, 0 }; +const char DIR_Y[4] = { 0, 1, 0, -1 }; + +void init_game() { + memset(players, 0, sizeof(players)); + players[0].head_attr = CHAR('1'); + players[1].head_attr = CHAR('2'); + players[0].tail_attr = 254; + players[1].tail_attr = 254; + frames_per_move = START_SPEED; +} + +void reset_players() { + players[0].x = players[0].y = 5; + players[0].dir = D_RIGHT; + players[1].x = 25; + players[1].y = 19; + players[1].dir = D_LEFT; + players[0].collided = players[1].collided = 0; +} + +void draw_player(Player* p) { + putchar(p->x, p->y, p->head_attr); +} + +void move_player(Player* p) { + putchar(p->x, p->y, p->tail_attr); + p->x += DIR_X[p->dir]; + p->y += DIR_Y[p->dir]; + if (getchar(p->x, p->y) != CHAR(' ')) + p->collided = 1; + draw_player(p); +} + +void human_control(Player* p) { + byte dir = 0xff; + struct cv_controller_state cs; + cv_get_controller_state(&cs, 0); // Read the controller. + if (!p->human) return; + if (cs.joystick & CV_LEFT) dir = D_LEFT; + if (cs.joystick & CV_RIGHT) dir = D_RIGHT; + if (cs.joystick & CV_UP) dir = D_UP; + if (cs.joystick & CV_DOWN) dir = D_DOWN; + // don't let the player reverse + if (dir < 0x80 && dir != (p->dir ^ 2)) { + p->dir = dir; + } +} + +byte ai_try_dir(Player* p, dir_t dir, byte shift) { + byte x,y; + dir &= 3; + x = p->x + (DIR_X[dir] << shift); + y = p->y + (DIR_Y[dir] << shift); + if (x < 29 && y < 27 && getchar(x, y) == CHAR(' ')) { + p->dir = dir; + return 1; + } else { + return 0; + } +} + +void ai_control(Player* p) { + dir_t dir; + if (p->human) return; + dir = p->dir; + if (!ai_try_dir(p, dir, 0)) { + ai_try_dir(p, dir+1, 0); + ai_try_dir(p, dir-1, 0); + } else { + ai_try_dir(p, dir-1, 0) && ai_try_dir(p, dir-1, 1+(rand() & 3)); + ai_try_dir(p, dir+1, 0) && ai_try_dir(p, dir+1, 1+(rand() & 3)); + ai_try_dir(p, dir, rand() & 3); + } +} + +byte gameover; + +void flash_colliders() { + byte i; + // flash players that collided + for (i=0; i<56; i++) { + //cv_set_frequency(CV_SOUNDCHANNEL_0, 1000+i*8); + //cv_set_attenuation(CV_SOUNDCHANNEL_0, i/2); + if (players[0].collided) players[0].head_attr ^= 0x80; + if (players[1].collided) players[1].head_attr ^= 0x80; + delay(2); + draw_player(&players[0]); + draw_player(&players[1]); + } + //cv_set_attenuation(CV_SOUNDCHANNEL_0, 28); +} + +void make_move() { + byte i; + for (i=0; i MAX_SPEED) frames_per_move--; + // game over? + if (players[0].score != players[1].score) { + if (players[0].score >= MAX_SCORE) + declare_winner(0); + else if (players[1].score >= MAX_SCORE) + declare_winner(1); + } +} + +void play_game() { + gameover = 0; + init_game(); + players[0].human = 1; + while (!gameover) { + play_round(); + } +} + +void main() { + setup_32_column_font(); + cv_set_screen_active(true); + cv_set_vint_handler(&vint_handler); + + draw_playfield(); + play_game(); +} diff --git a/presets/coleco/simplemusic.c b/presets/coleco/simplemusic.c new file mode 100644 index 00000000..17ac840b --- /dev/null +++ b/presets/coleco/simplemusic.c @@ -0,0 +1,23 @@ +#include + +const uint16_t notes[] = { 12846, 12334, 11086, 10062, 10062, 9806, 10062, 10574, 11086, 10062, 11086, 12430, 11042, 12334, 12878, 14158, 14158, 12878, 13390, 13646, 10574, 9806, 10574, 12430, 12846, 12334, 11086, 10062, 10062, 9806, 10062, 10574, 11086, 10062, 11086, 12430, 11054, 12334, 12878, 14158, 14158, 12878, 13390, 13646, 10574, 10062, 10062, 10126, 11054, 12334, 12878, 14158, 13902, 14158, 14670, 14158, 13646, 12878, 13390, 13646, 3918, 12878, 14158, 13902, 12878, 12366, 12878, 12366, 12878, 11086, 10062, 9870, 12334, 11054, 11086, 10062, 10062, 9806, 10062, 10574, 11086, 10062, 11086, 12430, 11054, 12334, 12878, 14158, 14158, 12878, 13390, 13646, 10574, 10062, 10062, 10126, 0xffff }; + +#include "cv.h" +#include "cvu_sound.h" + +struct cvu_music music; + +void play(void) +{ + cvu_play_music(&music); +} + +void main(void) +{ + cvu_init_music(&music); + music.notes = notes; + cv_set_vint_handler(&play); + cv_set_colors(CV_COLOR_BLACK, CV_COLOR_BLACK); + cv_set_screen_active(true); + for(;;); +} diff --git a/presets/coleco/stars.c b/presets/coleco/stars.c new file mode 100644 index 00000000..351d9932 --- /dev/null +++ b/presets/coleco/stars.c @@ -0,0 +1,81 @@ +#include +#include + +#include "cv.h" +#include "cvu.h" + +#define PATTERN ((const cv_vmemp)0x0000) +#define COLOR ((const cv_vmemp)0x2000) +#define IMAGE ((const cv_vmemp)0x1c00) + +volatile bool vint; +volatile uint_fast8_t vint_counter; +uint_fast8_t oldcounter; + +void vint_handler(void) +{ + vint = true; + vint_counter++; +} + +void update_stars(void) +{ + uint_fast8_t j; + uint_fast8_t tmp = vint_counter; + tmp %= (16 * 8); + + for(j = 0; j < 3; j++) + { + cvu_voutb(0x00, PATTERN + j * 256 * 8 + oldcounter); + cvu_voutb(0x10, PATTERN + j * 256 * 8 + tmp); + } + + oldcounter = tmp; +} + +void init_stars(void) +{ + uint_fast8_t i, j, r; + + for(j = 0; j < 32; j += rand() % 2) + { + r = rand() % 16; + for(i = 0; i < 24; i++) + { + cvu_voutb(r++, IMAGE + j + i * 32); + r %= 16; + } + } + + for(j = 0; j < 3; j++) + cvu_vmemset(COLOR + j * 256 * 8, (CV_COLOR_WHITE << 4) | CV_COLOR_BLACK, 16 * 8); + + cvu_voutb(0x10, PATTERN); + oldcounter = 0; + vint_counter = 0; +} + +void main(void) +{ + cv_set_screen_active(false); + cv_set_image_table(IMAGE); + cv_set_color_table(0x3fff); + cv_set_character_pattern_t(0x1fff); + cv_set_screen_mode(CV_SCREENMODE_BITMAP); + cv_set_vint_handler(&vint_handler); + + cvu_vmemset(PATTERN, 0, 8 * 256 * 3); + cvu_vmemset(COLOR, 0, 8 * 256 * 3); + cvu_vmemset(IMAGE, 0xff, 32 * 24); + + init_stars(); + + cv_set_screen_active(true); + + for(;;) + { + while(!vint); + update_stars(); + vint = false; + } +} diff --git a/presets/coleco/text.c b/presets/coleco/text.c new file mode 100644 index 00000000..8f285e07 --- /dev/null +++ b/presets/coleco/text.c @@ -0,0 +1,29 @@ + +#include +#include + +#include "cv.h" +#include "cvu.h" + +#define PATTERN ((const cv_vmemp)0x0000) +#define COLOR ((const cv_vmemp)0x2000) +#define IMAGE ((const cv_vmemp)0x1c00) + +uintptr_t __at(0x6a) font_bitmap_a; +uintptr_t __at(0x6c) font_bitmap_0; + +void setup_40_column_font() { + cv_set_image_table(IMAGE); + cvu_memtovmemcpy(0x1800, (void *)(font_bitmap_0 - 0x30*8), 2048); + cv_set_character_pattern_t(0x1800); + cv_set_screen_mode(CV_SCREENMODE_TEXT); +} + +void main(void) { + setup_40_column_font(); + cv_set_colors(CV_COLOR_LIGHT_GREEN, CV_COLOR_BLACK); + cvu_vmemset(IMAGE, '.', 960); + cvu_memtovmemcpy(IMAGE + 1, "Hello Professor Falken", 22); + cv_set_screen_active(true); + while (1); +} diff --git a/presets/coleco/text32.c b/presets/coleco/text32.c new file mode 100644 index 00000000..8a4102dc --- /dev/null +++ b/presets/coleco/text32.c @@ -0,0 +1,88 @@ + +#include +#include +#include + +#include "cv.h" +#include "cvu.h" + +#define COLOR ((const cv_vmemp)0x2000) +#define IMAGE ((const cv_vmemp)0x1c00) + +#define COLS 32 +#define ROWS 24 + +uintptr_t __at(0x6a) font_bitmap_a; +uintptr_t __at(0x6c) font_bitmap_0; + +void setup_32_column_font() { + cv_set_image_table(IMAGE); + cvu_memtovmemcpy(0x1800, (void *)(font_bitmap_0 - '0'*8), 2048); + cv_set_character_pattern_t(0x1800); + cv_set_screen_mode(CV_SCREENMODE_STANDARD); + cv_set_color_table(COLOR); + cvu_vmemset(COLOR, 0x36, 8); // set color for chars 0-63 + cvu_vmemset(COLOR+8, 0x06, 32-8); // set chars 63-255 +} + +char cursor_x; +char cursor_y; + +void clrscr() { + cvu_vmemset(IMAGE, ' ', COLS*ROWS); +} + +void setup_stdio() { + cursor_x = 0; + cursor_y = 0; + clrscr(); +} + +void scrollup() { + char buf[COLS]; + char y; + for (y=0; y= ROWS-1) { + scrollup(); + } else { + cursor_y++; + } +} + +int putchar(int ch) { + switch (ch) { + case '\n': + newline(); // TODO: scrolling + case '\r': + cursor_x = 0; + return 0; + } + cvu_voutb(ch, IMAGE + COLS*cursor_y + cursor_x); + cursor_x++; + if (cursor_x >= COLS) { + newline(); + cursor_x = 0; + } +} + +void main() { + unsigned char byteval = 123; + signed char charval = 123; + short shortval = 12345; + + setup_32_column_font(); + setup_stdio(); + cv_set_screen_active(true); + printf("HELLO WORLD!\n"); + while (1) { + printf("char %d byte %u sh %d\n", + charval++, byteval++, shortval++); + } +} diff --git a/presets/vicdual/hello.c b/presets/vicdual/hello.c index eab7ce11..a3304164 100644 --- a/presets/vicdual/hello.c +++ b/presets/vicdual/hello.c @@ -52,13 +52,13 @@ void newline() { } } -void putchar(char ch) { +int putchar(int ch) { switch (ch) { case '\n': newline(); // TODO: scrolling case '\r': cursor_x = 0; - return; + return 0; } cellram[cursor_x][31-cursor_y] = ch; cursor_x++; diff --git a/src/emu.js b/src/emu.js index 761d38a5..dfc853e9 100644 --- a/src/emu.js +++ b/src/emu.js @@ -873,6 +873,7 @@ var BaseMAMEPlatform = function() { var romdata; var video; var preload_files; + var running = false; this.luacall = function(s) { //console.log(s); @@ -884,11 +885,17 @@ var BaseMAMEPlatform = function() { } this.pause = function() { - if (loaded) this.luacall('emu.pause()'); + if (loaded && running) { + this.luacall('emu.pause()'); + running = false; + } } this.resume = function() { - if (loaded) this.luacall('emu.unpause()'); + if (loaded && !running) { + this.luacall('emu.unpause()'); + running = true; + } } this.reset = function() { @@ -896,7 +903,7 @@ var BaseMAMEPlatform = function() { } this.isRunning = function() { - // TODO + return running; } this.startModule = function(mainElement, opts) { diff --git a/src/platform/coleco.js b/src/platform/coleco.js index e4af9dc2..72a1d59c 100644 --- a/src/platform/coleco.js +++ b/src/platform/coleco.js @@ -5,11 +5,21 @@ // http://www.kernelcrash.com/blog/recreating-the-colecovision/2016/01/27/ // http://www.atarihq.com/danb/files/CV-Tech.txt // http://www.colecoboxart.com/faq/FAQ05.htm +// http://www.theadamresource.com/manuals/technical/Jeffcoleco.html +// http://bifi.msxnet.org/msxnet//tech/tms9918a.txt +// http://www.colecovision.dk/tools.htm?refreshed var ColecoVision_PRESETS = [ - {id:'minimal.c', name:'Minimal Example'}, + {id:'text.c', name:'Text Mode'}, + {id:'hello.c', name:'Scrolling Text'}, + {id:'text32.c', name:'32-Column Text'}, + {id:'stars.c', name:'Scrolling Starfield'}, + {id:'cursorsmooth.c', name:'Moving Cursor'}, + {id:'simplemusic.c', name:'Simple Music'}, + {id:'siegegame.c', name:'Siege Game'}, ]; +// doesn't work, use MAME var ColecoVisionPlatform = function(mainElement) { var self = this; this.__proto__ = new BaseZ80Platform(); diff --git a/src/ui.js b/src/ui.js index d1a49d3e..131916fe 100644 --- a/src/ui.js +++ b/src/ui.js @@ -398,6 +398,7 @@ function setCompileOutput(data) { addr2symbol = invertMap(symbolmap); addr2symbol[0x10000] = '__END__'; compparams = data.params; + updatePreset(current_preset_id, editor.getValue()); // update persisted entry // errors? function addErrorMarker(line, msg) { var div = document.createElement("div"); @@ -422,7 +423,6 @@ function setCompileOutput(data) { } current_output = null; } else { - updatePreset(current_preset_id, editor.getValue()); // update persisted entry // load ROM var rom = data.output; var rom_changed = rom && !arrayCompare(rom, current_output); @@ -1112,18 +1112,28 @@ function showBookLink() { } function addPageFocusHandlers() { + var hidden = false; document.addEventListener("visibilitychange", function() { - if (document.visibilityState == 'hidden') + if (document.visibilityState == 'hidden' && platform.isRunning()) { platform.pause(); - else if (document.visibilityState == 'visible') + hidden = true; + } else if (document.visibilityState == 'visible' && hidden) { platform.resume(); + hidden = false; + } + }); + $(window).on("focus", function() { + if (hidden) { + platform.resume(); + hidden = false; + } + }); + $(window).on("blur", function() { + if (platform.isRunning()) { + platform.pause(); + hidden = true; + } }); - window.onfocus = function() { - platform.resume(); - }; - window.onblur = function() { - platform.pause(); - }; } function startPlatform() { diff --git a/src/worker/fssdcc.data b/src/worker/fssdcc.data index c7e90394..640b9d91 100644 --- a/src/worker/fssdcc.data +++ b/src/worker/fssdcc.data @@ -65,6 +65,64 @@ #endif +/*------------------------------------------------------------------------- + uchar.h: Unicode utilities (ISO C 11 7.28) + + Copyright (C) 2015-2016, Philipp Klaus Krause, pkk@spth.de + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __SDCC_UCHAR_H +#define __SDCC_UCHAR_H 1 + +#ifndef __MBSTATE_T_DEFINED +#define __MBSTATE_T_DEFINED + typedef struct {unsigned char c[3];} mbstate_t; +#endif + +#ifndef __SIZE_T_DEFINED +#define __SIZE_T_DEFINED + typedef unsigned int size_t; +#endif + +#ifndef __CHAR16_T_DEFINED +#define __CHAR16_T_DEFINED + typedef unsigned int char16_t; +#endif + +#ifndef __CHAR32_T_DEFINED +#define __CHAR32_T_DEFINED + typedef unsigned long int char32_t; +#endif + +size_t mbrtoc16(char16_t *restrict pc16, const char *restrict s, size_t n, mbstate_t *restrict ps); +size_t c16rtomb(char *restrict s, char16_t c16, mbstate_t *restrict ps); +size_t mbrtoc32(char32_t *restrict pc32, const char *restrict s, size_t n, mbstate_t *restrict ps); +size_t c32rtomb(char *restrict s, char32_t c32, mbstate_t *restrict ps); + +#endif + /*------------------------------------------------------------------------- stddef.h - ANSI functions forward declarations @@ -121,7 +179,7 @@ #ifndef __WCHAR_T_DEFINED #define __WCHAR_T_DEFINED - typedef char wchar_t; + typedef unsigned long int wchar_t; #endif /* Bounds-checking interfaces from annex K of the C11 standard. */ @@ -144,9 +202,10 @@ typedef int errno_t; #endif /*------------------------------------------------------------------------- - stdlib.h - ANSI functions forward declarations + stdlib.h - General utilities (ISO C 11 7.22) - Copyright (C)1998, Sandeep Dutta . sandeep.dutta@usa.net + Copyright (C) 1998, Sandeep Dutta . sandeep.dutta@usa.net + Copyright (c) 2016, Philipp Klaus Krause, pkk@spth.de This library is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the @@ -158,7 +217,7 @@ typedef int errno_t; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - You should have received a copy of the GNU General Public License + You should have received a copy of the GNU General Public License along with this library; see the file COPYING. If not, write to the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. @@ -171,17 +230,26 @@ typedef int errno_t; might be covered by the GNU General Public License. -------------------------------------------------------------------------*/ -#ifndef __SDC51_STDLIB_H -#define __SDC51_STDLIB_H 1 +#ifndef __SDCC_STDLIB_H +#define __SDCC_STDLIB_H 1 -#ifndef NULL -# define NULL (void *)0 +#ifndef __SIZE_T_DEFINED +#define __SIZE_T_DEFINED + typedef unsigned int size_t; #endif -#include +#ifndef __WCHAR_T_DEFINED +#define __WCHAR_T_DEFINED + typedef unsigned long int wchar_t; +#endif -int abs(int j); -long int labs(long int j); +#ifndef NULL +#define NULL (void *)0 +#endif + +#define RAND_MAX 32767 + +#define MB_CUR_MAX 4 extern float atof (const char *nptr); extern int atoi (const char *nptr); @@ -196,11 +264,49 @@ extern void _itoa(int, char*, unsigned char); extern void _ultoa(unsigned long, char*, unsigned char); extern void _ltoa(long, char*, unsigned char); -#define RAND_MAX 32767 - int rand(void); void srand(unsigned int seed); +#if defined(__SDCC_mcs51) || defined(__SDCC_ds390) || defined(__SDCC_ds400) +void __xdata *calloc (size_t nmemb, size_t size); +void __xdata *malloc (size_t size); +void __xdata *realloc (void *ptr, size_t size); +#else +void *calloc (size_t nmemb, size_t size); +void *malloc (size_t size); +void *realloc (void *ptr, size_t size); +#endif + +#if __STDC_VERSION__ >= 201112L +inline void *aligned_alloc(size_t alignment, size_t size) +{ + (void)alignment; + return malloc(size); +} +#endif + +extern void free (void * ptr); + +#if defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r3ka) || defined(__SDCC_tlcs90) +int abs(int j) __preserves_regs(b, c, iyl, iyh); +#else +int abs(int j); +#endif +long int labs(long int j); + +/* C99 Multibyte/wide character conversion functions (ISO C 11 7.22.7) */ +#if __STDC_VERSION__ >= 199901L +int mblen(const char *s, size_t n); +int mbtowc(wchar_t *restrict pwc, const char *restrict s, size_t n); +int wctomb(char *s, wchar_t wc); +#endif + +/* C99 Multibyte/wide string conversion functions (ISO C 11 7.22.8) */ +#if __STDC_VERSION__ >= 199901L +size_t mbstowcs(wchar_t *restrict pwcs, const char *restrict s, size_t n); +size_t wcstombs(char *restrict s, const wchar_t *restrict pwcs, size_t n); +#endif + /* Bounds-checking interfaces from annex K of the C11 standard. */ #if defined (__STDC_WANT_LIB_EXT1__) && __STDC_WANT_LIB_EXT1__ @@ -219,6 +325,7 @@ typedef void (*constraint_handler_t)(const char *restrict msg, void *restrict pt #endif #endif + /*------------------------------------------------------------------------- time.h @@ -528,8 +635,16 @@ typedef int errno_t; /* Copying functions: */ extern void *memcpy (void * /*restrict */ dest, const void * /*restrict*/ src, size_t n); +#if defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r3ka) +extern void *memmove (void *dest, const void *src, size_t n) __preserves_regs(iyl, iyh); +#else extern void *memmove (void *dest, const void *src, size_t n); +#endif +#if defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r3ka) || defined(__SDCC_tlcs90) +extern char *strcpy (char * /*restrict*/ dest, const char * /*restrict*/ src) __preserves_regs(iyl, iyh); +#else extern char *strcpy (char * /*restrict*/ dest, const char * /*restrict*/ src); +#endif extern char *strncpy(char * /*restrict*/ dest, const char * /*restrict*/ src, size_t n); /* Concatenation functions: */ @@ -570,7 +685,11 @@ extern void *memset (void *s, int c, size_t n); #endif /* extern char *strerror(int errnum); */ +#if defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_tlcs90) +extern size_t strlen (const char *s) __preserves_regs(d, e, iyl, iyh); +#else extern size_t strlen (const char *s); +#endif #ifdef __SDCC_ds390 extern void __xdata * memcpyx(void __xdata *, void __xdata *, int) __naked; @@ -585,6 +704,7 @@ extern void __xdata * memcpyx(void __xdata *, void __xdata *, int) __naked; #endif #endif + /*------------------------------------------------------------------------- iso646.h @@ -669,6 +789,7 @@ extern int errno; #define EDOM 33 /* Math argument out of domain of functions */ #define ERANGE 34 /* Math result not representable */ +#define EILSEQ 84 /* Illegal byte sequence */ /* Bounds-checking interfaces from annex K of the C11 standard. */ #if defined (__STDC_WANT_LIB_EXT1__) && __STDC_WANT_LIB_EXT1__ @@ -736,6 +857,165 @@ typedef int errno_t; #define TYPEOF_EEPPOINTER 21 #endif +# +# +# + +VERSION = @VERSION@ +VERSIONHI = @VERSIONHI@ +VERSIONLO = @VERSIONLO@ +VERSIONP = @VERSIONP@ + +SHELL = /bin/sh +CPP = @CPP@ +INSTALL = @INSTALL@ +CP = @CP@ + +top_builddir = @top_builddir@ +top_srcdir = @top_srcdir@ + +prefix = @prefix@ +exec_prefix = @exec_prefix@ +bindir = @bindir@ +libdir = @libdir@ +datadir = @datadir@ +datarootdir = @datarootdir@ +includedir = @includedir@ +inclibdir = @inclibdir@ +mandir = @mandir@ +man1dir = $(mandir)/man1 +man2dir = $(mandir)/man2 +infodir = @infodir@ +VPATH = @srcdir@ +srcdir = @srcdir@ + +include_dir_suffix = @include_dir_suffix@ +inclib_dir_suffix = @inclib_dir_suffix@ + +sdcc_includedir = $(DESTDIR)$(datadir)/$(include_dir_suffix) +sdcc_inclibdir = $(DESTDIR)$(datadir)/$(inclib_dir_suffix) + +CPPFLAGS = @CPPFLAGS@ -I$(top_builddir) + + +# Compiling entire program or any subproject +# ------------------------------------------ +all: + +# Compiling and installing everything and running test +# ---------------------------------------------------- +install: all installdirs + $(CP) -r $(srcdir)/asm $(srcdir)/*.h $(sdcc_includedir) + for target in mcs51 ds390 pic14 pic16 z80 hc08 stm8; \ + do \ + if [ "`grep $${target} $(top_builddir)/ports.build`" = "$${target}" ]; \ + then \ + for mask in '*.h' '*.inc' '*.txt'; \ + do \ + if `ls $(srcdir)/$${target}/$${mask} > /dev/null 2>&1`; \ + then \ + $(CP) $(srcdir)/$${target}/$${mask} $(sdcc_includedir)/$${target}/; \ + fi; \ + done; \ + fi; \ + done; + # z80 family: z180, r2k, r3ka, gbz80, and tlcs90 + if [ "`grep z80 $(top_builddir)/ports.build`" = "z80" ]; \ + then \ + for target in z180 r2k gbz80 r3ka tlcs90; \ + do \ + for mask in '*.h' '*.inc' '*.txt'; \ + do \ + if `ls $(srcdir)/$${target}/$${mask} > /dev/null 2>&1`; \ + then \ + $(CP) $(srcdir)/$${target}/$${mask} $(sdcc_includedir)/$${target}/; \ + fi; \ + done; \ + done; \ + fi + # ds390 family: ds400 + if [ "`grep ds390 $(top_builddir)/ports.build`" = "ds390" ]; \ + then \ + for target in ds400; \ + do \ + for mask in '*.h' '*.inc' '*.txt'; \ + do \ + if `ls $(srcdir)/$${target}/$${mask} > /dev/null 2>&1`; \ + then \ + $(CP) $(srcdir)/$${target}/$${mask} $(sdcc_includedir)/$${target}/; \ + fi; \ + done; \ + done; \ + fi + # 6808 family: s08 + if [ "`grep hc08 $(top_builddir)/ports.build`" = "hc08" ]; \ + then \ + for target in s08; \ + do \ + for mask in '*.h' '*.inc' '*.txt'; \ + do \ + if `ls $(srcdir)/$${target}/$${mask} > /dev/null 2>&1`; \ + then \ + $(CP) $(srcdir)/$${target}/$${mask} $(sdcc_includedir)/$${target}/; \ + fi; \ + done; \ + done; \ + fi + find $(sdcc_includedir) -type d -name '.svn' -exec rm -rf {} \; + # correct file modes + find $(sdcc_includedir) -type f -exec chmod 644 {} \; + + +# Deleting all the installed files +# -------------------------------- +uninstall: + rm -rf $(sdcc_includedir) + rm -rf $(sdcc_inclibdir) + + +# Performing self-test +# -------------------- +check: + + +# Performing installation test +# ---------------------------- +installcheck: + + +# Creating installation directories +# --------------------------------- +installdirs: + mkdir -p $(sdcc_includedir) + for target in mcs51 ds390 ds400 pic14 pic16 z80 z180 gbz80 hc08; \ + do \ + if [ -d $(srcdir)/$${target} ]; \ + then \ + mkdir -p $(sdcc_includedir)/$${target}; \ + fi; \ + done + + +# Creating dependencies +# --------------------- +dep: + +include $(srcdir)/clean.mk + +# My rules +# -------- + + +# Remaking configuration +# ---------------------- +checkconf: + @if [ -f $(top_builddir)/devel ]; \ + then \ + $(MAKE) -f $(srcdir)/conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" \ + freshconf; \ + fi + +# End of main_in.mk/main.mk /*------------------------------------------------------------------------- stdio.h - ANSI functions forward declarations @@ -821,7 +1101,7 @@ extern char *gets(char *); #endif extern char getchar(void); -extern void putchar(char); +extern int putchar(int); #if defined(__SDCC_mcs51) && !defined(__SDCC_USE_XSTACK) extern void printf_fast(__code const char *fmt, ...) _REENTRANT; @@ -907,10 +1187,11 @@ void _assert(char *, const char *, unsigned int); #ifndef __SDC51_LIMITS_H #define __SDC51_LIMITS_H 1 -#define CHAR_BIT 8 /* bits in a char */ +#define CHAR_BIT 8 /* bits in a char */ #define SCHAR_MAX 127 #define SCHAR_MIN -128 #define UCHAR_MAX 0xff + #ifdef __SDCC_CHAR_UNSIGNED #define CHAR_MAX UCHAR_MAX #define CHAR_MIN 0 @@ -918,7 +1199,11 @@ void _assert(char *, const char *, unsigned int); #define CHAR_MAX SCHAR_MAX #define CHAR_MIN SCHAR_MIN #endif -#define MB_LEN_MAX 1 + +#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199409L +#define MB_LEN_MAX 4 +#endif + #define INT_MIN -32768 #define INT_MAX 32767 #define SHRT_MAX INT_MAX @@ -931,67 +1216,15 @@ void _assert(char *, const char *, unsigned int); #define LONG_MAX 2147483647L #define ULONG_MAX 0xffffffff #define ULONG_MIN 0 + +#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L #define LLONG_MIN (-9223372036854775807LL-1) #define LLONG_MAX 9223372036854775807LL #define ULLONG_MAX 18446744073709551615ULL - -#endif - - - - - - -/*------------------------------------------------------------------------- - malloc.h - malloc header file - - Copyright (C) 1997, Dmitry S. Obukhov - - This library is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published by the - Free Software Foundation; either version 2, or (at your option) any - later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this library; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, - MA 02110-1301, USA. - - As a special exception, if you link this library with other files, - some of which are compiled with SDCC, to produce an executable, - this library does not by itself cause the resulting executable to - be covered by the GNU General Public License. This exception does - not however invalidate any other reasons why the executable file - might be covered by the GNU General Public License. --------------------------------------------------------------------------*/ - -#ifndef __SDCC51_MALLOC_H -#define __SDCC51_MALLOC_H -#include -#include - -#if _SDCC_MALLOC_TYPE_MLH - -void * calloc (size_t nmemb, size_t size); -void * malloc (size_t size); -void * realloc (void * ptr, size_t size); -void free (void * ptr); - -#else - -extern void __xdata * calloc (size_t nmemb, size_t size); -extern void __xdata * malloc (size_t size); -extern void __xdata * realloc (void * ptr, size_t size); -extern void free (void * ptr); - #endif #endif + /*------------------------------------------------------------------------- float.h - ANSI functions forward declarations @@ -1037,6 +1270,7 @@ extern void free (void * ptr); #define FLT_MAX_10_EXP (+38) /* the following deal with IEEE single-precision numbers */ +#if defined(__SDCC_FLOAT_LIB) #define EXCESS 126 #define SIGNBIT ((unsigned long)0x80000000) #define __INFINITY ((unsigned long)0x7F800000) @@ -1046,6 +1280,7 @@ extern void free (void * ptr); #define MANT(fp) (((fp) & (unsigned long)0x007FFFFF) | HIDDEN) #define NORM 0xff000000 #define PACK(s,e,m) ((s) | ((unsigned long)(e) << 23) | (m)) +#endif float __uchar2fs (unsigned char); float __schar2fs (signed char); @@ -1109,7 +1344,7 @@ char __fsgt (float, float); MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - You should have received a copy of the GNU General Public License + You should have received a copy of the GNU General Public License along with this library; see the file COPYING. If not, write to the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. @@ -1147,18 +1382,20 @@ char __fsgt (float, float); #define RET_SIZE 2 #endif -#if defined (__SDCC_z80) || defined (__SDCC_z180) || defined (__SDCC_r2k) || defined (__SDCC_r3ka) -typedef unsigned char jmp_buf[6]; // 2 for the stack pointer, 2 for the return address, 2 for the frame pointer. -#elif defined (__SDCC_stm8) -typedef unsigned char jmp_buf[4]; // 2 for the stack pointer, 2 for the return address. +#if defined (__SDCC_z80) || defined (__SDCC_z180) || defined (__SDCC_r2k) || defined (__SDCC_r3ka) || defined (__SDCC_tlcs90) +typedef unsigned char jmp_buf[6]; /* 2 for the stack pointer, 2 for the return address, 2 for the frame pointer. */ +#elif defined (__SDCC_stm8) || defined (__SDCC_gbz80) || defined (__SDCC_hc08) || defined (__SDCC_s08) +typedef unsigned char jmp_buf[4]; /* 2 for the stack pointer, 2 for the return address. */ +#elif defined (__SDCC_ds390) +typedef unsigned char jmp_buf[5]; /* 2 for the stack pointer, 3 for the return address. */ #else typedef unsigned char jmp_buf[RET_SIZE + SP_SIZE + BP_SIZE + SPX_SIZE + BPX_SIZE]; #endif int __setjmp (jmp_buf); -// C99 might require setjmp to be a macro. The standard seems self-contradicting on this issue. -// However, it is clear that the standards allow setjmp to be a macro. +/* C99 might require setjmp to be a macro. The standard seems self-contradicting on this issue. */ +/* However, it is clear that the standards allow setjmp to be a macro. */ #define setjmp(jump_buf) __setjmp(jump_buf) #ifndef __SDCC_HIDE_LONGJMP @@ -1173,6 +1410,165 @@ _Noreturn void longjmp(jmp_buf, int); #endif +# +# +# + +VERSION = 3.6.5 +VERSIONHI = 3 +VERSIONLO = 6 +VERSIONP = 5 + +SHELL = /bin/sh +CPP = gcc -E +INSTALL = /usr/bin/install -c +CP = cp + +top_builddir = ../.. +top_srcdir = ../.. + +prefix = /usr/local +exec_prefix = ${prefix} +bindir = ${exec_prefix}/bin +libdir = ${exec_prefix}/lib +datadir = ${datarootdir} +datarootdir = ${prefix}/share +includedir = ${prefix}/include +inclibdir = @inclibdir@ +mandir = ${datarootdir}/man +man1dir = $(mandir)/man1 +man2dir = $(mandir)/man2 +infodir = ${datarootdir}/info + +srcdir = . + +include_dir_suffix = sdcc/include +inclib_dir_suffix = sdcc + +sdcc_includedir = $(DESTDIR)$(datadir)/$(include_dir_suffix) +sdcc_inclibdir = $(DESTDIR)$(datadir)/$(inclib_dir_suffix) + +CPPFLAGS = -I$(top_builddir) + + +# Compiling entire program or any subproject +# ------------------------------------------ +all: + +# Compiling and installing everything and running test +# ---------------------------------------------------- +install: all installdirs + $(CP) -r $(srcdir)/asm $(srcdir)/*.h $(sdcc_includedir) + for target in mcs51 ds390 pic14 pic16 z80 hc08 stm8; \ + do \ + if [ "`grep $${target} $(top_builddir)/ports.build`" = "$${target}" ]; \ + then \ + for mask in '*.h' '*.inc' '*.txt'; \ + do \ + if `ls $(srcdir)/$${target}/$${mask} > /dev/null 2>&1`; \ + then \ + $(CP) $(srcdir)/$${target}/$${mask} $(sdcc_includedir)/$${target}/; \ + fi; \ + done; \ + fi; \ + done; + # z80 family: z180, r2k, r3ka, gbz80, and tlcs90 + if [ "`grep z80 $(top_builddir)/ports.build`" = "z80" ]; \ + then \ + for target in z180 r2k gbz80 r3ka tlcs90; \ + do \ + for mask in '*.h' '*.inc' '*.txt'; \ + do \ + if `ls $(srcdir)/$${target}/$${mask} > /dev/null 2>&1`; \ + then \ + $(CP) $(srcdir)/$${target}/$${mask} $(sdcc_includedir)/$${target}/; \ + fi; \ + done; \ + done; \ + fi + # ds390 family: ds400 + if [ "`grep ds390 $(top_builddir)/ports.build`" = "ds390" ]; \ + then \ + for target in ds400; \ + do \ + for mask in '*.h' '*.inc' '*.txt'; \ + do \ + if `ls $(srcdir)/$${target}/$${mask} > /dev/null 2>&1`; \ + then \ + $(CP) $(srcdir)/$${target}/$${mask} $(sdcc_includedir)/$${target}/; \ + fi; \ + done; \ + done; \ + fi + # 6808 family: s08 + if [ "`grep hc08 $(top_builddir)/ports.build`" = "hc08" ]; \ + then \ + for target in s08; \ + do \ + for mask in '*.h' '*.inc' '*.txt'; \ + do \ + if `ls $(srcdir)/$${target}/$${mask} > /dev/null 2>&1`; \ + then \ + $(CP) $(srcdir)/$${target}/$${mask} $(sdcc_includedir)/$${target}/; \ + fi; \ + done; \ + done; \ + fi + find $(sdcc_includedir) -type d -name '.svn' -exec rm -rf {} \; + # correct file modes + find $(sdcc_includedir) -type f -exec chmod 644 {} \; + + +# Deleting all the installed files +# -------------------------------- +uninstall: + rm -rf $(sdcc_includedir) + rm -rf $(sdcc_inclibdir) + + +# Performing self-test +# -------------------- +check: + + +# Performing installation test +# ---------------------------- +installcheck: + + +# Creating installation directories +# --------------------------------- +installdirs: + mkdir -p $(sdcc_includedir) + for target in mcs51 ds390 ds400 pic14 pic16 z80 z180 gbz80 hc08; \ + do \ + if [ -d $(srcdir)/$${target} ]; \ + then \ + mkdir -p $(sdcc_includedir)/$${target}; \ + fi; \ + done + + +# Creating dependencies +# --------------------- +dep: + +include $(srcdir)/clean.mk + +# My rules +# -------- + + +# Remaking configuration +# ---------------------- +checkconf: + @if [ -f $(top_builddir)/devel ]; \ + then \ + $(MAKE) -f $(srcdir)/conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" \ + freshconf; \ + fi + +# End of main_in.mk/main.mk #ifndef __SDCC_STDALIGN_H #define __SDCC_STDALIGN_H 1 @@ -1323,20 +1719,83 @@ extern int isupper (int c); #define true 1 #define false 0 -#if defined (__SDCC_ds390) || defined (__SDCC_mcs51) || defined (__SDCC_xa51) - /* The ports that have __bit and use it as an imperfect substitute for bool */ - #define _Bool __bit - #define bool _Bool - #define __bool_true_false_are_defined 1 - #define __SDCC_WEIRD_BOOL 1 -#else - /* The ports that have bool */ - #define bool _Bool - #define __bool_true_false_are_defined 1 -#endif +#define bool _Bool +#define __bool_true_false_are_defined 1 #endif +/*------------------------------------------------------------------------- + wchar.h - Extended and multibyte wide character utilitites (ISO C 11 7.29) + + Copyright (c) 2015-2016, Philipp Klaus Krause / pkk@spth.de + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __WCHAR_T_DEFINED +#define __WCHAR_T_DEFINED + typedef unsigned long int wchar_t; +#endif + +#ifndef __SIZE_T_DEFINED +#define __SIZE_T_DEFINED + typedef unsigned int size_t; +#endif + +#ifndef __MBSTATE_T_DEFINED +#define __MBSTATE_T_DEFINED + typedef struct {unsigned char c[3];} mbstate_t; +#endif + +#ifndef __WINT_T_DEFINED +#define __WINT_T_DEFINED + typedef unsigned long int wint_t; +#endif + +struct tm; + +#ifndef WEOF + #define WEOF 0xfffffffful +#endif + +/* C99 Wide string comparison functions (ISO C11 7.29.4.4) */ +int wcscmp(const wchar_t *s1, const wchar_t *s2); + +/* C99 Miscellaneous functions (ISO C11 7.29.4.6) */ +size_t wcslen(const wchar_t *s); + +/* C99 Single-byte/wide character conversion functions (ISO C 11 7.29.6.1) */ +wint_t btowc(int c); +int wctob(wint_t c); + +/* C99 Conversion state functions (ISO C 11 7.29.6.2) */ +int mbsinit(const mbstate_t *ps); + +/* C99 Restartable multibyte/wide character conversion functions (ISO C 11 7.29.6.3) */ +size_t mbrlen(const char *restrict s, size_t n, mbstate_t *restrict ps); +size_t mbrtowc(wchar_t *restrict pwc, const char *restrict s, size_t n, mbstate_t *restrict ps); +size_t wcrtomb(char *restrict s, wchar_t wc, mbstate_t *restrict ps); + /*------------------------------------------------------------------------- ds80c390.h - Register Declarations for the DALLAS DS80C390 Processor far from complete, e.g. no CAN @@ -1636,7 +2095,41 @@ float ceilf(float x) _FLOAT_FUNC_REENTRANT; float floorf(float x) _FLOAT_FUNC_REENTRANT; float modff(float x, float * y); +int isnan(float f); +int isinf(float f); #endif /* _INC_MATH */ +# +# Makefile targets to remake configuration +# + +freshconf: Makefile + +Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.in + cd $(top_builddir) && $(SHELL) ./config.status + +# End of conf.mk +# Deleting all files created by building the program +# -------------------------------------------------- +clean: + rm -f *core *[%~] *.[oa] + rm -f .[a-z]*~ + + +# Deleting all files created by configuring or building the program +# ----------------------------------------------------------------- +distclean: clean + rm -f Makefile *.dep + + +# Like clean but some files may still exist +# ----------------------------------------- +mostlyclean: clean + + +# Deleting everything that can reconstructed by this Makefile. It deletes +# everything deleted by distclean plus files created by bison, etc. +# ----------------------------------------------------------------------- +realclean: distclean /*------------------------------------------------------------------------- stdint.h - ISO C99 7.18 Integer types @@ -1671,7 +2164,7 @@ float modff(float x, float * y); /* Exact integral types. */ -#if !defined(__SDCC_mcs51) && !defined(__SDCC_ds390) && !defined(__SDCC_ds400) && !defined(__SDCC_pic14) && !defined(__SDCC_pic16) +#if !defined(__SDCC_ds390) && !defined(__SDCC_ds400) && !defined(__SDCC_pic14) && !defined(__SDCC_pic16) #if __STDC_VERSION__ >= 199901L #define __SDCC_LONGLONG #endif @@ -1965,6 +2458,6059 @@ typedef unsigned char __data * va_list; #endif +/*------------------------------------------------------------------------- + sdcc-lib.h - SDCC Library Main Header + + Copyright (C) 2004, Vangelis Rokas + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __PIC16_SDCC_LIB_H +#define __PIC16_SDCC_LIB_H 1 + +#include <../asm/pic16/features.h> + +#endif +/*------------------------------------------------------------------------- + stddef.h - ANSI functions forward declarations + + Copyright (C) 2004, Maarten Brock + Ported to PIC16 port by Raphael Neider (2005) + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __PIC16_STDDEF_H +#define __PIC16_STDDEF_H 1 + +#ifndef NULL + #define NULL (void *)0 +#endif + +#ifndef _SIZE_T_DEFINED +#define _SIZE_T_DEFINED + typedef unsigned int size_t; +#endif + +#define offsetof(s, m) __builtin_offsetof (s, m) + +#endif /* __PIC16_STDDEF_H */ +/*------------------------------------------------------------------------- + stdlib.h - ANSI functions forward declarations + + Copyright (C) 1998, Sandeep Dutta . sandeep.dutta@usa.net + Ported to PIC16 port by Vangelis Rokas, 2004 + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __STDLIB_H__ +#define __STDLIB_H__ 1 + +#pragma library c + +#include + +#ifndef NULL +# define NULL (void *)0 +#endif + +#define RAND_MAX 0x7fffffff + +/* absolute value */ +int abs (int j); +long int labs (long int j); + +/* initialize random seed */ +void srand (unsigned long seed); + +/* return a random number between 0 and RAND_MAX */ +long rand (void); + +/* reentrant version of rand() */ +long rand_r (unsigned long *ctx); + +/* returns the CRC16 checksum of the data buffer, takes as + * last argument an old value of crc16 checksum */ +uint16_t crc16 (uint8_t *, uint32_t, uint16_t); + +/* convert a ASCII string to float */ +float atof (char *); + +/* convert a ASCII string to integer */ +int atoi (char *); + +/* convert a ASCII string to long */ +long atol (char *); + +/* convert an unsigned/signed integer to ASCII string */ +void uitoa (unsigned int, __data char *, unsigned char); +void itoa (int, __data char*, unsigned char); + +/* convert an unsigned/signed long integer to ASCII string */ +void ultoa (unsigned long, __data char *, unsigned char); +void ltoa (long, __data char*, unsigned char); + +/* helper functions: convert a float to ASCII string */ +extern char x_ftoa (float, __data char *, unsigned char, unsigned char); + +/* George M. Gallant's version of ftoa() */ +extern void g_ftoa (__data char *, float, char); + + +#endif /* __STDLIB_H__ */ +/*------------------------------------------------------------------------- + string.h - ANSI functions forward declarations + + Copyright (C) 1998, Sandeep Dutta . sandeep.dutta@usa.net + Ported to PIC16 port by Vangelis Rokas, 2004 + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __STRING_H /* { */ +#define __STRING_H 1 + +#define _STRING_SPEC __data + +#pragma library c + +#ifndef NULL +# define NULL (void *)0 +#endif + +#ifndef _SIZE_T_DEFINED +# define _SIZE_T_DEFINED + typedef unsigned int size_t; +#endif + +char *strcat (char *, char *); +char *strchr (char *, char); +int strcmp (char *, char *); +char *strcpy (char *, char *); +int strcspn(char *, char *); +int strlen (char *); +char *strlwr (char *); +char *strncat(char *, char *, size_t ); +int strncmp(char *, char *, size_t ); +char *strncpy(char *, char *, size_t ); +char *strpbrk(char *, char *); +char *strrchr(char *, char); +int strspn (char *, char *); +char *strstr (char *, char *); +char *strtok (char *, char *); +char *strupr (char *); + +void *memccpy(void *, void *, char, size_t); +void *memchr(const void *, char, size_t); +int memcmp (const void *, const void *, size_t); +void *memcpy (void *, const void *, size_t); +void *memmove (void *, const void *, size_t); +void *memrchr(void *, char, size_t); +void *memset (_STRING_SPEC void *, unsigned char, size_t ); + +__code void *memchrpgm(__code void *, char, size_t); +__data void *memchrram(__data void *, char, size_t); +__data void *memcpypgm2ram(__data void *, __code void *, size_t); +__data void *memcpyram2ram(__data void *, __data void *, size_t); + + +#endif /* } */ +/*------------------------------------------------------------------------- + gstack.h - debug stack tracing header + + Copyright (C) 2004, Vangelis Rokas + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __PIC16_GSTACK_H__ +#define __PIC16_GSTACK_H__ + +/* link the debug library */ +#pragma library debug + +extern void (* _gstack_overflow_handler)(void); + +#endif /* __PIC16_GSTACK_H__ */ +/*------------------------------------------------------------------------- + errno.h - Error codes used in the math functions + + Copyright (C) 2001, Jesus Calvino-Fraga jesusc@ieee.org + Ported to PIC16 port by Vangelis Rokas, 2004 + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef _PIC16_ERRNO_H +#define _PIC16_ERRNO_H + +/* link with C library */ +#pragma library c + +extern int errno; + +/* Error Codes: */ + +#define EDOM 33 /* Math argument out of domain of functions */ +#define ERANGE 34 /* Math result not representable */ + +#endif /* _PIC16_ERRNO_H */ +;-------------------------------------------------------------------------- +; p18fxxx.inc +; +; Copyright (C) 2005, Vangelis Rokas +; +; This library is free software; you can redistribute it and/or modify it +; under the terms of the GNU General Public License as published by the +; Free Software Foundation; either version 2, or (at your option) any +; later version. +; +; This library is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this library; see the file COPYING. If not, write to the +; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, +; MA 02110-1301, USA. +; +; As a special exception, if you link this library with other files, +; some of which are compiled with SDCC, to produce an executable, +; this library does not by itself cause the resulting executable to +; be covered by the GNU General Public License. This exception does +; not however invalidate any other reasons why the executable file +; might be covered by the GNU General Public License. +;-------------------------------------------------------------------------- + +#ifndef __P18FXXX__ +#define __P18FXXX__ 1 + + + list r=dec, n=96, st=off, mm=off + + nolist + +; This header file defines configurations, registers, and other useful bits of +; information common to all PIC18Fxxx microcontrollers. + +FSR0 equ 0 +FSR1 equ 1 +FSR2 equ 2 + +FAST equ 1 + +W equ 0 +A equ 0 +ACCESS equ 0 +BANKED equ 1 + +; Register Files + +TOSU equ 0x0FFF +TOSH equ 0x0FFE +TOSL equ 0x0FFD + +STKPTR equ 0x0FFC + +PCLATU equ 0x0FFB +PCLATH equ 0x0FFA +PCL equ 0x0FF9 + +TBLPTRU equ 0x0FF8 +TBLPTRH equ 0x0FF7 +TBLPTRL equ 0x0FF6 +TABLAT equ 0x0FF5 + +PRODH equ 0x0FF4 +PRODL equ 0x0FF3 + +INDF0 equ 0x0FEF +POSTINC0 equ 0x0FEE +POSTDEC0 equ 0x0FED +PREINC0 equ 0x0FEC +PLUSW0 equ 0x0FEB +FSR0H equ 0x0FEA +FSR0L equ 0x0FE9 + +WREG equ 0x0FE8 + +INDF1 equ 0x0FE7 +POSTINC1 equ 0x0FE6 +POSTDEC1 equ 0x0FE5 +PREINC1 equ 0x0FE4 +PLUSW1 equ 0x0FE3 +FSR1H equ 0x0FE2 +FSR1L equ 0x0FE1 + +BSR equ 0x0FE0 + +INDF2 equ 0x0FDF +POSTINC2 equ 0x0FDE +POSTDEC2 equ 0x0FDD +PREINC2 equ 0x0FDC +PLUSW2 equ 0x0FDB +FSR2H equ 0x0FDA +FSR2L equ 0x0FD9 + +STATUS equ 0x0FD8 + +PORTC equ 0x0F82 +PORTB equ 0x0F81 +PORTA equ 0x0F80 + +; Status Register Bit Definitions + +C equ 0 +DC equ 1 +Z equ 2 +OV equ 3 +N equ 4 + + list +#endif +/*------------------------------------------------------------------------- + signal.h - Signal handler header + + Copyright (C) 2005, Vangelis Rokas + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __SIGNAL_H__ +#define __SIGNAL_H__ + +/* interrupt testing arguments */ +#define SIG_RB SIG_RBIF +#define SIG_INT0 SIG_INT0IF +#define SIG_INT1 SIG_INT1IF +#define SIG_INT2 SIG_INT2IF +#define SIG_CCP1 SIG_CCP1IF +#define SIG_CCP2 SIG_CCP2IF +#define SIG_TMR0 SIG_TMR0IF +#define SIG_TMR1 SIG_TMR1IF +#define SIG_TMR2 SIG_TMR2IF +#define SIG_TMR3 SIG_TMR3IF +#define SIG_EE SIG_EEIF +#define SIG_BCOL SIG_BCOLIF +#define SIG_LVD SIG_LVDIF +#define SIG_PSP SIG_PSPIF +#define SIG_AD SIG_ADIF +#define SIG_RC SIG_RCIF +#define SIG_TX SIG_TXIF +#define SIG_SSP SIG_SSPIF +#define SIG_MSSP SIG_SSPIF /* just an alias */ +#define SIG_USB SIG_USBIF + +/* define name to be the interrupt handler for interrupt #vecno */ +#define DEF_ABSVECTOR(vecno, name) \ +void __ivt_ ## name(void) __interrupt(vecno) __naked \ +{ \ + __asm goto _ ## name __endasm; \ +} + +/* Define name to be the handler for high priority interrupts, + * use like this: + * DEF_INTHIGH(high_handler) + * DEF_HANDLER(SIG_TMR0, timer0_handler) + * DEF_HANDLER2(SIG_TMR1, SIG_TMR1IE, timer1_handler) + * ... + * END_DEF + * + * SIGHANDLER(timer0_handler) + * { + * // code to handle timer0 interrupts + * } + * SIGHANDLER(timer1_handler) + * { + * // code to handle timer1 interrupts + * } + */ +#define DEF_INTHIGH(name) \ +DEF_ABSVECTOR(1, name) \ +void name(void) __naked __interrupt \ +{ + +/* Define name to be the handler for high priority interrupts, + * use like this: + * DEF_INTLOW(low_handler) + * DEF_HANDLER(SIG_RB, portb_handler) + * DEF_HANDLER2(SIG_LVD, SIG_LVDIE, lowvolt_handler) + * ... + * END_DEF + * + * SIGHANDLER(portb_handler) + * { + * // code to handle PORTB change interrupts + * } + * SIGHANDLER(lowvolt_handler) + * { + * // code to handle low voltage interrupts + * } + */ +#define DEF_INTLOW(name) \ +DEF_ABSVECTOR(2, name) \ +void name(void) __naked __interrupt \ +{ + +/* finish an interrupt handler definition */ +#define END_DEF \ + __asm retfie __endasm; \ +} + +/* Declare handler to be the handler function for the given signal. + * sig should be one of SIG_xxx from above, handler should be a + * function defined using SIGHANDLER(handler) or + * SIGHANDLERNAKED(handler). + * ATTENTION: This macro ignores the signal's enable bit! + * Use DEF_HANDLER2(SIG_xxx, SIGxxxIE, handler) instead! + * To be used together with DEF_INTHIGH and DEF_INTLOW. + */ +#define DEF_HANDLER(sig, handler) \ + __asm btfsc sig, 0 __endasm; \ + __asm goto _ ## handler __endasm; + +/* Declare handler to be the handler function for the given signal. + * sig should be one of SIG_xxx from above, + * sig2 should also be a signal (probably SIG_xxxIE from below) and + * handler should be a function defined using SIGHANDLER(handler) + * or SIGHANDLERNAKED(handler). + * To be used together with DEF_INTHIGH and DEF_INTLOW. + */ +#define DEF_HANDLER2(sig1,sig2,handler) \ + __asm btfss sig1, 0 __endasm; \ + __asm bra $+8 __endasm; \ + __asm btfsc sig2, 0 __endasm; \ + __asm goto _ ## handler __endasm; + +/* Declare or define an interrupt handler function. */ +#define SIGHANDLER(handler) void handler (void) __interrupt +#define SIGHANDLERNAKED(handler) void handler (void) __naked __interrupt + + +/* + * inline assembly compatible bit definitions + */ +#define SIG_RBIF _INTCON, 0 +#define SIG_RBIE _INTCON, 3 +#define SIG_RBIP _INTCON2, 0 + +#define SIG_INT0IF _INTCON, 1 +#define SIG_INT0IE _INTCON, 4 +/*#define SIG_INT0IP not selectable, always ? */ + +#define SIG_TMR0IF _INTCON, 2 +#define SIG_TMR0IE _INTCON, 5 +#define SIG_TMR0IP _INTCON2, 2 + +#define SIG_INT1IF _INTCON3, 0 +#define SIG_INT1IE _INTCON3, 3 +#define SIG_INT1IP _INTCON3, 6 + +#define SIG_INT2IF _INTCON3, 1 +#define SIG_INT2IE _INTCON3, 4 +#define SIG_INT2IP _INTCON3, 7 + +/* device dependent -- should be moved to pic18f*.h */ +#define SIG_TMR1IDX 0 +#define SIG_TMR1SUF 1 +#define SIG_TMR2IDX 1 +#define SIG_TMR2SUF 1 +#define SIG_CCP1IDX 2 +#define SIG_CCP1SUF 1 +#define SIG_SSPIDX 3 +#define SIG_SSPSUF 1 +#define SIG_TXIDX 4 +#define SIG_TXSUF 1 +#define SIG_RCIDX 5 +#define SIG_RCSUF 1 +#define SIG_ADIDX 6 +#define SIG_ADSUF 1 +#define SIG_PSPIDX 7 +#define SIG_PSPSUF 1 + +#define SIG_CCP2IDX 0 +#define SIG_CCP2SUF 2 +#define SIG_TMR3IDX 1 +#define SIG_TMR3SUF 2 +#define SIG_LVDIDX 2 +#define SIG_LVDSUF 2 +#define SIG_BCOLIDX 3 +#define SIG_BCOLSUF 2 +#define SIG_EEIDX 4 +#define SIG_EESUF 2 +#define SIG_USBIDX 5 +#define SIG_USBSUF 2 + +/* device independent */ +#define __concat(a,b) __concat2(a,b) +#define __concat2(a,b) a ## b + +#define SIG_PIR(suf) __concat(_PIR,suf) +#define SIG_PIE(suf) __concat(_PIE,suf) +#define SIG_IPR(suf) __concat(_IPR,suf) + +#define SIG_TMR1IF SIG_PIR(SIG_TMR1SUF), SIG_TMR1IDX +#define SIG_TMR1IE SIG_PIE(SIG_TMR1SUF), SIG_TMR1IDX +#define SIG_TMR1IP SIG_IPR(SIG_TMR1SUF), SIG_TMR1IDX + +#define SIG_TMR2IF SIG_PIR(SIG_TMR2SUF), SIG_TMR2IDX +#define SIG_TMR2IE SIG_PIE(SIG_TMR2SUF), SIG_TMR2IDX +#define SIG_TMR2IP SIG_IPR(SIG_TMR2SUF), SIG_TMR2IDX + +#define SIG_CCP1IF SIG_PIR(SIG_CCP1SUF), SIG_CCP1IDX +#define SIG_CCP1IE SIG_PIE(SIG_CCP1SUF), SIG_CCP1IDX +#define SIG_CCP1IP SIG_IPR(SIG_CCP1SUF), SIG_CCP1IDX + +#define SIG_SSPIF SIG_PIR(SIG_SSPSUF), SIG_SSPIDX +#define SIG_SSPIE SIG_PIE(SIG_SSPSUF), SIG_SSPIDX +#define SIG_SSPIP SIG_IPR(SIG_SSPSUF), SIG_SSPIDX +/* aliases: MSSP */ +#define SIG_MSSPIF SIG_SSPIF //SIG_PIR(SIG_SSPSUF), SIG_SSPIDX +#define SIG_MSSPIE SIG_SSPIE //SIG_PIE(SIG_SSPSUF), SIG_SSPIDX +#define SIG_MSSPIP SIG_SSPIP //SIG_IPR(SIG_SSPSUF), SIG_SSPIDX + +#define SIG_TXIF SIG_PIR(SIG_TXSUF), SIG_TXIDX +#define SIG_TXIE SIG_PIE(SIG_TXSUF), SIG_TXIDX +#define SIG_TXIP SIG_IPR(SIG_TXSUF), SIG_TXIDX + +#define SIG_RCIF SIG_PIR(SIG_RCSUF), SIG_RCIDX +#define SIG_RCIE SIG_PIE(SIG_RCSUF), SIG_RCIDX +#define SIG_RCIP SIG_IPR(SIG_RCSUF), SIG_RCIDX + +#define SIG_ADIF SIG_PIR(SIG_ADSUF), SIG_ADIDX +#define SIG_ADIE SIG_PIE(SIG_ADSUF), SIG_ADIDX +#define SIG_ADIP SIG_IPR(SIG_ADSUF), SIG_ADIDX + +#define SIG_PSPIF SIG_PIR(SIG_PSPSUF), SIG_PSPIDX +#define SIG_PSPIE SIG_PIE(SIG_PSPSUF), SIG_PSPIDX +#define SIG_PSPIP SIG_IPR(SIG_PSPSUF), SIG_PSPIDX + +#define SIG_CCP2IF SIG_PIR(SIG_CCP2SUF), SIG_CCP2IDX +#define SIG_CCP2IE SIG_PIE(SIG_CCP2SUF), SIG_CCP2IDX +#define SIG_CCP2IP SIG_IPR(SIG_CCP2SUF), SIG_CCP2IDX + +#define SIG_TMR3IF SIG_PIR(SIG_TMR3SUF), SIG_TMR3IDX +#define SIG_TMR3IE SIG_PIE(SIG_TMR3SUF), SIG_TMR3IDX +#define SIG_TMR3IP SIG_IPR(SIG_TMR3SUF), SIG_TMR3IDX + +#define SIG_LVDIF SIG_PIR(SIG_LVDSUF), SIG_LVDIDX +#define SIG_LVDIE SIG_PIE(SIG_LVDSUF), SIG_LVDIDX +#define SIG_LVDIP SIG_IPR(SIG_LVDSUF), SIG_LVDIDX + +#define SIG_BCOLIF SIG_PIR(SIG_BCOLSUF), SIG_BCOLIDX +#define SIG_BCOLIE SIG_PIE(SIG_BCOLSUF), SIG_BCOLIDX +#define SIG_BCOLIP SIG_IPR(SIG_BCOLSUF), SIG_BCOLIDX + +#define SIG_EEIF SIG_PIR(SIG_EESUF), SIG_EEIDX +#define SIG_EEIE SIG_PIE(SIG_EESUF), SIG_EEIDX +#define SIG_EEIP SIG_IPR(SIG_EESUF), SIG_EEIDX + +#define SIG_USBIF SIG_PIR(SIG_USBSUF), SIG_USBIDX +#define SIG_USBIE SIG_PIE(SIG_USBSUF), SIG_USBIDX +#define SIG_USBIP SIG_IPR(SIG_USBSUF), SIG_USBIDX + +#endif /* __SIGNAL_H__ */ +/* + * + * This file is generated automatically by the device-manager.pl program. + * + * Copyright (C) 2012-2015, Molnar Karoly + * + */ + +#ifndef __PIC18FREGS_H__ +#define __PIC18FREGS_H__ + +#if defined(__SDCC_PIC18F13K22) + #include + +#elif defined(__SDCC_PIC18F13K50) + #include + +#elif defined(__SDCC_PIC18F14K22) + #include + +#elif defined(__SDCC_PIC18F14K50) + #include + +#elif defined(__SDCC_PIC18F23K20) + #include + +#elif defined(__SDCC_PIC18F23K22) + #include + +#elif defined(__SDCC_PIC18F24J10) + #include + +#elif defined(__SDCC_PIC18F24J11) + #include + +#elif defined(__SDCC_PIC18F24J50) + #include + +#elif defined(__SDCC_PIC18F24K20) + #include + +#elif defined(__SDCC_PIC18F24K22) + #include + +#elif defined(__SDCC_PIC18F24K50) + #include + +#elif defined(__SDCC_PIC18F25J10) + #include + +#elif defined(__SDCC_PIC18F25J11) + #include + +#elif defined(__SDCC_PIC18F25J50) + #include + +#elif defined(__SDCC_PIC18F25K20) + #include + +#elif defined(__SDCC_PIC18F25K22) + #include + +#elif defined(__SDCC_PIC18F25K50) + #include + +#elif defined(__SDCC_PIC18F25K80) + #include + +#elif defined(__SDCC_PIC18F26J11) + #include + +#elif defined(__SDCC_PIC18F26J13) + #include + +#elif defined(__SDCC_PIC18F26J50) + #include + +#elif defined(__SDCC_PIC18F26J53) + #include + +#elif defined(__SDCC_PIC18F26K20) + #include + +#elif defined(__SDCC_PIC18F26K22) + #include + +#elif defined(__SDCC_PIC18F26K80) + #include + +#elif defined(__SDCC_PIC18F27J13) + #include + +#elif defined(__SDCC_PIC18F27J53) + #include + +#elif defined(__SDCC_PIC18F43K20) + #include + +#elif defined(__SDCC_PIC18F43K22) + #include + +#elif defined(__SDCC_PIC18F44J10) + #include + +#elif defined(__SDCC_PIC18F44J11) + #include + +#elif defined(__SDCC_PIC18F44J50) + #include + +#elif defined(__SDCC_PIC18F44K20) + #include + +#elif defined(__SDCC_PIC18F44K22) + #include + +#elif defined(__SDCC_PIC18F45J10) + #include + +#elif defined(__SDCC_PIC18F45J11) + #include + +#elif defined(__SDCC_PIC18F45J50) + #include + +#elif defined(__SDCC_PIC18F45K20) + #include + +#elif defined(__SDCC_PIC18F45K22) + #include + +#elif defined(__SDCC_PIC18F45K50) + #include + +#elif defined(__SDCC_PIC18F45K80) + #include + +#elif defined(__SDCC_PIC18F46J11) + #include + +#elif defined(__SDCC_PIC18F46J13) + #include + +#elif defined(__SDCC_PIC18F46J50) + #include + +#elif defined(__SDCC_PIC18F46J53) + #include + +#elif defined(__SDCC_PIC18F46K20) + #include + +#elif defined(__SDCC_PIC18F46K22) + #include + +#elif defined(__SDCC_PIC18F46K80) + #include + +#elif defined(__SDCC_PIC18F47J13) + #include + +#elif defined(__SDCC_PIC18F47J53) + #include + +#elif defined(__SDCC_PIC18F63J11) + #include + +#elif defined(__SDCC_PIC18F63J90) + #include + +#elif defined(__SDCC_PIC18F64J11) + #include + +#elif defined(__SDCC_PIC18F64J90) + #include + +#elif defined(__SDCC_PIC18F65J10) + #include + +#elif defined(__SDCC_PIC18F65J11) + #include + +#elif defined(__SDCC_PIC18F65J15) + #include + +#elif defined(__SDCC_PIC18F65J50) + #include + +#elif defined(__SDCC_PIC18F65J90) + #include + +#elif defined(__SDCC_PIC18F65J94) + #include + +#elif defined(__SDCC_PIC18F65K22) + #include + +#elif defined(__SDCC_PIC18F65K80) + #include + +#elif defined(__SDCC_PIC18F65K90) + #include + +#elif defined(__SDCC_PIC18F66J10) + #include + +#elif defined(__SDCC_PIC18F66J11) + #include + +#elif defined(__SDCC_PIC18F66J15) + #include + +#elif defined(__SDCC_PIC18F66J16) + #include + +#elif defined(__SDCC_PIC18F66J50) + #include + +#elif defined(__SDCC_PIC18F66J55) + #include + +#elif defined(__SDCC_PIC18F66J60) + #include + +#elif defined(__SDCC_PIC18F66J65) + #include + +#elif defined(__SDCC_PIC18F66J90) + #include + +#elif defined(__SDCC_PIC18F66J93) + #include + +#elif defined(__SDCC_PIC18F66J94) + #include + +#elif defined(__SDCC_PIC18F66J99) + #include + +#elif defined(__SDCC_PIC18F66K22) + #include + +#elif defined(__SDCC_PIC18F66K80) + #include + +#elif defined(__SDCC_PIC18F66K90) + #include + +#elif defined(__SDCC_PIC18F67J10) + #include + +#elif defined(__SDCC_PIC18F67J11) + #include + +#elif defined(__SDCC_PIC18F67J50) + #include + +#elif defined(__SDCC_PIC18F67J60) + #include + +#elif defined(__SDCC_PIC18F67J90) + #include + +#elif defined(__SDCC_PIC18F67J93) + #include + +#elif defined(__SDCC_PIC18F67J94) + #include + +#elif defined(__SDCC_PIC18F67K22) + #include + +#elif defined(__SDCC_PIC18F67K90) + #include + +#elif defined(__SDCC_PIC18F83J11) + #include + +#elif defined(__SDCC_PIC18F83J90) + #include + +#elif defined(__SDCC_PIC18F84J11) + #include + +#elif defined(__SDCC_PIC18F84J90) + #include + +#elif defined(__SDCC_PIC18F85J10) + #include + +#elif defined(__SDCC_PIC18F85J11) + #include + +#elif defined(__SDCC_PIC18F85J15) + #include + +#elif defined(__SDCC_PIC18F85J50) + #include + +#elif defined(__SDCC_PIC18F85J90) + #include + +#elif defined(__SDCC_PIC18F85J94) + #include + +#elif defined(__SDCC_PIC18F85K22) + #include + +#elif defined(__SDCC_PIC18F85K90) + #include + +#elif defined(__SDCC_PIC18F86J10) + #include + +#elif defined(__SDCC_PIC18F86J11) + #include + +#elif defined(__SDCC_PIC18F86J15) + #include + +#elif defined(__SDCC_PIC18F86J16) + #include + +#elif defined(__SDCC_PIC18F86J50) + #include + +#elif defined(__SDCC_PIC18F86J55) + #include + +#elif defined(__SDCC_PIC18F86J60) + #include + +#elif defined(__SDCC_PIC18F86J65) + #include + +#elif defined(__SDCC_PIC18F86J72) + #include + +#elif defined(__SDCC_PIC18F86J90) + #include + +#elif defined(__SDCC_PIC18F86J93) + #include + +#elif defined(__SDCC_PIC18F86J94) + #include + +#elif defined(__SDCC_PIC18F86J99) + #include + +#elif defined(__SDCC_PIC18F86K22) + #include + +#elif defined(__SDCC_PIC18F86K90) + #include + +#elif defined(__SDCC_PIC18F87J10) + #include + +#elif defined(__SDCC_PIC18F87J11) + #include + +#elif defined(__SDCC_PIC18F87J50) + #include + +#elif defined(__SDCC_PIC18F87J60) + #include + +#elif defined(__SDCC_PIC18F87J72) + #include + +#elif defined(__SDCC_PIC18F87J90) + #include + +#elif defined(__SDCC_PIC18F87J93) + #include + +#elif defined(__SDCC_PIC18F87J94) + #include + +#elif defined(__SDCC_PIC18F87K22) + #include + +#elif defined(__SDCC_PIC18F87K90) + #include + +#elif defined(__SDCC_PIC18F95J94) + #include + +#elif defined(__SDCC_PIC18F96J60) + #include + +#elif defined(__SDCC_PIC18F96J65) + #include + +#elif defined(__SDCC_PIC18F96J94) + #include + +#elif defined(__SDCC_PIC18F96J99) + #include + +#elif defined(__SDCC_PIC18F97J60) + #include + +#elif defined(__SDCC_PIC18F97J94) + #include + +#elif defined(__SDCC_PIC18F242) + #include + +#elif defined(__SDCC_PIC18F248) + #include + +#elif defined(__SDCC_PIC18F252) + #include + +#elif defined(__SDCC_PIC18F258) + #include + +#elif defined(__SDCC_PIC18F442) + #include + +#elif defined(__SDCC_PIC18F448) + #include + +#elif defined(__SDCC_PIC18F452) + #include + +#elif defined(__SDCC_PIC18F458) + #include + +#elif defined(__SDCC_PIC18F1220) + #include + +#elif defined(__SDCC_PIC18F1230) + #include + +#elif defined(__SDCC_PIC18F1320) + #include + +#elif defined(__SDCC_PIC18F1330) + #include + +#elif defined(__SDCC_PIC18F2220) + #include + +#elif defined(__SDCC_PIC18F2221) + #include + +#elif defined(__SDCC_PIC18F2320) + #include + +#elif defined(__SDCC_PIC18F2321) + #include + +#elif defined(__SDCC_PIC18F2331) + #include + +#elif defined(__SDCC_PIC18F2410) + #include + +#elif defined(__SDCC_PIC18F2420) + #include + +#elif defined(__SDCC_PIC18F2423) + #include + +#elif defined(__SDCC_PIC18F2431) + #include + +#elif defined(__SDCC_PIC18F2439) + #include + +#elif defined(__SDCC_PIC18F2450) + #include + +#elif defined(__SDCC_PIC18F2455) + #include + +#elif defined(__SDCC_PIC18F2458) + #include + +#elif defined(__SDCC_PIC18F2480) + #include + +#elif defined(__SDCC_PIC18F2510) + #include + +#elif defined(__SDCC_PIC18F2515) + #include + +#elif defined(__SDCC_PIC18F2520) + #include + +#elif defined(__SDCC_PIC18F2523) + #include + +#elif defined(__SDCC_PIC18F2525) + #include + +#elif defined(__SDCC_PIC18F2539) + #include + +#elif defined(__SDCC_PIC18F2550) + #include + +#elif defined(__SDCC_PIC18F2553) + #include + +#elif defined(__SDCC_PIC18F2580) + #include + +#elif defined(__SDCC_PIC18F2585) + #include + +#elif defined(__SDCC_PIC18F2610) + #include + +#elif defined(__SDCC_PIC18F2620) + #include + +#elif defined(__SDCC_PIC18F2680) + #include + +#elif defined(__SDCC_PIC18F2682) + #include + +#elif defined(__SDCC_PIC18F2685) + #include + +#elif defined(__SDCC_PIC18F4220) + #include + +#elif defined(__SDCC_PIC18F4221) + #include + +#elif defined(__SDCC_PIC18F4320) + #include + +#elif defined(__SDCC_PIC18F4321) + #include + +#elif defined(__SDCC_PIC18F4331) + #include + +#elif defined(__SDCC_PIC18F4410) + #include + +#elif defined(__SDCC_PIC18F4420) + #include + +#elif defined(__SDCC_PIC18F4423) + #include + +#elif defined(__SDCC_PIC18F4431) + #include + +#elif defined(__SDCC_PIC18F4439) + #include + +#elif defined(__SDCC_PIC18F4450) + #include + +#elif defined(__SDCC_PIC18F4455) + #include + +#elif defined(__SDCC_PIC18F4458) + #include + +#elif defined(__SDCC_PIC18F4480) + #include + +#elif defined(__SDCC_PIC18F4510) + #include + +#elif defined(__SDCC_PIC18F4515) + #include + +#elif defined(__SDCC_PIC18F4520) + #include + +#elif defined(__SDCC_PIC18F4523) + #include + +#elif defined(__SDCC_PIC18F4525) + #include + +#elif defined(__SDCC_PIC18F4539) + #include + +#elif defined(__SDCC_PIC18F4550) + #include + +#elif defined(__SDCC_PIC18F4553) + #include + +#elif defined(__SDCC_PIC18F4580) + #include + +#elif defined(__SDCC_PIC18F4585) + #include + +#elif defined(__SDCC_PIC18F4610) + #include + +#elif defined(__SDCC_PIC18F4620) + #include + +#elif defined(__SDCC_PIC18F4680) + #include + +#elif defined(__SDCC_PIC18F4682) + #include + +#elif defined(__SDCC_PIC18F4685) + #include + +#elif defined(__SDCC_PIC18F6310) + #include + +#elif defined(__SDCC_PIC18F6390) + #include + +#elif defined(__SDCC_PIC18F6393) + #include + +#elif defined(__SDCC_PIC18F6410) + #include + +#elif defined(__SDCC_PIC18F6490) + #include + +#elif defined(__SDCC_PIC18F6493) + #include + +#elif defined(__SDCC_PIC18F6520) + #include + +#elif defined(__SDCC_PIC18F6525) + #include + +#elif defined(__SDCC_PIC18F6527) + #include + +#elif defined(__SDCC_PIC18F6585) + #include + +#elif defined(__SDCC_PIC18F6620) + #include + +#elif defined(__SDCC_PIC18F6621) + #include + +#elif defined(__SDCC_PIC18F6622) + #include + +#elif defined(__SDCC_PIC18F6627) + #include + +#elif defined(__SDCC_PIC18F6628) + #include + +#elif defined(__SDCC_PIC18F6680) + #include + +#elif defined(__SDCC_PIC18F6720) + #include + +#elif defined(__SDCC_PIC18F6722) + #include + +#elif defined(__SDCC_PIC18F6723) + #include + +#elif defined(__SDCC_PIC18F8310) + #include + +#elif defined(__SDCC_PIC18F8390) + #include + +#elif defined(__SDCC_PIC18F8393) + #include + +#elif defined(__SDCC_PIC18F8410) + #include + +#elif defined(__SDCC_PIC18F8490) + #include + +#elif defined(__SDCC_PIC18F8493) + #include + +#elif defined(__SDCC_PIC18F8520) + #include + +#elif defined(__SDCC_PIC18F8525) + #include + +#elif defined(__SDCC_PIC18F8527) + #include + +#elif defined(__SDCC_PIC18F8585) + #include + +#elif defined(__SDCC_PIC18F8620) + #include + +#elif defined(__SDCC_PIC18F8621) + #include + +#elif defined(__SDCC_PIC18F8622) + #include + +#elif defined(__SDCC_PIC18F8627) + #include + +#elif defined(__SDCC_PIC18F8628) + #include + +#elif defined(__SDCC_PIC18F8680) + #include + +#elif defined(__SDCC_PIC18F8720) + #include + +#elif defined(__SDCC_PIC18F8722) + #include + +#elif defined(__SDCC_PIC18F8723) + #include + +#elif defined(__SDCC_PIC18LF13K22) + #include + +#elif defined(__SDCC_PIC18LF13K50) + #include + +#elif defined(__SDCC_PIC18LF14K22) + #include + +#elif defined(__SDCC_PIC18LF14K50) + #include + +#elif defined(__SDCC_PIC18LF23K22) + #include + +#elif defined(__SDCC_PIC18LF24J10) + #include + +#elif defined(__SDCC_PIC18LF24J11) + #include + +#elif defined(__SDCC_PIC18LF24J50) + #include + +#elif defined(__SDCC_PIC18LF24K22) + #include + +#elif defined(__SDCC_PIC18LF24K50) + #include + +#elif defined(__SDCC_PIC18LF25J10) + #include + +#elif defined(__SDCC_PIC18LF25J11) + #include + +#elif defined(__SDCC_PIC18LF25J50) + #include + +#elif defined(__SDCC_PIC18LF25K22) + #include + +#elif defined(__SDCC_PIC18LF25K50) + #include + +#elif defined(__SDCC_PIC18LF25K80) + #include + +#elif defined(__SDCC_PIC18LF26J11) + #include + +#elif defined(__SDCC_PIC18LF26J13) + #include + +#elif defined(__SDCC_PIC18LF26J50) + #include + +#elif defined(__SDCC_PIC18LF26J53) + #include + +#elif defined(__SDCC_PIC18LF26K22) + #include + +#elif defined(__SDCC_PIC18LF26K80) + #include + +#elif defined(__SDCC_PIC18LF27J13) + #include + +#elif defined(__SDCC_PIC18LF27J53) + #include + +#elif defined(__SDCC_PIC18LF43K22) + #include + +#elif defined(__SDCC_PIC18LF44J10) + #include + +#elif defined(__SDCC_PIC18LF44J11) + #include + +#elif defined(__SDCC_PIC18LF44J50) + #include + +#elif defined(__SDCC_PIC18LF44K22) + #include + +#elif defined(__SDCC_PIC18LF45J10) + #include + +#elif defined(__SDCC_PIC18LF45J11) + #include + +#elif defined(__SDCC_PIC18LF45J50) + #include + +#elif defined(__SDCC_PIC18LF45K22) + #include + +#elif defined(__SDCC_PIC18LF45K50) + #include + +#elif defined(__SDCC_PIC18LF45K80) + #include + +#elif defined(__SDCC_PIC18LF46J11) + #include + +#elif defined(__SDCC_PIC18LF46J13) + #include + +#elif defined(__SDCC_PIC18LF46J50) + #include + +#elif defined(__SDCC_PIC18LF46J53) + #include + +#elif defined(__SDCC_PIC18LF46K22) + #include + +#elif defined(__SDCC_PIC18LF46K80) + #include + +#elif defined(__SDCC_PIC18LF47J13) + #include + +#elif defined(__SDCC_PIC18LF47J53) + #include + +#elif defined(__SDCC_PIC18LF65K80) + #include + +#elif defined(__SDCC_PIC18LF66K80) + #include + +#elif defined(__SDCC_PIC18LF242) + #include + +#elif defined(__SDCC_PIC18LF248) + #include + +#elif defined(__SDCC_PIC18LF252) + #include + +#elif defined(__SDCC_PIC18LF258) + #include + +#elif defined(__SDCC_PIC18LF442) + #include + +#elif defined(__SDCC_PIC18LF448) + #include + +#elif defined(__SDCC_PIC18LF452) + #include + +#elif defined(__SDCC_PIC18LF458) + #include + +#elif defined(__SDCC_PIC18LF1220) + #include + +#elif defined(__SDCC_PIC18LF1230) + #include + +#elif defined(__SDCC_PIC18LF1320) + #include + +#elif defined(__SDCC_PIC18LF1330) + #include + +#elif defined(__SDCC_PIC18LF2220) + #include + +#elif defined(__SDCC_PIC18LF2221) + #include + +#elif defined(__SDCC_PIC18LF2320) + #include + +#elif defined(__SDCC_PIC18LF2321) + #include + +#elif defined(__SDCC_PIC18LF2331) + #include + +#elif defined(__SDCC_PIC18LF2410) + #include + +#elif defined(__SDCC_PIC18LF2420) + #include + +#elif defined(__SDCC_PIC18LF2423) + #include + +#elif defined(__SDCC_PIC18LF2431) + #include + +#elif defined(__SDCC_PIC18LF2439) + #include + +#elif defined(__SDCC_PIC18LF2450) + #include + +#elif defined(__SDCC_PIC18LF2455) + #include + +#elif defined(__SDCC_PIC18LF2458) + #include + +#elif defined(__SDCC_PIC18LF2480) + #include + +#elif defined(__SDCC_PIC18LF2510) + #include + +#elif defined(__SDCC_PIC18LF2515) + #include + +#elif defined(__SDCC_PIC18LF2520) + #include + +#elif defined(__SDCC_PIC18LF2523) + #include + +#elif defined(__SDCC_PIC18LF2525) + #include + +#elif defined(__SDCC_PIC18LF2539) + #include + +#elif defined(__SDCC_PIC18LF2550) + #include + +#elif defined(__SDCC_PIC18LF2553) + #include + +#elif defined(__SDCC_PIC18LF2580) + #include + +#elif defined(__SDCC_PIC18LF2585) + #include + +#elif defined(__SDCC_PIC18LF2610) + #include + +#elif defined(__SDCC_PIC18LF2620) + #include + +#elif defined(__SDCC_PIC18LF2680) + #include + +#elif defined(__SDCC_PIC18LF2682) + #include + +#elif defined(__SDCC_PIC18LF2685) + #include + +#elif defined(__SDCC_PIC18LF4220) + #include + +#elif defined(__SDCC_PIC18LF4221) + #include + +#elif defined(__SDCC_PIC18LF4320) + #include + +#elif defined(__SDCC_PIC18LF4321) + #include + +#elif defined(__SDCC_PIC18LF4331) + #include + +#elif defined(__SDCC_PIC18LF4410) + #include + +#elif defined(__SDCC_PIC18LF4420) + #include + +#elif defined(__SDCC_PIC18LF4423) + #include + +#elif defined(__SDCC_PIC18LF4431) + #include + +#elif defined(__SDCC_PIC18LF4439) + #include + +#elif defined(__SDCC_PIC18LF4450) + #include + +#elif defined(__SDCC_PIC18LF4455) + #include + +#elif defined(__SDCC_PIC18LF4458) + #include + +#elif defined(__SDCC_PIC18LF4480) + #include + +#elif defined(__SDCC_PIC18LF4510) + #include + +#elif defined(__SDCC_PIC18LF4515) + #include + +#elif defined(__SDCC_PIC18LF4520) + #include + +#elif defined(__SDCC_PIC18LF4523) + #include + +#elif defined(__SDCC_PIC18LF4525) + #include + +#elif defined(__SDCC_PIC18LF4539) + #include + +#elif defined(__SDCC_PIC18LF4550) + #include + +#elif defined(__SDCC_PIC18LF4553) + #include + +#elif defined(__SDCC_PIC18LF4580) + #include + +#elif defined(__SDCC_PIC18LF4585) + #include + +#elif defined(__SDCC_PIC18LF4610) + #include + +#elif defined(__SDCC_PIC18LF4620) + #include + +#elif defined(__SDCC_PIC18LF4680) + #include + +#elif defined(__SDCC_PIC18LF4682) + #include + +#elif defined(__SDCC_PIC18LF4685) + #include + +#elif defined(__SDCC_PIC18LF6310) + #include + +#elif defined(__SDCC_PIC18LF6390) + #include + +#elif defined(__SDCC_PIC18LF6393) + #include + +#elif defined(__SDCC_PIC18LF6410) + #include + +#elif defined(__SDCC_PIC18LF6490) + #include + +#elif defined(__SDCC_PIC18LF6493) + #include + +#elif defined(__SDCC_PIC18LF6520) + #include + +#elif defined(__SDCC_PIC18LF6525) + #include + +#elif defined(__SDCC_PIC18LF6527) + #include + +#elif defined(__SDCC_PIC18LF6585) + #include + +#elif defined(__SDCC_PIC18LF6620) + #include + +#elif defined(__SDCC_PIC18LF6621) + #include + +#elif defined(__SDCC_PIC18LF6622) + #include + +#elif defined(__SDCC_PIC18LF6627) + #include + +#elif defined(__SDCC_PIC18LF6628) + #include + +#elif defined(__SDCC_PIC18LF6680) + #include + +#elif defined(__SDCC_PIC18LF6720) + #include + +#elif defined(__SDCC_PIC18LF6722) + #include + +#elif defined(__SDCC_PIC18LF6723) + #include + +#elif defined(__SDCC_PIC18LF8310) + #include + +#elif defined(__SDCC_PIC18LF8390) + #include + +#elif defined(__SDCC_PIC18LF8393) + #include + +#elif defined(__SDCC_PIC18LF8410) + #include + +#elif defined(__SDCC_PIC18LF8490) + #include + +#elif defined(__SDCC_PIC18LF8493) + #include + +#elif defined(__SDCC_PIC18LF8520) + #include + +#elif defined(__SDCC_PIC18LF8525) + #include + +#elif defined(__SDCC_PIC18LF8527) + #include + +#elif defined(__SDCC_PIC18LF8585) + #include + +#elif defined(__SDCC_PIC18LF8620) + #include + +#elif defined(__SDCC_PIC18LF8621) + #include + +#elif defined(__SDCC_PIC18LF8622) + #include + +#elif defined(__SDCC_PIC18LF8627) + #include + +#elif defined(__SDCC_PIC18LF8628) + #include + +#elif defined(__SDCC_PIC18LF8680) + #include + +#elif defined(__SDCC_PIC18LF8720) + #include + +#elif defined(__SDCC_PIC18LF8722) + #include + +#elif defined(__SDCC_PIC18LF8723) + #include + +#else + #error The sdcc is not supported by this processor! +#endif + +#ifndef __CONCAT2 + #define __CONCAT2(a, b) a##b +#endif + +#ifndef __CONCAT + #define __CONCAT(a, b) __CONCAT2(a, b) +#endif + +#define __CONFIG(address, value) \ + static const __code unsigned char __at(address) __CONCAT(_conf, __LINE__) = (value) + +#define Nop() __asm nop __endasm +#define ClrWdt() __asm clrwdt __endasm +#define Sleep() __asm sleep __endasm +#define Reset() __asm reset __endasm + + // To pointer manipulations. (From the sdcc/src/pic16/gen.h file.) +#define GPTR_TAG_MASK 0xC0 // Generated by the device-manager.pl program. +#define GPTR_TAG_DATA 0x80 +#define GPTR_TAG_EEPROM 0x40 +#define GPTR_TAG_CODE 0x00 + +#endif // #ifndef __PIC18FREGS_H__ +/*------------------------------------------------------------------------- + stdio.h - ANSI functions forward declarations + + Copyright (C) 1998, Sandeep Dutta . sandeep.dutta@usa.net + Ported to PIC16 port by Vangelis Rokas, 2004 + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __STDIO_H +#define __STDIO_H 1 + +/* link the C library */ +#pragma library c + +#include + +#include + +#ifndef NULL + #define NULL (void *)0 +#endif + +#ifndef _SIZE_T_DEFINED +#define _SIZE_T_DEFINED + typedef unsigned int size_t; +#endif + +/* stream descriptor definition */ +typedef char *FILE; + +/* USART and MSSP module stream descriptors */ + +/* since FILE is declared as a generic pointer, + * the upper byte is used to dereference the pointer + * information. For the stream descriptors we + * use the 5th bit and the lower nubble bits. + * Descriptors are denoted by an 1 in bit 5, + * further dereference is made for: + * <3:0> bits + * USART 0 (0x0) + * MSSP 1 (0x1) + * USER 15 (0xf) + * + * There is a special value for GPSIM specific (see below) + * which is: + * GPSIM 14 (0xe) + * + * + * if further stream descriptors need to be added then more + * bits of the upper byte can be used + */ + +#define USART_DEREF 0x0 +#define MSSP_DEREF 0x1 +#define USER_DEREF 0xf + +#define STREAM_USART ((FILE *)(0x00200000UL)) +#define STREAM_MSSP ((FILE *)(0x00210000UL)) +#define STREAM_USER ((FILE *)(0x002f0000UL)) + +/* this is a custom dereference which points to a custom + * port of GPSIM simulator. This port redirects characters + * to /tmp/gpsim.debug.1 file (used for debugging purposes) + * NOTICE: This feature is not part of the official gpsim + * distribution. Contact vrokas AT users.sourceforge.net + * for more info */ +#define GPSIM_DEREF 0xe +#define STREAM_GPSIM ((FILE *)(0x002e0000UL)) + +extern FILE *stdin; +extern FILE *stdout; + +/* printf_small() supports float print */ +void printf_small (const char *fmt, ...); + +/* printf_tiny() does not support float print */ +void printf_tiny (const char *fmt, ...); // __reentrant; + +extern int printf (const char *fmt, ...); +extern int fprintf (FILE *stream, const char *fmt, ...); +extern int sprintf (char *str, const char *fmt, ...); + +extern int vprintf (const char *fmt, va_list ap); +extern int vfprintf (FILE *stream, const char *fmt, va_list ap); +extern int vsprintf (char *str, const char *fmt, va_list ap); + +#define PUTCHAR(C) void putchar (char C) __wparam +extern PUTCHAR (c); + +extern void __stream_putchar (FILE *stream, char c); + +extern void __stream_usart_putchar (char c) __wparam __naked; +extern void __stream_mssp_putchar (char c) __wparam __naked; +extern void __stream_gpsim_putchar (char c) __wparam __naked; + +extern char *gets (char *str); +extern char getchar (void); + +#endif /* __STDIO_H */ +/*------------------------------------------------------------------------- + limits.h - ANSI defines constants for sizes of integral types + + Copyright (C) 1999, Sandeep Dutta . sandeep.dutta@usa.net + Adopted for the pic16 port by Vangelis Rokas 2004 + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __LIMITS_H +#define __LIMITS_H 1 + +#define CHAR_BIT 8 /* bits in a char */ +#define SCHAR_MAX 127 +#define SCHAR_MIN -128 +#define UCHAR_MAX 0xff +#define UCHAR_MIN 0 +#ifdef __SDCC_CHAR_UNSIGNED +#define CHAR_MAX UCHAR_MAX +#define CHAR_MIN UCHAR_MIN +#else +#define CHAR_MAX SCHAR_MAX +#define CHAR_MIN SCHAR_MIN +#endif +#define INT_MIN -32768 +#define INT_MAX 32767 +#define SHRT_MAX INT_MAX +#define SHRT_MIN INT_MIN +#define UINT_MAX 0xffff +#define UINT_MIN 0 +#define USHRT_MAX UINT_MAX +#define USHRT_MIN UINT_MIN +#define LONG_MIN -2147483648 +#define LONG_MAX 2147483647 +#define ULONG_MAX 0xffffffff +#define ULONG_MIN 0 + +#endif +/*------------------------------------------------------------------------- + malloc.h - dynamic memory allocation header + + Copyright (C) 2004, Vangelis Rokas + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +/* + * Structure of memory block header: + * bit 7 (MSB): allocated flag + * bits 0-6: pointer to next block (max length: 126) + * + */ + + +#ifndef __MALLOC_H__ +#define __MALLOC_H__ + + +/* set EMULATION to 1 to enable native Linux malloc emulation layer. This is + * for debugging purposes only */ + +#ifndef EMULATION +#define EMULATION 0 +#endif + +#if EMULATION +//#define malloc pic16_malloc +//#define free pic16_free +//#define realloc pic16_realloc +//#define calloc pic16_calloc + +//#define lmalloc pic16_lmalloc +//#define lfree pic16_lfree +//#define lrealloc pic16_lrealloc +//#define lcalloc pic16_lcalloc +#define _MALLOC_SPEC + +#else + +#pragma library c + +#define _MALLOC_SPEC __data + +#endif + +/* when MALLOC_MAX_FIRST is 1, the memory allocator tries to find a block + * that fits the requested size without merging (initially), if this block + * is not found, then tries to merge adjacent blocks. If MALLOC_MAX_FIRST is + * set 0, then the allocator tries to merge adjacent blocks in the first + * place. Both behaviours may give better results when used in certain + * circumstancs. I.e. if realloc is to be used, leaving some space after the + * block, will allow realloc to allocate it, otherwise it may result in much + * more memory fragmentation. An algorithm can be implemented to allow small + * fragments to be allocated but this is much too complicated for the PIC18F's + * architecture */ +#define MALLOC_MAX_FIRST 0 + +#define MAX_BLOCK_SIZE 0x7f /* 127 bytes */ +#define MAX_HEAP_SIZE 0x200 /* 512 bytes */ +#define _MAX_HEAP_SIZE (MAX_HEAP_SIZE-1) + +#define ALLOC_FLAG 0x80 +#define HEADER_SIZE 1 + +/* memory block header, max size 127 bytes, 126 usable */ +typedef union { + unsigned char datum; + struct { + unsigned count: 7; + unsigned alloc: 1; + } bits; +} _malloc_rec; + + +/* initialize heap, should be called before any call to malloc/realloc/calloc */ +void _initHeap(unsigned char _MALLOC_SPEC *dHeap, unsigned int heapsize); + + +/* start searching for a block of size at least bSize, merge adjacent blocks + * if necessery */ +_malloc_rec _MALLOC_SPEC *_mergeHeapBlock(_malloc_rec _MALLOC_SPEC *sBlock, unsigned char bSize); + + +/* allocate a memory block */ +unsigned char _MALLOC_SPEC *malloc(unsigned char len); + + +/* same as malloc, but clear memory */ +unsigned char _MALLOC_SPEC *calloc(unsigned char len); + + +/* expand or reduce a memory block, if mblock is NULL, then same as malloc */ +unsigned char _MALLOC_SPEC *realloc(unsigned char _MALLOC_SPEC *mblock, unsigned char len); + + +/* free a memory block */ +void free(unsigned char _MALLOC_SPEC *); + + +/* returns the size of all the unallocated memory */ +unsigned int memfree(void); + + +/* return the size of the maximum unallocated memory block */ +unsigned int memfreemax(void); + +#endif /* __MALLOC_H__ */ +/*------------------------------------------------------------------------- + float.h - ANSI functions forward declarations + + Copyright (C) 1998, Sandeep Dutta . sandeep.dutta@usa.net + Adopted for pic16 port library by Vangelis Rokas (2004) + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __FLOAT_H +#define __FLOAT_H 1 + +#include +#include + +#define FLT_RADIX 2 +#define FLT_MANT_DIG 24 +#define FLT_EPSILON 1.192092896E-07F +#define FLT_DIG 6 +#define FLT_MIN_EXP (-125) +#define FLT_MIN 1.175494351E-38F +#define FLT_MIN_10_EXP (-37) +#define FLT_MAX_EXP (+128) +#define FLT_MAX 3.402823466E+38F +#define FLT_MAX_10_EXP (+38) + +/* the following deal with IEEE single-precision numbers */ +#define EXCESS 126 +#define SIGNBIT ((unsigned long)0x80000000) +#define HIDDEN (unsigned long)(1ul << 23) +#define SIGN(fp) (((unsigned long)(fp) >> (8*sizeof(fp)-1)) & 1) +#define EXP(fp) (((unsigned long)(fp) >> 23) & (unsigned int) 0x00FF) +#define MANT(fp) (((fp) & (unsigned long)0x007FFFFF) | HIDDEN) +#define NORM 0xff000000 +#define PACK(s,e,m) ((s) | ((unsigned long)(e) << 23) | (m)) + + +float __uchar2fs (unsigned char) _FS_REENTRANT; +float __schar2fs (signed char) _FS_REENTRANT; +float __uint2fs (unsigned int) _FS_REENTRANT; +float __sint2fs (signed int) _FS_REENTRANT; +float __ulong2fs (unsigned long) _FS_REENTRANT; +float __slong2fs (signed long) _FS_REENTRANT; +unsigned char __fs2uchar (float) _FS_REENTRANT; +signed char __fs2schar (float) _FS_REENTRANT; +unsigned int __fs2uint (float) _FS_REENTRANT; +signed int __fs2sint (float) _FS_REENTRANT; +unsigned long __fs2ulong (float) _FS_REENTRANT; +signed long __fs2slong (float) _FS_REENTRANT; + +float __fsadd (float, float) _FS_REENTRANT; +float __fssub (float, float) _FS_REENTRANT; +float __fsmul (float, float) _FS_REENTRANT; +float __fsdiv (float, float) _FS_REENTRANT; + +char __fslt (float, float) _FS_REENTRANT; +char __fseq (float, float) _FS_REENTRANT; +char __fsneq (float, float) _FS_REENTRANT; +char __fsgt (float, float) _FS_REENTRANT; + +#endif + + + + + +/*------------------------------------------------------------------------- + i2c.h - I2C communications module library header + + Copyright (C) 2005, Vangelis Rokas + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ +/* + * Devices implemented: + * PIC18F[24][45][28] + */ + +#ifndef __I2C_H__ +#define __I2C_H__ + +/* link the I/O library */ +#pragma library io + +#include + + +#define _I2CPARAM_SPEC __data + + +/* I2C modes of operation */ +#define I2C_SLAVE10B_INT 0x0f +#define I2C_SLAVE7B_INT 0x0e +#define I2C_SLAVE_IDLE 0x0b +#define I2C_MASTER 0x08 +#define I2C_SLAVE10B 0x07 +#define I2C_SLAVE7B 0x06 + + +/* slew rate control */ +#define I2C_SLEW_OFF 0x80 +#define I2C_SLEW_ON 0x00 + +/* macros to generate hardware conditions on I2C module */ + +/* generate stop condition */ +#define I2C_STOP() do { SSPCON2bits.PEN = 1; } while (0) + +/* generate start condition */ +#define I2C_START() do { SSPCON2bits.SEN = 1; } while (0) + +/* generate restart condition */ +#define I2C_RESTART() do { SSPCON2bits.RSEN = 1; } while (0) + +/* generate not acknowledge condition */ +#define I2C_NACK() do { SSPCON2bits.ACKDT = 1; SSPCON2bits.ACKEN = 1; } while (0) + +/* generate acknowledge condition */ +#define I2C_ACK() do { SSPCON2bits.ACKDT = 0; SSPCON2bits.ACKEN = 1; } while (0) + +/* wait until I2C is idle */ +#define I2C_IDLE() do { /* busy waiting */ } while ((SSPCON2 & 0x1f) | (SSPSTATbits.R_W)) + +/* is data ready from I2C module ?? */ +#define I2C_DRDY() (SSPSTATbits.BF) + + +/* function equivalent to macros for generating hardware conditions */ + +/* stop */ +void i2c_stop(void); + +/* start */ +void i2c_start(void); + +/* restart */ +void i2c_restart(void); + +/* not acknowledge */ +void i2c_nack(void); + +/* acknowledge */ +void i2c_ack(void); + +/* wait until I2C goes idle */ +void i2c_idle(void); + +/* is character ready in I2C buffer ?? */ +unsigned char i2c_drdy(void); + +/* read a character from I2C module */ +unsigned char i2c_readchar(void); + +/* read a string from I2C module */ +char i2c_readstr(_I2CPARAM_SPEC unsigned char *ptr, unsigned char len); + +/* write a character to I2C module */ +char i2c_writechar(unsigned char dat); + +/* write a string to I2C module */ +char i2c_writestr(unsigned char *ptr); + +/* configure I2C port for operation */ +void i2c_open(unsigned char mode, unsigned char slew, unsigned char addr_brd); + +void i2c_close(void); + +#endif /* __I2C_H__ */ +/*------------------------------------------------------------------------- + adc.c - A/D conversion module library header + + Copyright (C) 2004, Vangelis Rokas + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ +/* + * Devices implemented: + * PIC18F[24][45][28] + * PIC18F2455-style + */ + +#ifndef __ADC_H__ +#define __ADC_H__ + +/* link I/O libarary */ +#pragma library io + +/* + * adc_open's `channel' argument: + * + * one of ADC_CHN_* + */ + +/* channel selection (CHS field in ADCON0) */ +#define ADC_CHN_0 0x00 +#define ADC_CHN_1 0x01 +#define ADC_CHN_2 0x02 +#define ADC_CHN_3 0x03 +#define ADC_CHN_4 0x04 +#define ADC_CHN_5 0x05 +#define ADC_CHN_6 0x06 +#define ADC_CHN_7 0x07 +#define ADC_CHN_8 0x08 +#define ADC_CHN_9 0x09 +#define ADC_CHN_10 0x0a +#define ADC_CHN_11 0x0b +#define ADC_CHN_12 0x0c +#define ADC_CHN_13 0x0d +#define ADC_CHN_14 0x0e +#define ADC_CHN_DAC 0x0e /* 13k50-style */ +#define ADC_CHN_15 0x0f +#define ADC_CHN_FVR 0x0f /* 13k50-style */ +/* more channels: 23k22-style */ +#define ADC_CHN_16 0x10 +#define ADC_CHN_17 0x11 +#define ADC_CHN_18 0x12 +#define ADC_CHN_19 0x13 +#define ADC_CHN_20 0x14 +#define ADC_CHN_21 0x15 +#define ADC_CHN_22 0x16 +#define ADC_CHN_23 0x17 +#define ADC_CHN_24 0x18 +#define ADC_CHN_25 0x19 +#define ADC_CHN_26 0x1a +#define ADC_CHN_27 0x1b +#define ADC_CHN_K_CTMU 0x1d +#define ADC_CHN_K_DAC 0x1e +#define ADC_CHN_K_FVR 0x1f + + +/* + * adc_open's `fosc' argument: + * + * ADC_FOSC_* | ADC_ACQT_* | ADC_CAL | ADC_TRIGSEL_* + * + * 7 6 5 4 3 2 1 0 + * +-----+-----+-----+-----+-----+-----+-----+-----+ + * | TRG | CAL | ACQT | FOSC/ADCS | + * +-----+-----+-----+-----+-----+-----+-----+-----+ + */ + +/* oscillator frequency (ADCS field) */ +#define ADC_FOSC_2 0x00 +#define ADC_FOSC_4 0x04 +#define ADC_FOSC_8 0x01 +#define ADC_FOSC_16 0x05 +#define ADC_FOSC_32 0x02 +#define ADC_FOSC_64 0x06 +#define ADC_FOSC_RC 0x07 + +/* acquisition time (13k50/2220/24j50/65j50-styles only) */ +#define ADC_ACQT_0 (0x00 << 3) +#define ADC_ACQT_2 (0x01 << 3) +#define ADC_ACQT_4 (0x02 << 3) +#define ADC_ACQT_6 (0x03 << 3) +#define ADC_ACQT_8 (0x04 << 3) +#define ADC_ACQT_12 (0x05 << 3) +#define ADC_ACQT_16 (0x06 << 3) +#define ADC_ACQT_20 (0x07 << 3) + +/* calibration enable (24j50/65j50-style only) */ +#define ADC_CAL 0x40 + +/* trigger selection (23k22-style only) */ +#define ADC_TRIGGER 0x80 + + +/* + * adc_open's `pcfg' argment: + * + * ADC_CFG_* (see below, style-specific) + */ + + +/* + * adc_open's `config' argument: + * + * ADC_FRM_* | ADC_INT_* | ADC_VCFG_* | ADC_NVCFG_* | ADC_PVCFG_* + * + * 7 6 5 4 3 2 1 0 + * +-----+-----+-----+-----+-----+-----+-----+-----+ + * | FRM | INT | VCFG | PVCFG | NVCFG | + * +-----+-----+-----+-----+-----+-----+-----+-----+ + */ + +/* output format */ +#define ADC_FRM_LJUST 0x00 +#define ADC_FRM_RJUST 0x80 + +/* interrupt on/off flag */ +#define ADC_INT_OFF 0x00 +#define ADC_INT_ON 0x40 + +/* reference voltage configuration (not for 18f242-style ADC) */ +#define ADC_VCFG_VDD_VSS 0x00 +#define ADC_VCFG_AN3_VSS 0x10 +#define ADC_VCFG_VDD_AN2 0x20 +#define ADC_VCFG_AN3_AN2 0x30 + +/* reference voltage configuration (13k50-style) */ +#define ADC_NVCFG_VSS 0x00 +#define ADC_NVCFG_AN5 0x01 + +#define ADC_PVCFG_VDD (0x00 << 2) +#define ADC_PVCFG_AN4 (0x01 << 2) +#define ADC_PVCFG_FVR (0x02 << 2) + +/* reference voltage configuration (23k22-style) */ +#define ADC_NVCFG_AN2 0x01 +#define ADC_PVCFG_AN3 (0x01 << 2) +#define ADC_TRIGSEL_CCP5 (0x00 << 7) +#define ADC_TRIGSEL_CTMU (0x01 << 7) + + +/* + * Distinguishing between ADC-styles: + * - 18f24j50-style devices have separate ANCON0/ANCON1 + * registers for A/D port pin configuration, whereas + * 18f65j50-style devices multiplex ANCONx and ADCONx + * + * ADCON0: + * bit 18f242 18f1220 18f1230 18f13k50 18f2220 18f24j50 18f65j50 18f23k22 + * 0 ADON ADON ADON ADON ADON ADON ADON ADON + * 1 - GO GO GO GO GO GO GO + * 2 GO CHS0 CHS0 CHS0 CHS0 CHS0 CHS0 CHS0 + * 3 CHS0 CHS1 CHS1 CHS1 CHS1 CHS1 CHS1 CHS1 + * 4 CHS1 CHS2 - CHS2 CHS2 CHS2 CHS2 CHS2 + * 5 CHS2 - - CHS3 CHS3 CHS3 CHS3 CHS3 + * 6 ADCS0 VCFG0 - - - VCFG0 VCFG0 CHS4 + * 7 ADCS1 VCFG1 SEVTEN - (ADCAL) VCFG1 VCFG1 - + * + * ADCON1: + * bit 18f242 18f1220 18f1230 18f13k50 18f2220 18f24j50 18f65j50 18f23k22 + * 0 PCFG0 PCFG0 PCFG0 NVCFG0 PCFG0 ADCS0 ADCS0 NVCFG0 + * 1 PCFG1 PCFG1 PCFG1 NVCFG1 PCFG1 ADCS1 ADCS1 NVCFG1 + * 2 PCFG2 PCFG2 PCFG2 PVCFG0 PCFG2 ADCS2 ADCS2 PVCFG0 + * 3 PCFG3 PCFG3 PCFG3 PVCFG1 PCFG3 ACQT0 ACQT0 PVCFG1 + * 4 - PCFG4 VCFG0 - VCFG0 ACQT1 ACQT1 - + * 5 - PCFG5 - VCFG1 ACQT2 ACQT2 - + * 6 ADCS2 PCFG6 - - ADCAL ADCAL - + * 7 ADFM - - - ADFM ADFM TRIGSEL + * + * ADCON2: + * bit 18f242 18f1220 18f1230 18f13k50 18f2220 18f24j50 18f65j50 18f23k22 + * 0 ADCS0 ADCS0 ADCS0 ADCS0 + * 1 ADCS1 ADCS1 ADCS1 ADCS1 + * 2 ADCS2 ADCS2 ADCS2 ADCS2 + * 3 ACQT0 ACQT0 ADQT0 ACQT0 + * 4 ACQT1 ACQT1 ADQT1 ACQT1 + * 5 ACQT2 ACQT2 ADQT2 ACQT2 + * 6 - - - - + * 7 ADFM ADFM ADFM ADFM + */ +#include "pic18fam.h" + + + +/* Port configuration (PCFG (and VCFG) field(s) in ADCON1) */ +#if (__SDCC_ADC_STYLE == 0) + +#warning The target device is not supported by the SDCC PIC16 ADC library. + +#elif (__SDCC_ADC_STYLE == 1802420) + +#define ADC_CFG_8A_0R 0x00 +#define ADC_CFG_7A_1R 0x01 +#define ADC_CFG_5A_0R 0x02 +#define ADC_CFG_4A_1R 0x03 +#define ADC_CFG_3A_0R 0x04 +#define ADC_CFG_2A_1R 0x05 +#define ADC_CFG_0A_0R 0x06 +#define ADC_CFG_6A_2R 0x08 +#define ADC_CFG_6A_0R 0x09 +#define ADC_CFG_5A_1R 0x0a +#define ADC_CFG_4A_2R 0x0b +#define ADC_CFG_3A_2R 0x0c +#define ADC_CFG_2A_2R 0x0d +#define ADC_CFG_1A_0R 0x0e +#define ADC_CFG_1A_2R 0x0f + +#elif (__SDCC_ADC_STYLE == 1812200) + +/* + * These devices use a bitmask in ADCON1 to configure AN0..AN6 + * as digital ports (bit set) or analog input (bit clear). + * + * These settings are selected based on their similarity with + * the 2220-style settings; 1220-style is more flexible, though. + * + * Reference voltages are configured via adc_open's config parameter + * using ADC_VCFG_*. + */ + +#define ADC_CFG_6A 0x00 +#define ADC_CFG_5A 0x20 +#define ADC_CFG_4A 0x30 +#define ADC_CFG_3A 0x38 +#define ADC_CFG_2A 0x3c +#define ADC_CFG_1A 0x3e +#define ADC_CFG_0A 0x3f + +#elif (__SDCC_ADC_STYLE == 1812300) + +/* + * These devices use a bitmask in ADCON1 to configure AN0..AN3 + * as digital ports (bit set) or analog input (bit clear). + * + * These settings are selected based on their similarity with + * the 2220-style settings; 1230-style is more flexible, though. + * + * Reference voltages are configured via adc_open's config parameter + * using ADC_VCFG_*. + */ + +#define ADC_CFG_4A 0x00 +#define ADC_CFG_3A 0x08 +#define ADC_CFG_2A 0x0c +#define ADC_CFG_1A 0x0e +#define ADC_CFG_0A 0x0f + +#define ADC_VCFG_AVDD 0x00 /* AVdd */ +#define ADC_VCFG_VREF 0x10 /* Vref+ */ + +#elif (__SDCC_ADC_STYLE == 1813502) + +/* + * These devices use a bitmask in ANSEL/H to configure + * AN7..0/AN15..8 as digital ports (bit clear) or analog + * inputs (bit set). + * + * These settings are selected based on their similarity with + * the 2220-style settings; 13k50-style is more flexible, though. + * + * Reference voltages are configured via adc_open's config parameter + * using ADC_PVCFG_* and ADC_NVCFG_*. + */ + +#define ADC_CFG_16A 0xFFFF +#define ADC_CFG_15A 0x7FFF +#define ADC_CFG_14A 0x3FFF +#define ADC_CFG_13A 0x1FFF +#define ADC_CFG_12A 0x0FFF +#define ADC_CFG_11A 0x07FF +#define ADC_CFG_10A 0x03FF +#define ADC_CFG_9A 0x01FF +#define ADC_CFG_8A 0x00FF +#define ADC_CFG_7A 0x007F +#define ADC_CFG_6A 0x003F +#define ADC_CFG_5A 0x001F +#define ADC_CFG_4A 0x000F +#define ADC_CFG_3A 0x0007 +#define ADC_CFG_2A 0x0003 +#define ADC_CFG_1A 0x0001 +#define ADC_CFG_0A 0x0000 + +#elif (__SDCC_ADC_STYLE == 1822200) + +/* + * The reference voltage configuration should be factored out into + * the config argument (ADC_VCFG_*) to adc_open to facilitate a + * merger with the 1220-style ADC. + */ + +#define ADC_CFG_16A 0x00 +/* 15 analog ports cannot be configured! */ +#define ADC_CFG_14A 0x01 +#define ADC_CFG_13A 0x02 +#define ADC_CFG_12A 0x03 +#define ADC_CFG_11A 0x04 +#define ADC_CFG_10A 0x05 +#define ADC_CFG_9A 0x06 +#define ADC_CFG_8A 0x07 +#define ADC_CFG_7A 0x08 +#define ADC_CFG_6A 0x09 +#define ADC_CFG_5A 0x0a +#define ADC_CFG_4A 0x0b +#define ADC_CFG_3A 0x0c +#define ADC_CFG_2A 0x0d +#define ADC_CFG_1A 0x0e +#define ADC_CFG_0A 0x0f + +/* + * For compatibility only: Combined port and reference voltage selection. + * Consider using ADC_CFG_nA and a separate ADC_VCFG_* instead! + */ + +#define ADC_CFG_16A_0R 0x00 +#define ADC_CFG_16A_1R 0x10 +#define ADC_CFG_16A_2R 0x30 + +/* Can only select 14 or 16 analog ports ... */ +#define ADC_CFG_15A_0R 0x00 +#define ADC_CFG_15A_1R 0x10 +#define ADC_CFG_15A_2R 0x30 + +#define ADC_CFG_14A_0R 0x01 +#define ADC_CFG_14A_1R 0x11 +#define ADC_CFG_14A_2R 0x31 +#define ADC_CFG_13A_0R 0x02 +#define ADC_CFG_13A_1R 0x12 +#define ADC_CFG_13A_2R 0x32 +#define ADC_CFG_12A_0R 0x03 +#define ADC_CFG_12A_1R 0x13 +#define ADC_CFG_12A_2R 0x33 +#define ADC_CFG_11A_0R 0x04 +#define ADC_CFG_11A_1R 0x14 +#define ADC_CFG_11A_2R 0x34 +#define ADC_CFG_10A_0R 0x05 +#define ADC_CFG_10A_1R 0x15 +#define ADC_CFG_10A_2R 0x35 +#define ADC_CFG_09A_0R 0x06 +#define ADC_CFG_09A_1R 0x16 +#define ADC_CFG_09A_2R 0x36 +#define ADC_CFG_08A_0R 0x07 +#define ADC_CFG_08A_1R 0x17 +#define ADC_CFG_08A_2R 0x37 +#define ADC_CFG_07A_0R 0x08 +#define ADC_CFG_07A_1R 0x18 +#define ADC_CFG_07A_2R 0x38 +#define ADC_CFG_06A_0R 0x09 +#define ADC_CFG_06A_1R 0x19 +#define ADC_CFG_06A_2R 0x39 +#define ADC_CFG_05A_0R 0x0a +#define ADC_CFG_05A_1R 0x1a +#define ADC_CFG_05A_2R 0x3a +#define ADC_CFG_04A_0R 0x0b +#define ADC_CFG_04A_1R 0x1b +#define ADC_CFG_04A_2R 0x3b +#define ADC_CFG_03A_0R 0x0c +#define ADC_CFG_03A_1R 0x1c +#define ADC_CFG_03A_2R 0x3c +#define ADC_CFG_02A_0R 0x0d +#define ADC_CFG_02A_1R 0x1d +#define ADC_CFG_02A_2R 0x3d +#define ADC_CFG_01A_0R 0x0e +#define ADC_CFG_01A_1R 0x1e +#define ADC_CFG_01A_2R 0x3e +#define ADC_CFG_00A_0R 0x0f + +#elif (__SDCC_ADC_STYLE == 1823222) + +/* use ANSELA, ANSELB, ANSELC, ANSELD, ANSELE registers and + * TRISA, TRISB, TRISC, TRISD, TRISE registers to set + * corresponding port to analog mode + * Note: 46k22 supports up to 28 ADC ports */ + + +#elif (__SDCC_ADC_STYLE == 1824501) || (__SDCC_ADC_STYLE == 1865501) + +/* + * These devices use a bitmask in ANCON0/1 to configure + * AN7..0/AN15..8 as digital ports (bit set) or analog + * inputs (bit clear). + * + * These settings are selected based on their similarity with + * the 2220-style settings; 24j50/65j50-style is more flexible, though. + * + * Reference voltages are configured via adc_open's config parameter + * using ADC_VCFG_*. + */ + +#define ADC_CFG_16A 0x0000 +#define ADC_CFG_15A 0x8000 +#define ADC_CFG_14A 0xC000 +#define ADC_CFG_13A 0xE000 +#define ADC_CFG_12A 0xF000 +#define ADC_CFG_11A 0xF800 +#define ADC_CFG_10A 0xFC00 +#define ADC_CFG_9A 0xFE00 +#define ADC_CFG_8A 0xFF00 +#define ADC_CFG_7A 0xFF80 +#define ADC_CFG_6A 0xFFC0 +#define ADC_CFG_5A 0xFFE0 +#define ADC_CFG_4A 0xFFF0 +#define ADC_CFG_3A 0xFFF8 +#define ADC_CFG_2A 0xFFFC +#define ADC_CFG_1A 0xFFFE +#define ADC_CFG_0A 0xFFFF + +#else /* unhandled ADC style */ + +#error No supported ADC style selected. + +#endif /* __SDCC_ADC_STYLE */ + + + +#if (__SDCC_ADC_STYLE == 1813502) \ + || (__SDCC_ADC_STYLE == 1824501) \ + || (__SDCC_ADC_STYLE == 1865501) +typedef unsigned int sdcc_pcfg_t; +#else /* other styles */ +typedef unsigned char sdcc_pcfg_t; +#endif + +/* initialize AD module */ +void adc_open (unsigned char channel, unsigned char fosc, sdcc_pcfg_t pcfg, unsigned char config); + +/* shutdown AD module */ +void adc_close (void); + +/* begin a conversion */ +void adc_conv (void); + +/* return 1 if AD is performing a conversion, 0 if done */ +char adc_busy (void) __naked; + +/* get value of conversion */ +int adc_read (void) __naked; + +/* setup conversion channel */ +void adc_setchannel (unsigned char channel); + +#endif + +/*------------------------------------------------------------------------- + ctype.h - ANSI functions forward declarations + + Copyright (C) 1998, Sandeep Dutta . sandeep.dutta@usa.net + Modified for pic16 port by Vangelis Rokas, 2004, + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ +/* + Revisions: + 1.0 - June.1.2000 1.0 - Bela Torok / bela.torok@kssg.ch + order: function definitions -> macros + corretced macro: isalpha(c) + added macros: _tolower(c), _toupper(c), tolower(c), toupper(c) toascii(c) +*/ + +#ifndef __CTYPE_H +#define __CTYPE_H 1 + +/* link the C libarary */ +#pragma library c + +#include + +extern char iscntrl (unsigned char ) ; +extern char isdigit (unsigned char ) ; +extern char isgraph (unsigned char ) ; +extern char islower (unsigned char ) ; +extern char isupper (unsigned char ) ; +extern char isprint (unsigned char ) ; +extern char ispunct (unsigned char ) ; +extern char isspace (unsigned char ) ; +extern char isxdigit (unsigned char ) ; + +#define isalnum(c) (isalpha(c) || isdigit(c)) +#define isalpha(c) (isupper(c) || islower(c)) + +/* ANSI versions of _tolower & _toupper +#define _tolower(c) ((c) - ('a' - 'A')) +#define _toupper(c) ((c) + ('a' - 'A')) +*/ + +// The _tolower & _toupper functions below can applied to any +// alpha characters regardless of the case (upper or lower) +#define _tolower(c) ((c) | ('a' - 'A')) +#define _toupper(c) ((c) & ~('a' - 'A')) + +#define tolower(c) ((isupper(c)) ? _tolower(c) : (c)) +#define toupper(c) ((islower(c)) ? _toupper(c) : (c)) +#define toascii(c) ((c) & 0x7F) + +#endif +/*------------------------------------------------------------------------- + math.h - Floating point math function declarations + + Copyright (C) 2001, Jesus Calvino-Fraga + Ported to PIC16 port by Vangelis Rokas, 2004 + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __PIC16_MATH_H +#define __PIC16_MATH_H 1 + +#pragma library math + +#include + +#define PI 3.1415926536 +#define TWO_PI 6.2831853071 +#define HALF_PI 1.5707963268 +#define QUART_PI 0.7853981634 +#define iPI 0.3183098862 +#define iTWO_PI 0.1591549431 +#define TWO_O_PI 0.6366197724 + +// EPS=B**(-t/2), where B is the radix of the floating-point representation +// and there are t base-B digits in the significand. Therefore, for floats +// EPS=2**(-12). Also define EPS2=EPS*EPS. +#define EPS 244.14062E-6 +#define EPS2 59.6046E-9 +#define XMAX 3.402823466E+38 + +union float_long +{ + float f; + long l; +}; + +/********************************************** + * Prototypes for float ANSI C math functions * + **********************************************/ + +/* Trigonometric functions */ +float sinf(float x) _MATH_REENTRANT; +float cosf(float x) _MATH_REENTRANT; +float tanf(float x) _MATH_REENTRANT; +float cotf(float x) _MATH_REENTRANT; +float asinf(float x) _MATH_REENTRANT; +float acosf(float x) _MATH_REENTRANT; +float atanf(float x) _MATH_REENTRANT; +float atan2f(float x, float y); + +/* Hyperbolic functions */ +float sinhf(float x) _MATH_REENTRANT; +float coshf(float x) _MATH_REENTRANT; +float tanhf(float x) _MATH_REENTRANT; + +/* Exponential, logarithmic and power functions */ +float expf(float x); +float logf(float x) _MATH_REENTRANT; +float log10f(float x) _MATH_REENTRANT; +float powf(float x, float y); +float sqrtf(float a) _MATH_REENTRANT; + +/* Nearest integer, absolute value, and remainder functions */ +float fabsf(float x) _MATH_REENTRANT; +float frexpf(float x, int *pw2); +float ldexpf(float x, int pw2); +float ceilf(float x) _MATH_REENTRANT; +float floorf(float x) _MATH_REENTRANT; +float modff(float x, float * y); + +int isnan(float f); +int isinf(float f); +#endif /* _PIC16_MATH_H */ +/*------------------------------------------------------------------------- + usart.h - USART communications module library header + + Copyright (C) 2005, Vangelis Rokas + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __USART_H__ +#define __USART_H__ + +#pragma library io + + +#define RAM_SCLS __data + +/* configuration bit masks for open function */ +#define USART_TX_INT_ON 0xff +#define USART_TX_INT_OFF 0x7f +#define USART_RX_INT_ON 0xff +#define USART_RX_INT_OFF 0xbf +#define USART_BRGH_HIGH 0xff +#define USART_BRGH_LOW 0xef +#define USART_CONT_RX 0xff +#define USART_SINGLE_RX 0xf7 +#define USART_SYNC_MASTER 0xff +#define USART_SYNC_SLAVE 0xfb +#define USART_NINE_BIT 0xff +#define USART_EIGHT_BIT 0xfd +#define USART_SYNCH_MODE 0xff +#define USART_ASYNCH_MODE 0xfe + +/* + * USART styles: + * + * --- Families with 1 USART --- + * + * INIT: + * RCSTA<7> = 1 (SPEN) + * TXSTA<4> = 0 (SYNC) + * TXSTA<5> = 1 (TXEN) + * + * 18f1220: + * RB1/AN5/TX and RB4/AN6/RX + * + * TRISB<1> = TRISB<4> = 1 (TX, RX) + * ADCON1<5> = ADCON1<6> = 1 (PCFG<5>, PCFG<6>) + * SPBRGH:SPBRG + * + * 18f13k50: + * RB7/TX and RB5/AN11/RX + * + * TRISB<7> = TRISB<5> = 1 (TX, RX) + * ANSELH<3> = 0 (ANS11/RX) + * SPBRGH:SPBRG + * + * 18f2220: + * RC6/TX and RC7/RX + * + * TRISC<6> = 0 (TX) + * TRISC<7> = 1 (RX) + * SPBRG + * + * 18f2221/18f2331/18f23k20/18f2410/18f2420/18f2423/18f2455/18f24j10/18f2525: + * RC6/TX and RC7/RX + * + * TRISC<6> = TRISC<7> = 1 (TX, RX) + * SPBRGH:SPBRG + * + * 18f2450/18f2480/18f2585/18f2682/18f6585/18f6680/18f8585/18f8680: + * RC6/TX and RC7/RX + * + * TRISC<6> = 0 (TX) + * TRISC<7> = 1 (RX) + * SPBRGH:SPBRG + * + * --- Families with 2+ USARTs --- + * + * INIT: + * RCSTA1<7> = 1 (SPEN) + * TXSTA1<4> = 0 (SYNC) + * TXSTA1<5> = 1 (TXEN) + * + * 18f24j50/18f6527/18f65j50/18f66j60: + * RC6/TX1 and RC7/RX1 (EUSART1) + * + * TRISC<6> = 0 (TX1) + * TRISC<7> = 1 (RX1) + * SPBRGH1:SPBRG1 + * + * 18f6520: + * RC6/TX1 and RC7/RX1 (EUSART1) + * + * TRISC<6> = 0 (TX1) + * TRISC<7> = 1 (RX1) + * SPBRG1 + * + */ +#include "pic18fam.h" + +#if (__SDCC_USART_STYLE == 0) +#warning The target device is not supported by the SDCC PIC16 USART library. +#endif + +#if (__SDCC_USART_STYLE == 1822200) || \ + (__SDCC_USART_STYLE == 1865200) +#define __SDCC_NO_SPBRGH 1 +#endif /* device lacks SPBRGH */ + + +#if __SDCC_NO_SPBRGH +typedef unsigned char sdcc_spbrg_t; +#else /* !__SDCC_NO_SPBRGH */ +typedef unsigned int sdcc_spbrg_t; +#endif /* !__SDCC_NO_SPBRGH */ + + +/* status bits */ +union USART +{ + unsigned char val; + struct + { + unsigned RX_NINE:1; + unsigned TX_NINE:1; + unsigned FRAME_ERROR:1; + unsigned OVERRUN_ERROR:1; + unsigned fill:4; + }; +}; + +void usart_open (unsigned char config, sdcc_spbrg_t spbrg) __wparam; +void usart_close (void); + +unsigned char usart_busy (void) __naked; +unsigned char usart_drdy (void) __naked; + +unsigned char usart_getc (void); +void usart_gets (RAM_SCLS char * buffer, unsigned char len); + +void usart_putc (unsigned char data) __wparam __naked; +void usart_puts (char * data); + + +void usart_baud (sdcc_spbrg_t baudconfig) __wparam; + +#endif +/*------------------------------------------------------------------------- + stdint.h - ISO C99 7.18 Integer types + + Copyright (C) 2005, Maarten Brock + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef _STDINT_H +#define _STDINT_H 1 + +/* Exact integral types. */ + +/* Signed. */ + +typedef signed char int8_t; +typedef short int int16_t; +typedef long int int32_t; + +/* Unsigned. */ +typedef unsigned char uint8_t; +typedef unsigned short int uint16_t; +typedef unsigned long int uint32_t; + + +/* Small types. */ + +/* Signed. */ +typedef signed char int_least8_t; +typedef short int int_least16_t; +typedef long int int_least32_t; + +/* Unsigned. */ +typedef unsigned char uint_least8_t; +typedef unsigned short int uint_least16_t; +typedef unsigned long int uint_least32_t; + + +/* Fast types. */ + +/* Signed. */ +typedef signed char int_fast8_t; +typedef int int_fast16_t; +typedef long int int_fast32_t; + +/* Unsigned. */ +typedef unsigned char uint_fast8_t; +typedef unsigned int uint_fast16_t; +typedef unsigned long int uint_fast32_t; + + +/* Types for `void *' pointers. */ +typedef long int intptr_t; +typedef unsigned long int uintptr_t; + + +/* Largest integral types. */ +typedef long int intmax_t; +typedef unsigned long int uintmax_t; + + +/* Limits of integral types. */ + +/* Minimum of signed integral types. */ +# define INT8_MIN (-128) +# define INT16_MIN (-32767-1) +# define INT32_MIN (-2147483647L-1) +/* Maximum of signed integral types. */ +# define INT8_MAX (127) +# define INT16_MAX (32767) +# define INT32_MAX (2147483647L) + +/* Maximum of unsigned integral types. */ +# define UINT8_MAX (255) +# define UINT16_MAX (65535) +# define UINT32_MAX (4294967295UL) + +/* Minimum of signed integral types having a minimum size. */ +# define INT_LEAST8_MIN (-128) +# define INT_LEAST16_MIN (-32767-1) +# define INT_LEAST32_MIN (-2147483647L-1) +/* Maximum of signed integral types having a minimum size. */ +# define INT_LEAST8_MAX (127) +# define INT_LEAST16_MAX (32767) +# define INT_LEAST32_MAX (2147483647L) + +/* Maximum of unsigned integral types having a minimum size. */ +# define UINT_LEAST8_MAX (255) +# define UINT_LEAST16_MAX (65535) +# define UINT_LEAST32_MAX (4294967295UL) + +/* Minimum of fast signed integral types having a minimum size. */ +# define INT_FAST8_MIN (-128) +# define INT_FAST16_MIN (-32767-1) +# define INT_FAST32_MIN (-2147483647L-1) + +/* Maximum of fast signed integral types having a minimum size. */ +# define INT_FAST8_MAX (127) +# define INT_FAST16_MAX (32767) +# define INT_FAST32_MAX (2147483647L) + +/* Maximum of fast unsigned integral types having a minimum size. */ +# define UINT_FAST8_MAX (255) +# define UINT_FAST16_MAX (65535) +# define UINT_FAST32_MAX (4294967295UL) + +/* Values to test for integral types holding `void *' pointer. */ +# define INTPTR_MIN (-2147483647L-1) +# define INTPTR_MAX (2147483647L) +# define UINTPTR_MAX (4294967295UL) + +/* Minimum for largest signed integral type. */ +# define INTMAX_MIN (-__INT32_C(-2147483647L)-1) +/* Maximum for largest signed integral type. */ +# define INTMAX_MAX (__INT32_C(2147483647L)) + +/* Maximum for largest unsigned integral type. */ +# define UINTMAX_MAX (__UINT32_C(4294967295UL)) + + +/* Limits of other integer types. */ + +/* Limits of `ptrdiff_t' type. */ +# define PTRDIFF_MIN (-2147483647L-1) +# define PTRDIFF_MAX (2147483647L) + +/* Limit of `size_t' type. */ +# define SIZE_MAX (65535) + +/* Signed. */ +# define INT8_C(c) c +# define INT16_C(c) c +# define INT32_C(c) c ## L + +/* Unsigned. */ +# define UINT8_C(c) c ## U +# define UINT16_C(c) c ## U +# define UINT32_C(c) c ## UL + +/* Maximal type. */ +# define INTMAX_C(c) c ## L +# define UINTMAX_C(c) c ## UL + + +#endif /* stdint.h */ +/*------------------------------------------------------------------------- + delay.h - delay functions header file + + Copyright (C) 2005, Vangelis Rokas + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __DELAY_H__ +#define __DELAY_H__ + +#pragma library c + +/* + * the delayNNtcy family of functions performs a + * delay of NN cycles. Possible values for NN are: + * 10 10*n cycles delay + * 100 100*n cycles delay + * 1k 1000*n cycles delay + * 10k 10000*n cycles delay + * 100k 100000*n cycles delay + * 1m 1000000*n cycles delay + */ + +void delay10tcy(unsigned char) __wparam; +void delay100tcy(unsigned char) __wparam; +void delay1ktcy(unsigned char) __wparam; +void delay10ktcy(unsigned char) __wparam; +void delay100ktcy(unsigned char) __wparam; +void delay1mtcy(unsigned char) __wparam; + +#endif +/*------------------------------------------------------------------------- + stdarg.h - ANSI macros for variable parameter list + + Copyright (C) 1998, Sandeep Dutta . sandeep.dutta@usa.net + Ported to PIC16 port by Vangelis Rokas, 2004 (vrokas@otenet.gr) + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __PIC16_STDARG_H +#define __PIC16_STDARG_H 1 + +typedef unsigned char * va_list; +#define va_start(list, last) list = (unsigned char *)&last + sizeof(last) +#define va_arg(list, type) *((type *)((list += sizeof(type)) - sizeof(type))) +#define va_end(list) list = ((va_list) 0) + +#endif /* __PIC16_STDARG_H */ +#-------------------------------------------------------------------------- +# pic16devices.txt - Specification of devices supported by the PIC16 +# target of the Small Devices C Compiler (SDCC). +# +# Copyright (C) 2008 Raphael Neider +# Copyright (C) 2012 Molnar Karoly +# +# This library is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the +# Free Software Foundation; either version 2, or (at your option) any +# later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this library; see the file COPYING. If not, write to the +# Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301, USA. +#-------------------------------------------------------------------------- + +# +# Lines starting with a hash '#' are ignored. +# A new device specification must begin with a 'name' command. +# Numbers can be given in any way acceptable for scanf's %d, +# i.e., octal (0[0-7]*), decimal ([1-9][0-9]*), or hexadecimal +# (0[xX][0-9a-fA-F]+). +# Strings must not be quoted and may not contain whitespace! +# +# Valid commands are: +# name +# Begin specification of device type , e.g. 18f6720. +# Aliases 'p' and 'pic' will be recognized as well. +# using +# Import specification from the named entry, which must be defined +# earlier. Later commands overrule imported ones. +# ramsize +# This device has bytes of RAM. +# split +# Addresses below refer to bank 0, addresses above +# refer to SFRs in bank 15 for references via the access bank. +# configrange +# Configuration registers occupy addresses to (both +# included). +# configword
[] +# The config word at address
only implements the bits +# indicated via (all others will be forced to 0 by the +# compiler). +# Unless overridden in C code, use the given default . +# The optional will be applied to the value just before +# emitting it into the .asm file (used to disable XINST by default). +# idlocrange +# ID locations occupy addresses to (both included). +# idword
+# Unless overridden in C code, use the given default . +# + +name 18f13k22 +ramsize 256 +split 0x60 +configrange 0x300001 0x30000D +configword 0x300001 0xFF 0x27 +configword 0x300002 0x1F 0x1F +configword 0x300003 0x1F 0x1F +configword 0x300005 0x88 0x88 +configword 0x300006 0xCD 0x85 0xBF +configword 0x300008 0x03 0x03 +configword 0x300009 0xC0 0xC0 +configword 0x30000A 0x03 0x03 +configword 0x30000B 0xE0 0xE0 +configword 0x30000C 0x03 0x03 +configword 0x30000D 0x40 0x40 +XINST 1 +idlocrange 0x200000 0x200007 + +name 18f13k50 +ramsize 512 +split 0x60 +configrange 0x300000 0x30000D +configword 0x300000 0x38 0x00 +configword 0x300001 0xFF 0x27 +configword 0x300002 0x1F 0x1F +configword 0x300003 0x1F 0x1F +configword 0x300005 0x88 0x88 +configword 0x300006 0xCD 0x85 0xBF +configword 0x300008 0x03 0x03 +configword 0x300009 0xC0 0xC0 +configword 0x30000A 0x03 0x03 +configword 0x30000B 0xE0 0xE0 +configword 0x30000C 0x03 0x03 +configword 0x30000D 0x40 0x40 +XINST 1 +idlocrange 0x200000 0x200007 + +name 18f14k22 +using 18f13k22 +ramsize 512 + +name 18f14k50 +using 18f13k50 +ramsize 768 + +name 18f23k20 +ramsize 512 +split 0x60 +configrange 0x300001 0x30000D +configword 0x300001 0xCF 0x07 +configword 0x300002 0x1F 0x1F +configword 0x300003 0x1F 0x1F +configword 0x300005 0x8F 0x8B +configword 0x300006 0xC5 0x85 0xBF +configword 0x300008 0x03 0x0F +configword 0x300009 0xC0 0xC0 +configword 0x30000A 0x03 0x0F +configword 0x30000B 0xE0 0xE0 +configword 0x30000C 0x03 0x0F +configword 0x30000D 0x40 0x40 +XINST 1 +idlocrange 0x200000 0x200007 + +name 18f23k22 +ramsize 512 +split 0x60 +configrange 0x300001 0x30000D +configword 0x300001 0xFF 0x25 +configword 0x300002 0x1F 0x1F +configword 0x300003 0x3F 0x3F +configword 0x300005 0xBF 0xBF +configword 0x300006 0xC5 0x85 0xBF +configword 0x300008 0x03 0x03 +configword 0x300009 0xC0 0xC0 +configword 0x30000A 0x03 0x03 +configword 0x30000B 0xE0 0xE0 +configword 0x30000C 0x03 0x03 +configword 0x30000D 0x40 0x40 +XINST 1 +idlocrange 0x200000 0x200007 + +name 18f24j10 +ramsize 1024 +split 0x80 +configrange 0x003FF8 0x003FFD +configword 0x003FF8 0xE1 0xFF 0xBF +configword 0x003FF9 0x04 0xF7 +configword 0x003FFA 0xC7 0xFF +configword 0x003FFB 0x0F 0xFF +configword 0x003FFD 0x01 0xFF +XINST 1 + +name 18f24j11 +ramsize 3776 +split 0x60 +configrange 0x003FF8 0x003FFF +configword 0x003FF8 0xE1 0xE1 0xBF +configword 0x003FF9 0x04 0xF4 +configword 0x003FFA 0xDF 0xDF +configword 0x003FFB 0x0F 0xFF +configword 0x003FFC 0xFF 0xFF +configword 0x003FFD 0x09 0xF9 +configword 0x003FFE 0xCF 0xCF +configword 0x003FFF 0x01 0xF1 +XINST 1 + +name 18f24j50 +using 18f24j11 +configword 0x003FF8 0x6F 0xEF 0xBF +configword 0x003FF9 0x07 0xF7 + +name 18f24k20 +using 18f23k20 +ramsize 768 + +name 18f24k22 +using 18f23k22 +ramsize 768 + +name 18f24k50 +ramsize 2048 +split 0x60 +configrange 0x300000 0x30000D +configword 0x300000 0x3B 0x00 +configword 0x300001 0xEF 0x25 +configword 0x300002 0x5F 0x5F +configword 0x300003 0x3F 0x3F +configword 0x300005 0xD3 0xD3 +configword 0x300006 0xE5 0xA5 0xBF +configword 0x300008 0x03 0x03 +configword 0x300009 0xC0 0xC0 +configword 0x30000A 0x03 0x03 +configword 0x30000B 0xE0 0xE0 +configword 0x30000C 0x03 0x03 +configword 0x30000D 0x40 0x40 +XINST 1 +idlocrange 0x200000 0x200007 + +name 18f25j10 +ramsize 1024 +split 0x80 +configrange 0x007FF8 0x007FFD +configword 0x007FF8 0xE1 0xFF 0xBF +configword 0x007FF9 0x04 0xF7 +configword 0x007FFA 0xC7 0xFF +configword 0x007FFB 0x0F 0xFF +configword 0x007FFD 0x01 0xFF +XINST 1 + +name 18f25j11 +ramsize 3776 +split 0x60 +configrange 0x007FF8 0x007FFF +configword 0x007FF8 0xE1 0xE1 0xBF +configword 0x007FF9 0x04 0xF4 +configword 0x007FFA 0xDF 0xDF +configword 0x007FFB 0x0F 0xFF +configword 0x007FFC 0xFF 0xFF +configword 0x007FFD 0x09 0xF9 +configword 0x007FFE 0xDF 0xDF +configword 0x007FFF 0x01 0xF1 +XINST 1 + +name 18f25j50 +using 18f25j11 +configword 0x007FF8 0x6F 0xEF 0xBF +configword 0x007FF9 0x07 0xF7 + +name 18f25k20 +using 18f23k20 +ramsize 1536 +configword 0x300008 0x0F 0x0F +configword 0x30000A 0x0F 0x0F +configword 0x30000C 0x0F 0x0F + +name 18f25k22 +using 18f23k22 +ramsize 1536 +configword 0x300008 0x0F 0x0F +configword 0x30000A 0x0F 0x0F +configword 0x30000C 0x0F 0x0F + +name 18f25k50 +using 18f24k50 +configword 0x300008 0x0F 0x0F +configword 0x30000A 0x0F 0x0F +configword 0x30000C 0x0F 0x0F + +name 18f25k80 +ramsize 3648 +split 0x60 +configrange 0x300000 0x30000D +configword 0x300000 0x5D 0x5D 0xBF +configword 0x300001 0xDF 0x08 +configword 0x300002 0x7F 0x7F +configword 0x300003 0x7F 0x7F +configword 0x300005 0x89 0x89 +configword 0x300006 0x11 0x91 +configword 0x300008 0x0F 0x0F +configword 0x300009 0xC0 0xC0 +configword 0x30000A 0x0F 0x0F +configword 0x30000B 0xE0 0xE0 +configword 0x30000C 0x0F 0x0F +configword 0x30000D 0x40 0x40 +XINST 1 +idlocrange 0x200000 0x200007 + +name 18f26j11 +ramsize 3776 +split 0x60 +configrange 0x00FFF8 0x00FFFF +configword 0x00FFF8 0xE1 0xE1 0xBF +configword 0x00FFF9 0x04 0xF4 +configword 0x00FFFA 0xDF 0xDF +configword 0x00FFFB 0x0F 0xFF +configword 0x00FFFC 0xFF 0xFF +configword 0x00FFFD 0x09 0xF9 +configword 0x00FFFE 0xFF 0xFF +configword 0x00FFFF 0x01 0xF1 +XINST 1 + +name 18f26j13 +ramsize 3760 +split 0x60 +configrange 0x00FFF8 0x00FFFF +configword 0x00FFF8 0x7F 0xFF 0xBF +configword 0x00FFF9 0x04 0xF4 +configword 0x00FFFA 0xFF 0xFF +configword 0x00FFFB 0x0F 0xFF +configword 0x00FFFC 0xFF 0xFF +configword 0x00FFFD 0x0F 0xFF +configword 0x00FFFE 0xBF 0xBF +configword 0x00FFFF 0x03 0xF3 +XINST 1 + +name 18f26j50 +using 18f26j11 +configword 0x00FFF8 0x6F 0xEF 0xBF +configword 0x00FFF9 0x07 0xF7 + +name 18f26j53 +using 18f26j13 +ramsize 3776 +configword 0x00FFF9 0x07 0xF7 +configword 0x00FFFD 0x0B 0xFB +configword 0x00FFFF 0x0B 0xFB + +name 18f26k20 +using 18f23k20 +ramsize 3936 +configword 0x300008 0x0F 0x0F +configword 0x30000A 0x0F 0x0F +configword 0x30000C 0x0F 0x0F + +name 18f26k22 +using 18f23k22 +ramsize 3936 +configword 0x300008 0x0F 0x0F +configword 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0xFF 0xFF +configword 0x30000A 0xFF 0xFF +configword 0x30000C 0xFF 0xFF + +name 18f6722 +using 18f6627 +configword 0x300008 0xFF 0xFF +configword 0x30000A 0xFF 0xFF +configword 0x30000C 0xFF 0xFF + +name 18f6723 +using 18f6627 +configword 0x300008 0xFF 0xFF +configword 0x30000A 0xFF 0xFF +configword 0x30000C 0xFF 0xFF + +name 18f8310 +using 18f6310 +configword 0x300004 0xC3 0xC3 +configword 0x30000C 0x01 0x01 + +name 18f8390 +using 18f6390 + +name 18f8393 +using 18f6390 + +name 18f8410 +using 18f6310 +configword 0x300004 0xC3 0xC3 +configword 0x30000C 0x01 0x01 + +name 18f8490 +using 18f6390 + +name 18f8493 +using 18f6390 + +name 18f8520 +using 18f6520 +configword 0x300004 0x83 0x83 + +name 18f8525 +using 18f6525 +configword 0x300004 0x83 0x83 +configword 0x300005 0x83 0x83 + +name 18f8527 +ramsize 3936 +split 0x60 +configrange 0x300001 0x30000D +configword 0x300001 0xCF 0x07 +configword 0x300002 0x1F 0x1F +configword 0x300003 0x1F 0x1F +configword 0x300004 0xF3 0xF3 +configword 0x300005 0x87 0x83 +configword 0x300006 0xF5 0x85 0xBF +configword 0x300008 0x07 0xFF +configword 0x300009 0xC0 0xC0 +configword 0x30000A 0x07 0xFF +configword 0x30000B 0xE0 0xE0 +configword 0x30000C 0x07 0xFF +configword 0x30000D 0x40 0x40 +XINST 1 +idlocrange 0x200000 0x200007 + +name 18f8585 +using 18f6525 +ramsize 3328 +configword 0x300004 0x83 0x83 +configword 0x300005 0x83 0x83 + +name 18f8620 +using 18f6520 +ramsize 3840 +configword 0x300004 0x83 0x83 + +name 18f8621 +ramsize 3840 +split 0x60 +configrange 0x300001 0x30000D +configword 0x300001 0x2F 0x2F +configword 0x300002 0x0F 0x0F +configword 0x300003 0x1F 0x1F +configword 0x300004 0x83 0x83 +configword 0x300005 0x83 0x83 +configword 0x300006 0x85 0x85 +configword 0x300008 0x0F 0x0F +configword 0x300009 0xC0 0xC0 +configword 0x30000A 0x0F 0x0F +configword 0x30000B 0xE0 0xE0 +configword 0x30000C 0x0F 0x0F +configword 0x30000D 0x40 0x40 +idlocrange 0x200000 0x200007 + +name 18f8622 +using 18f8527 +configword 0x300008 0x0F 0xFF +configword 0x30000A 0x0F 0xFF +configword 0x30000C 0x0F 0xFF + +name 18f8627 +using 18f8527 +configword 0x300008 0x3F 0xFF +configword 0x30000A 0x3F 0xFF +configword 0x30000C 0x3F 0xFF + +name 18f8628 +using 18f8527 +configword 0x300008 0x3F 0xFF +configword 0x30000A 0x3F 0xFF +configword 0x30000C 0x3F 0xFF + +name 18f8680 +using 18f8621 +ramsize 3328 + +name 18f8720 +ramsize 3840 +split 0x60 +configrange 0x300001 0x30000D +configword 0x300001 0x27 0x27 +configword 0x300002 0x0F 0x0F +configword 0x300003 0x0F 0x0F +configword 0x300004 0x83 0x83 +configword 0x300005 0x01 0x03 +configword 0x300006 0x85 0x85 +configword 0x300008 0xFF 0xFF +configword 0x300009 0xC0 0xC0 +configword 0x30000A 0xFF 0xFF +configword 0x30000B 0xE0 0xE0 +configword 0x30000C 0xFF 0xFF +configword 0x30000D 0x40 0x40 +idlocrange 0x200000 0x200007 + +name 18f8722 +using 18f8527 +configword 0x300008 0xFF 0xFF +configword 0x30000A 0xFF 0xFF +configword 0x30000C 0xFF 0xFF + +name 18f8723 +using 18f8527 +configword 0x300008 0xFF 0xFF +configword 0x30000A 0xFF 0xFF +configword 0x30000C 0xFF 0xFF + +name 18lf13k22 +using 18f13k22 + +name 18lf13k50 +using 18f13k50 + +name 18lf14k22 +using 18f13k22 +ramsize 512 + +name 18lf14k50 +using 18f13k50 +ramsize 768 + +name 18lf23k22 +using 18f23k22 + +name 18lf24j10 +using 18f24j10 + +name 18lf24j11 +using 18f24j11 + +name 18lf24j50 +using 18f24j11 +configword 0x003FF8 0x6F 0xEF 0xBF +configword 0x003FF9 0x07 0xF7 + +name 18lf24k22 +using 18f23k22 +ramsize 768 + +name 18lf24k50 +using 18f24k50 + +name 18lf25j10 +using 18f25j10 + +name 18lf25j11 +using 18f25j11 + +name 18lf25j50 +using 18f25j11 +configword 0x007FF8 0x6F 0xEF 0xBF +configword 0x007FF9 0x07 0xF7 + +name 18lf25k22 +using 18f23k22 +ramsize 1536 +configword 0x300008 0x0F 0x0F +configword 0x30000A 0x0F 0x0F +configword 0x30000C 0x0F 0x0F + +name 18lf25k50 +using 18f45k50 +configword 0x300006 0xE5 0xA5 0xBF + +name 18lf25k80 +using 18f25k80 + +name 18lf26j11 +using 18f26j11 + +name 18lf26j13 +using 18f26j13 + +name 18lf26j50 +using 18f26j11 +configword 0x00FFF8 0x6F 0xEF 0xBF +configword 0x00FFF9 0x07 0xF7 + +name 18lf26j53 +using 18f26j13 +ramsize 3776 +configword 0x00FFF9 0x07 0xF7 +configword 0x00FFFD 0x0B 0xFB +configword 0x00FFFF 0x0B 0xFB + +name 18lf26k22 +using 18f23k22 +ramsize 3936 +configword 0x300008 0x0F 0x0F +configword 0x30000A 0x0F 0x0F +configword 0x30000C 0x0F 0x0F + +name 18lf26k80 +using 18f25k80 + +name 18lf27j13 +using 18f27j13 + +name 18lf27j53 +using 18f27j13 +ramsize 3776 +configword 0x01FFF9 0x07 0xF7 +configword 0x01FFFD 0x0B 0xFB +configword 0x01FFFF 0x0B 0xFB + +name 18lf43k22 +using 18f23k22 + +name 18lf44j10 +using 18f24j10 + +name 18lf44j11 +using 18f24j11 + +name 18lf44j50 +using 18f24j11 +configword 0x003FF8 0x6F 0xEF 0xBF +configword 0x003FF9 0x07 0xF7 + +name 18lf44k22 +using 18f23k22 +ramsize 768 + +name 18lf45j10 +using 18f25j10 + +name 18lf45j11 +using 18f25j11 + +name 18lf45j50 +using 18f25j11 +configword 0x007FF8 0x6F 0xEF 0xBF +configword 0x007FF9 0x07 0xF7 + +name 18lf45k22 +using 18f23k22 +ramsize 1536 +configword 0x300008 0x0F 0x0F +configword 0x30000A 0x0F 0x0F +configword 0x30000C 0x0F 0x0F + +name 18lf45k50 +using 18f45k50 + +name 18lf45k80 +using 18f25k80 + +name 18lf46j11 +using 18f26j11 + +name 18lf46j13 +using 18f26j13 + +name 18lf46j50 +using 18f26j11 +configword 0x00FFF8 0x6F 0xEF 0xBF +configword 0x00FFF9 0x07 0xF7 + +name 18lf46j53 +using 18f26j13 +ramsize 3776 +configword 0x00FFF9 0x07 0xF7 +configword 0x00FFFD 0x0B 0xFB +configword 0x00FFFF 0x0B 0xFB + +name 18lf46k22 +using 18f23k22 +ramsize 3936 +configword 0x300008 0x0F 0x0F +configword 0x30000A 0x0F 0x0F +configword 0x30000C 0x0F 0x0F + +name 18lf46k80 +using 18f25k80 + +name 18lf47j13 +using 18f27j13 + +name 18lf47j53 +using 18f27j13 +ramsize 3776 +configword 0x01FFF9 0x07 0xF7 +configword 0x01FFFD 0x0B 0xFB +configword 0x01FFFF 0x0B 0xFB + +name 18lf65k80 +using 18f25k80 +configword 0x300005 0x8F 0x8F + +name 18lf66k80 +using 18f25k80 +configword 0x300005 0x8F 0x8F + +name 18lf242 +using 18f242 + +name 18lf248 +using 18f248 + +name 18lf252 +using 18f242 +ramsize 1536 +configword 0x300008 0x0F 0x0F +configword 0x30000A 0x0F 0x0F +configword 0x30000C 0x0F 0x0F + +name 18lf258 +using 18f248 +ramsize 1536 +configword 0x300008 0x0F 0x0F +configword 0x30000A 0x0F 0x0F +configword 0x30000C 0x0F 0x0F + +name 18lf442 +using 18f242 + +name 18lf448 +using 18f248 + +name 18lf452 +using 18f242 +ramsize 1536 +configword 0x300008 0x0F 0x0F +configword 0x30000A 0x0F 0x0F +configword 0x30000C 0x0F 0x0F + +name 18lf458 +using 18f248 +ramsize 1536 +configword 0x300008 0x0F 0x0F +configword 0x30000A 0x0F 0x0F +configword 0x30000C 0x0F 0x0F + +name 18lf1220 +using 18f1220 + +name 18lf1230 +using 18f1230 + +name 18lf1320 +using 18f1220 + +name 18lf1330 +using 18f1230 + +name 18lf2220 +using 18f2320 +configword 0x300008 0x03 0x0F +configword 0x30000A 0x03 0x0F +configword 0x30000C 0x03 0x0F + +name 18lf2221 +using 18f13k22 +ramsize 512 +split 0x80 +configword 0x300001 0xCF 0x07 +configword 0x300005 0x87 0x83 +configword 0x300006 0xF5 0x85 0xBF + +name 18lf2320 +using 18f2320 + +name 18lf2321 +using 18f13k22 +ramsize 512 +split 0x80 +configword 0x300001 0xCF 0x07 +configword 0x300005 0x87 0x83 +configword 0x300006 0xF5 0x85 0xBF + +name 18lf2331 +using 18f2331 + +name 18lf2410 +using 18f23k20 +ramsize 768 +split 0x80 +configword 0x300005 0x87 0x83 +configword 0x300009 0x40 0x40 +configword 0x30000B 0x60 0x60 + +name 18lf2420 +using 18f23k20 +ramsize 768 +split 0x80 +configword 0x300005 0x87 0x83 + +name 18lf2423 +using 18f23k20 +ramsize 768 +split 0x80 +configword 0x300005 0x87 0x83 + +name 18lf2431 +using 18f4431 +configword 0x300005 0x80 0x9D + +name 18lf2439 +using 18f248 +ramsize 640 +split 0x80 +configword 0x300001 0x07 0x22 + +name 18lf2450 +# 0x200..0x3FF is not implemented, but we leave that to the linker ;-) +using 18f2450 + +name 18lf2455 +using 18f2455 + +name 18lf2458 +using 18f2455 + +name 18lf2480 +using 18f23k20 +ramsize 768 +configword 0x300005 0x86 0x82 +configword 0x300006 0xD5 0x85 0xBF + +name 18lf2510 +using 18f2510 + +name 18lf2515 +using 18f2525 +configword 0x300009 0x40 0x40 +configword 0x30000B 0x60 0x60 + +name 18lf2520 +using 18f2510 +configword 0x300009 0xC0 0xC0 +configword 0x30000B 0xE0 0xE0 + +name 18lf2523 +using 18f2510 +configword 0x300009 0xC0 0xC0 +configword 0x30000B 0xE0 0xE0 + +name 18lf2525 +using 18f2525 + +name 18lf2539 +using 18f2539 + +name 18lf2550 +using 18f4550 +configword 0x300006 0xC5 0x85 0xBF + +name 18lf2553 +using 18f4550 +configword 0x300006 0xC5 0x85 0xBF + +name 18lf2580 +using 18f2580 + +name 18lf2585 +using 18f2525 +split 0x60 +configword 0x300005 0x86 0x82 +configword 0x300006 0xF5 0x85 0xBF + +name 18lf2610 +using 18f2510 +ramsize 4096 + +name 18lf2620 +using 18f2510 +ramsize 4096 +configword 0x300009 0xC0 0xC0 +configword 0x30000B 0xE0 0xE0 + +name 18lf2680 +using 18f2580 +ramsize 4096 +configword 0x300006 0xF5 0x85 0xBF + +name 18lf2682 +using 18f2682 + +name 18lf2685 +using 18f2682 +configword 0x300008 0x3F 0x3F +configword 0x30000A 0x3F 0x3F +configword 0x30000C 0x3F 0x3F + +name 18lf4220 +using 18f2320 +configword 0x300008 0x03 0x0F +configword 0x30000A 0x03 0x0F +configword 0x30000C 0x03 0x0F + +name 18lf4221 +using 18f13k22 +ramsize 512 +split 0x80 +configword 0x300001 0xCF 0x07 +configword 0x300005 0x87 0x83 +configword 0x300006 0xF5 0x85 0xBF + +name 18lf4320 +using 18f2320 + +name 18lf4321 +using 18f13k22 +ramsize 512 +split 0x80 +configword 0x300001 0xCF 0x07 +configword 0x300005 0x87 0x83 +configword 0x300006 0xF5 0x85 0xBF + +name 18lf4331 +using 18f2331 +configword 0x300005 0x9D 0x9D + +name 18lf4410 +using 18f23k20 +ramsize 768 +split 0x80 +configword 0x300005 0x87 0x83 +configword 0x300009 0x40 0x40 +configword 0x30000B 0x60 0x60 + +name 18lf4420 +using 18f23k20 +ramsize 768 +split 0x80 +configword 0x300005 0x87 0x83 + +name 18lf4423 +using 18f23k20 +ramsize 768 +split 0x80 +configword 0x300005 0x87 0x83 + +name 18lf4431 +using 18f4431 + +name 18lf4439 +using 18f248 +ramsize 640 +split 0x80 +configword 0x300001 0x07 0x22 + +name 18lf4450 +using 18f2450 +configword 0x300006 0xED 0x85 0xBF + +name 18lf4455 +using 18f2455 +configword 0x300006 0xE5 0x85 0xBF + +name 18lf4458 +using 18f2455 +configword 0x300006 0xE5 0x85 0xBF + +name 18lf4480 +using 18f23k20 +ramsize 768 +configword 0x300005 0x86 0x82 +configword 0x300006 0xD5 0x85 0xBF + +name 18lf4510 +using 18f2510 + +name 18lf4515 +using 18f2525 +configword 0x300009 0x40 0x40 +configword 0x30000B 0x60 0x60 + +name 18lf4520 +using 18f2510 +configword 0x300009 0xC0 0xC0 +configword 0x30000B 0xE0 0xE0 + +name 18lf4523 +using 18f2510 +configword 0x300009 0xC0 0xC0 +configword 0x30000B 0xE0 0xE0 + +name 18lf4525 +using 18f2525 + +name 18lf4539 +using 18f2539 + +name 18lf4550 +using 18f4550 + +name 18lf4553 +using 18f4550 + +name 18lf4580 +using 18f2580 + +name 18lf4585 +using 18f2525 +split 0x60 +configword 0x300005 0x86 0x82 +configword 0x300006 0xF5 0x85 0xBF + +name 18lf4610 +using 18f2510 +ramsize 4096 + +name 18lf4620 +using 18f2510 +ramsize 4096 +configword 0x300009 0xC0 0xC0 +configword 0x30000B 0xE0 0xE0 + +name 18lf4680 +using 18f2580 +ramsize 4096 +configword 0x300006 0xF5 0x85 0xBF + +name 18lf4682 +using 18f2682 + +name 18lf4685 +using 18f2682 +configword 0x300008 0x3F 0x3F +configword 0x30000A 0x3F 0x3F +configword 0x30000C 0x3F 0x3F + +name 18lf6310 +using 18f6310 + +name 18lf6390 +using 18f6390 + +name 18lf6393 +using 18f6390 + +name 18lf6410 +using 18f6310 + +name 18lf6490 +using 18f6390 + +name 18lf6493 +using 18f6390 + +name 18lf6520 +using 18f6520 + +name 18lf6525 +using 18f6525 + +name 18lf6527 +using 18f6527 + +name 18lf6585 +using 18f6525 +ramsize 3328 + +name 18lf6620 +using 18f6520 +ramsize 3840 + +name 18lf6621 +using 18f8621 +configword 0x300004 0x00 0x83 +configword 0x300005 0x81 0x83 + +name 18lf6622 +using 18f6527 +configword 0x300008 0x0F 0xFF +configword 0x30000A 0x0F 0xFF +configword 0x30000C 0x0F 0xFF + +name 18lf6627 +using 18f6627 + +name 18lf6628 +using 18f6627 + +name 18lf6680 +using 18f8621 +ramsize 3328 +configword 0x300004 0x00 0x83 +configword 0x300005 0x81 0x83 + +name 18lf6720 +using 18f8720 +configword 0x300004 0x00 0x83 + +name 18lf6722 +using 18f6627 +configword 0x300008 0xFF 0xFF +configword 0x30000A 0xFF 0xFF +configword 0x30000C 0xFF 0xFF + +name 18lf6723 +using 18f6627 +configword 0x300008 0xFF 0xFF +configword 0x30000A 0xFF 0xFF +configword 0x30000C 0xFF 0xFF + +name 18lf8310 +using 18f6310 +configword 0x300004 0xC3 0xC3 +configword 0x30000C 0x01 0x01 + +name 18lf8390 +using 18f6390 + +name 18lf8393 +using 18f6390 + +name 18lf8410 +using 18f6310 +configword 0x300004 0xC3 0xC3 +configword 0x30000C 0x01 0x01 + +name 18lf8490 +using 18f6390 + +name 18lf8493 +using 18f6390 + +name 18lf8520 +using 18f6520 +configword 0x300004 0x83 0x83 + +name 18lf8525 +using 18f6525 +configword 0x300004 0x83 0x83 +configword 0x300005 0x83 0x83 + +name 18lf8527 +using 18f8527 + +name 18lf8585 +using 18f6525 +ramsize 3328 +configword 0x300004 0x83 0x83 +configword 0x300005 0x83 0x83 + +name 18lf8620 +using 18f6520 +ramsize 3840 +configword 0x300004 0x83 0x83 + +name 18lf8621 +using 18f8621 + +name 18lf8622 +using 18f8527 +configword 0x300008 0x0F 0xFF +configword 0x30000A 0x0F 0xFF +configword 0x30000C 0x0F 0xFF + +name 18lf8627 +using 18f8527 +configword 0x300008 0x3F 0xFF +configword 0x30000A 0x3F 0xFF +configword 0x30000C 0x3F 0xFF + +name 18lf8628 +using 18f8527 +configword 0x300008 0x3F 0xFF +configword 0x30000A 0x3F 0xFF +configword 0x30000C 0x3F 0xFF + +name 18lf8680 +using 18f8621 +ramsize 3328 + +name 18lf8720 +using 18f8720 + +name 18lf8722 +using 18f8527 +configword 0x300008 0xFF 0xFF +configword 0x30000A 0xFF 0xFF +configword 0x30000C 0xFF 0xFF + +name 18lf8723 +using 18f8527 +configword 0x300008 0xFF 0xFF +configword 0x30000A 0xFF 0xFF +configword 0x30000C 0xFF 0xFF /*------------------------------------------------------------------------- serial390.h @@ -2083,8 +8629,6 @@ typedef unsigned char __data * va_list; /* Register allocator is as good as hand coded asm. Cool. */ #define _SDCC_PORT_PROVIDES_STRCPY 0 -#define _SDCC_MALLOC_TYPE_MLH 1 - #endif /*------------------------------------------------------------------------- @@ -2176,8 +8720,6 @@ typedef unsigned char __data * va_list; /* Register allocator is as good as hand coded asm. Cool. */ #define _SDCC_PORT_PROVIDES_STRCPY 0 -#define _SDCC_MALLOC_TYPE_MLH 1 - #endif /*------------------------------------------------------------------------- @@ -2383,8 +8925,6 @@ typedef unsigned char __data * va_list; #define _SDCC_PORT_PROVIDES_STRCMP 0 #define _SDCC_PORT_PROVIDES_STRCPY 0 -#define _SDCC_MALLOC_TYPE_MLH 1 - #endif /*------------------------------------------------------------------------- @@ -2433,8 +8973,6 @@ typedef unsigned char __data * va_list; /* Register allocator is as good as hand coded asm. Cool. */ #define _SDCC_PORT_PROVIDES_STRCPY 0 -#define _SDCC_MALLOC_TYPE_MLH 1 - #endif /*------------------------------------------------------------------------- @@ -2527,8 +9065,6 @@ typedef unsigned char __data * va_list; /* Register allocator is as good as hand coded asm. Cool. */ #define _SDCC_PORT_PROVIDES_STRCPY 0 -#define _SDCC_MALLOC_TYPE_MLH 1 - #endif /*------------------------------------------------------------------------- features.h - Z80 specific features. @@ -2576,8 +9112,6 @@ typedef unsigned char __data * va_list; /* Register allocator is as good as hand coded asm. Cool. */ #define _SDCC_PORT_PROVIDES_STRCPY 0 -#define _SDCC_MALLOC_TYPE_MLH 1 - #endif /*------------------------------------------------------------------------- @@ -2626,10 +9160,233 @@ typedef unsigned char __data * va_list; /* Register allocator is as good as hand coded asm. Cool. */ #define _SDCC_PORT_PROVIDES_STRCPY 0 -#define _SDCC_MALLOC_TYPE_MLH 1 - #endif +/* + * XA G3 SFR definitions + * Extracted directly from Philips documentation + */ + +#ifndef XA_H +#define XA_H + +__sfr __at 0x400 /*unsigned short*/ PSW; /* Program status word */ +__sfr __at 0x400 PSWL; /* Program status word (low byte) */ +__sfr __at 0x401 PSWH; /* Program status word (high byte) */ +__sfr __at 0x402 PSW51; /* 80C51 compatible PSW */ +__sfr __at 0x403 SSEL; /* Segment selection register */ +__sfr __at 0x404 PCON; /* Power control register */ +__sfr __at 0x410 TCON; /* Timer 0 and 1 control register */ +__sfr __at 0x411 TSTAT; /* Timer 0 and 1 extended status */ +__sfr __at 0x418 T2CON; /* Timer 2 control register */ +__sfr __at 0x419 T2MOD; /* Timer 2 mode control */ +__sfr __at 0x41F WDCON; /* Watchdog control register */ +__sfr __at 0x420 S0CON; /* Serial port 0 control register */ +__sfr __at 0x421 S0STAT; /* Serial port 0 extended status */ +__sfr __at 0x424 S1CON; /* Serial port 1 control register */ +__sfr __at 0x425 S1STAT; /* Serial port 1 extended status */ +__sfr __at 0x426 IEL; /* Interrupt enable low byte */ +__sfr __at 0x427 IEH; /* Interrupt enable high byte */ +__sfr __at 0x42A SWR; /* Software Interrupt Request */ +__sfr __at 0x430 P0; /* Port 0 */ +__sfr __at 0x431 P1; /* Port 1 */ +__sfr __at 0x432 P2; /* Port 2 */ +__sfr __at 0x433 P3; /* Port3 */ +__sfr __at 0x440 SCR; /* System configuration register */ +__sfr __at 0x441 DS; /* Data segment */ +__sfr __at 0x442 ES; /* Extra segment */ +__sfr __at 0x443 CS; /* Code segment */ +__sfr __at 0x450 TL0; /* Timer 0 low byte */ +__sfr __at 0x451 TH0; /* Timer 0 high byte */ +__sfr __at 0x452 TL1; /* Timer 1 low byte */ +__sfr __at 0x453 TH1; /* Timer 1 high byte */ +__sfr __at 0x454 RTL0; /* Timer 0 extended reload, low byte */ +__sfr __at 0x455 RTH0; /* Timer 0 extended reload, high byte */ +__sfr __at 0x456 RTL1; /* Timer 1 extended reload, low byte */ +__sfr __at 0x457 RTH1; /* Timer 1 extended reload, high byte */ +__sfr __at 0x458 TL2; /* Timer 2 low byte */ +__sfr __at 0x459 TH2; /* Timer 2 high byte */ +__sfr __at 0x45A T2CAPL; /* Timer 2 capture register, low byte */ +__sfr __at 0x45B T2CAPH; /* Timer 2 capture register, high byte */ +__sfr __at 0x45C TMOD; /* Timer 0 and 1 mode register */ +__sfr __at 0x45D WFEED1; /* Watchdog feed 1 */ +__sfr __at 0x45E WFEED2; /* Watchdog feed 2 */ +__sfr __at 0x45F WDL; /* Watchdog timer reload */ +__sfr __at 0x460 S0BUF; /* Serial port 0 buffer register */ +__sfr __at 0x461 S0ADDR; /* Serial port 0 address register */ +__sfr __at 0x462 S0ADEN; /* Serial port 0 address enable register */ +__sfr __at 0x464 S1BUF; /* Serial port 1 buffer register */ +__sfr __at 0x465 S1ADDR; /* Serial port 1 address register */ +__sfr __at 0x466 S1ADEN; /* Serial port 1 address enable register */ +__sfr __at 0x468 BTRL; /* Bus timing register high byte */ +__sfr __at 0x469 BTRH; /* Bus timing register low byte */ +__sfr __at 0x46A BCR; /* Bus configuration register */ +__sfr __at 0x470 P0CFGA; /* Port 0 configuration A */ +__sfr __at 0x471 P1CFGA; /* Port 1 configuration A */ +__sfr __at 0x472 P2CFGA; /* Port 2 configuration A */ +__sfr __at 0x473 P3CFGA; /* Port 3 configuration A */ +__sfr __at 0x47A SWE; /* Software Interrupt Enable */ +__sfr __at 0x4A0 IPA0; /* Interrupt priority 0 */ +__sfr __at 0x4A1 IPA1; /* Interrupt priority 1 */ +__sfr __at 0x4A2 IPA2; /* Interrupt priority 2 */ +__sfr __at 0x4A4 IPA4; /* Interrupt priority 4 */ +__sfr __at 0x4A5 IPA5; /* Interrupt priority 5 */ +__sfr __at 0x4F0 P0CFGB; /* Port 0 configuration B */ +__sfr __at 0x4F1 P1CFGB; /* Port 1 configuration B */ +__sfr __at 0x4F2 P2CFGB; /* Port 2 configuration B */ +__sfr __at 0x4F3 P3CFGB; /* Port 3 configuration B */ + +__sbit __at 0x33B ETI1; /* TX interrupt enable 1 */ +__sbit __at 0x33A ERI1; /* RX interrupt enable 1 */ +__sbit __at 0x339 ETI0; /* TX interrupt enable 0 */ +__sbit __at 0x338 ERI0; /* RX interrupt enable 0 */ +__sbit __at 0x337 EA; /* global int. enable */ +__sbit __at 0x334 ET2; /* timer 2 interrupt */ +__sbit __at 0x333 ET1; /* timer 1 interrupt */ +__sbit __at 0x332 EX1; /* external interrupt 1 */ +__sbit __at 0x331 ET0; /* timer 0 interrupt */ +__sbit __at 0x330 EX0; /* external interrupt 0 */ +__sbit __at 0x221 PD; /* power down */ +__sbit __at 0x220 IDL; +__sbit __at 0x20F SM; +__sbit __at 0x20E TM; +__sbit __at 0x20D RS1; +__sbit __at 0x20C RS0; +__sbit __at 0x20B IM3; +__sbit __at 0x20A IM2; +__sbit __at 0x209 IM1; +__sbit __at 0x208 IM0; +__sbit __at 0x307 S0M0; +__sbit __at 0x306 S0M1; +__sbit __at 0x305 S0M2; +__sbit __at 0x304 R0EN; +__sbit __at 0x303 T0B8; +__sbit __at 0x302 R0B8; +__sbit __at 0x301 TI0; /* serial port 0 tx ready */ +__sbit __at 0x300 RI0; /* serial port 0 rx ready */ +__sbit __at 0x30B FE0; +__sbit __at 0x30A BR0; +__sbit __at 0x309 OE0; +__sbit __at 0x308 STINT0; +__sbit __at 0x327 S1M0; +__sbit __at 0x326 S1M1; +__sbit __at 0x325 S1M2; +__sbit __at 0x324 R1EN; +__sbit __at 0x323 T1B8; +__sbit __at 0x322 R1B8; +__sbit __at 0x321 TI1; /* serial port 0 tx ready */ +__sbit __at 0x320 RI1; /* serial port 0 rx ready */ +__sbit __at 0x32B FE1; +__sbit __at 0x32A BR1; +__sbit __at 0x329 OE1; +__sbit __at 0x328 STINT1; +__sbit __at 0x356 SWR7; +__sbit __at 0x355 SWR6; +__sbit __at 0x354 SWR5; +__sbit __at 0x353 SWR4; +__sbit __at 0x352 SWR3; +__sbit __at 0x351 SWR2; +__sbit __at 0x350 SWR1; +__sbit __at 0x2C7 TF2; +__sbit __at 0x2C6 EXF2; +__sbit __at 0x2C5 RCLK0; +__sbit __at 0x2C4 TCLK0; +__sbit __at 0x2CD RCLK1; +__sbit __at 0x2CC TCLK1; +__sbit __at 0x2C3 EXEN2; +__sbit __at 0x2C2 TR2; +__sbit __at 0x2C1 CT2; +__sbit __at 0x2C0 CPRL2; +__sbit __at 0x2C9 T2OE; +__sbit __at 0x2C8 DCEN; +__sbit __at 0x287 TF1; +__sbit __at 0x286 TR1; +__sbit __at 0x285 TF0; +__sbit __at 0x284 TR0; +__sbit __at 0x283 IE1; +__sbit __at 0x282 IT1; +__sbit __at 0x281 IE0; +__sbit __at 0x280 IT0; +__sbit __at 0x28A T1OE; +__sbit __at 0x288 T0OE; +__sbit __at 0x2FF PRE2; +__sbit __at 0x2FE PRE1; +__sbit __at 0x2FD PRE0; +__sbit __at 0x2FA WDRUN; +__sbit __at 0x2F9 WDTOF; +__sbit __at 0x2F8 WDMOD; +__sbit __at 0x388 WR1; +__sbit __at 0x38F T2EX; +__sbit __at 0x38C RXD1; +__sbit __at 0x38D TXD1; +__sbit __at 0x398 RXD0; +__sbit __at 0x399 TXD0; +__sbit __at 0x39A INT0; +__sbit __at 0x39B INT1; +__sbit __at 0x39C T0; +__sbit __at 0x39D T1; +__sbit __at 0x39E WR; +__sbit __at 0x39F RD; + +/* + * Interrupt stuff + */ + + +/* Vectors */ + +#define IV_BRKPT 0x04 /* breakpoint vector */ +#define IV_TRACE 0x08 /* Trace mode bit set */ +#define IV_STKOVER 0x0C /* stack overflow */ +#define IV_DIVZERO 0x10 /* divide by zero */ +#define IV_IRET 0x14 /* user mode IRET */ + +#define IV_EX0 0x80 +#define IV_T0 0x84 +#define IV_EX1 0x88 +#define IV_T1 0x8C +#define IV_T2 0x90 +#define IV_RI0 0xA0 +#define IV_TI0 0xA4 +#define IV_RI1 0xA8 +#define IV_TI1 0xAC +#define IV_SWI1 0x100 /* software interrupts */ +#define IV_SWI2 0x104 +#define IV_SWI3 0x108 +#define IV_SWI4 0x10C +#define IV_SWI5 0x110 +#define IV_SWI6 0x114 +#define IV_SWI7 0x118 + +/* PSW Values for interrupt vectors */ + +#define IV_PSW 0x8F00 /* System mode, high priority, bank 0 */ + +#define IV_SYSTEM 0x8000 + +#define IV_PRI00 0x0000 /* priorities 0 - 15 */ +#define IV_PRI01 0x0100 +#define IV_PRI02 0x0200 +#define IV_PRI03 0x0300 +#define IV_PRI04 0x0400 +#define IV_PRI05 0x0500 +#define IV_PRI06 0x0600 +#define IV_PRI07 0x0700 +#define IV_PRI08 0x0800 +#define IV_PRI09 0x0900 +#define IV_PRI10 0x0A00 +#define IV_PRI11 0x0B00 +#define IV_PRI12 0x0C00 +#define IV_PRI13 0x0D00 +#define IV_PRI14 0x0E00 +#define IV_PRI15 0x0F00 + +#define IV_BANK0 0x0000 +#define IV_BANK1 0x1000 +#define IV_BANK2 0x2000 +#define IV_BANK3 0x3000 + +#endif /* XA_H */ /*------------------------------------------------------------------------- at89x051.h - Register Declarations for Atmel AT89C1051, AT89C2051 and AT89C4051 Processors based on 8051.h (8051.h must be in mcs51 subdirectory) @@ -8065,6 +14822,2597 @@ SFRX(X_P1DIR, 0xDFFE); // Port 1 Direction SFRX(X_P2DIR, 0xDFFF); // Port 2 Direction #endif //REG_CC2430_H +/*------------------------------------------------------------------------- + * EFM8BB1.h - Register Declarations for the SiLabs EFM8BB1 Processor + * Range + * + * Copyright (C) 2015, Kharitonov Dmitriy, kharpost@altlinux.org + * + * This library is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2, or (at your option) any + * later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this library; see the file COPYING. If not, write to the + * Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + * + * As a special exception, if you link this library with other files, + * some of which are compiled with SDCC, to produce an executable, + * this library does not by itself cause the resulting executable to + * be covered by the GNU General Public License. This exception does + * not however invalidate any other reasons why the executable file + * might be covered by the GNU General Public License. + * -------------------------------------------------------------------------*/ +#ifndef EFM8BB1_H +#define EFM8BB1_H + +/* Supported Devices: + EFM8BB10F2G + EFM8BB10F4G + EFM8BB10F8G +*/ + +#include + +/* BYTE Registers */ + +SFR( P0, 0x80 ); /* PORT 0 */ +SFR( SP, 0x81 ); /* STACK POINTER */ +SFR( DPL, 0x82 ); /* DATA POINTER - LOW BYTE */ +SFR( DPH, 0x83 ); /* DATA POINTER - HIGH BYTE */ +SFR( PCON0, 0x87 ); /* POWER CONTROL */ +SFR( TCON, 0x88 ); /* TIMER CONTROL */ +SFR( TMOD, 0x89 ); /* TIMER MODE */ +SFR( TL0, 0x8A ); /* TIMER 0 - LOW BYTE */ +SFR( TL1, 0x8B ); /* TIMER 1 - LOW BYTE */ +SFR( TH0, 0x8C ); /* TIMER 0 - HIGH BYTE */ +SFR( TH1, 0x8D ); /* TIMER 1 - HIGH BYTE */ +SFR( CKCON0, 0x8E ); /* CLOCK CONTROL */ +SFR( PSCTL, 0x8F ); /* PROGRAM STORE R/W CONTROL */ +SFR( P1, 0x90 ); /* PORT 1 */ +SFR( TMR3CN0, 0x91 ); /* TIMER 3 CONTROL */ +SFR( TMR3RLL, 0x92 ); /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ +SFR( TMR3RLH, 0x93 ); /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ +SFR( TMR3L, 0x94 ); /* TIMER 3 - LOW BYTE */ +SFR( TMR3H, 0x95 ); /* TIMER 3 - HIGH BYTE */ +SFR( PCA0POL, 0x96 ); /* PCA Output Polarity */ +SFR( WDTCN, 0x97 ); /* Watchdog Timer Control*/ +SFR( SCON0, 0x98 ); /* SERIAL PORT CONTROL */ +SFR( SBUF0, 0x99 ); /* SERIAL PORT BUFFER */ +SFR( CMP0CN0, 0x9B ); /* COMPARATOR 0 CONTROL 0 */ +SFR( PCA0CLR, 0x9C ); /* PCA Comparator Clear Control */ +SFR( CMP0MD, 0x9D ); /* Comparator 0 Mode */ +SFR( PCA0CENT, 0x9E ); /* PCA Center Alignment Enable */ +SFR( CMP0MX, 0x9F ); /* Comparator 0 Multiplexer Selection */ +SFR( P2, 0xA0 ); /* PORT 2 */ +SFR( SPI0CFG, 0xA1 ); /* SPI0 CONFIGURATION */ +SFR( SPI0CKR, 0xA2 ); /* SPI0 CLOCK RATE CONTROL */ +SFR( SPI0DAT, 0xA3 ); /* SPI0 DATA */ +SFR( P0MDOUT, 0xA4 ); /* PORT 0 OUTPUT MODE CONFIGURATION */ +SFR( P1MDOUT, 0xA5 ); /* PORT 1 OUTPUT MODE CONFIGURATION */ +SFR( P2MDOUT, 0xA6 ); /* PORT 2 OUTPUT MODE CONFIGURATION */ +SFR( IE, 0xA8 ); /* INTERRUPT ENABLE */ +SFR( CLKSEL, 0xA9 ); /* SYSTEM CLOCK SELECT */ +SFR( CMP1MX, 0xAA ); /* Comparator 1 Multiplexer Selection */ +SFR( CMP1MD, 0xAB ); /* Comparator 1 Mode */ +SFR( SMB0TC, 0xAC ); /* SMBus 0 Timing and Pin Control */ +SFR( DERIVID, 0xAD ); /* Derivative Identification */ +SFR( LFO0CN, 0xB1 ); /* Low Frequency Oscillator Control */ +SFR( ADC0CN1, 0xB2 ); /* ADC0 Control 1 */ +SFR( ADC0AC, 0xB3 ); /* ADC0 Accumulator Configuration */ +SFR( C2FPDAT, 0xB4 ); /* C2 Flash Programming Data */ +SFR( DEVICEID, 0xB5 ); /* Device Identification */ +SFR( REVID, 0xB6 ); /* Revision Identifcation */ +SFR( FLKEY, 0xB7 ); /* Flash Lock and Key */ +SFR( IP, 0xB8 ); /* INTERRUPT PRIORITY */ +SFR( ADC0TK, 0xB9 ); /* ADC0 Burst Mode Track Time */ +SFR( ADC0MX, 0xBB ); /* ADC0 Multiplexer Selection */ +SFR( ADC0CF, 0xBC ); /* ADC 0 CONFIGURATION */ +SFR( ADC0L, 0xBD ); /* ADC 0 DATA WORD LSB */ +SFR( ADC0H, 0xBE ); /* ADC 0 DATA WORD MSB */ +SFR( CMP1CN0, 0xBF ); /* Comparator 1 Control 0 */ +SFR( SMB0CN0, 0xC0 ); /* SMBUS CONTROL */ +SFR( SMB0CF, 0xC1 ); /* SMBUS CONFIGURATION */ +SFR( SMB0DAT, 0xC2 ); /* SMBUS DATA */ +SFR( ADC0GTL, 0xC3 ); /* ADC 0 GREATER-THAN LOW BYTE */ +SFR( ADC0GTH, 0xC4 ); /* ADC 0 GREATER-THAN HIGH BYTE */ +SFR( ADC0LTL, 0xC5 ); /* ADC 0 LESS-THAN LOW BYTE */ +SFR( ADC0LTH, 0xC6 ); /* ADC 0 LESS-THAN HIGH BYTE */ +SFR( HFO0CAL, 0xC7 ); /* High Frequency Oscillator 0 Calibration */ +SFR( TMR2CN0, 0xC8 ); /* TIMER 2 CONTROL */ +SFR( REG0CN, 0xC9 ); /* TIMER 2 CONTROL */ +SFR( TMR2RLL, 0xCA ); /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +SFR( TMR2RLH, 0xCB ); /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +SFR( TMR2L, 0xCC ); /* TIMER 2 - LOW BYTE */ +SFR( TMR2H, 0xCD ); /* TIMER 2 - HIGH BYTE */ +SFR( CRC0CN0, 0xCE ); /* CRC0 Control 0 */ +SFR( CRC0FLIP, 0xCF ); /* CRC0 Bit Flip */ +SFR( PSW, 0xD0 ); /* PROGRAM STATUS WORD */ +SFR( REF0CN, 0xD1 ); /* VOLTAGE REFERENCE 0 CONTROL */ +SFR( CRC0AUTO, 0xD2 ); /* CRC0 Automatic Control */ +SFR( CRC0CNT, 0xD3 ); /* CRC0 Automatic Flash Sector Count */ +SFR( P0SKIP, 0xD4 ); /* PORT 0 SKIP */ +SFR( P1SKIP, 0xD5 ); /* PORT 1 SKIP */ +SFR( SMB0ADM, 0xD6 ); /* SMBus 0 Slave Address Mask */ +SFR( SMB0ADR, 0xD7 ); /* SMBus 0 Slave Address */ +SFR( PCA0CN0, 0xD8 ); /* PCA CONTROL */ +SFR( PCA0MD, 0xD9 ); /* PCA MODE */ +SFR( PCA0CPM0, 0xDA ); /* PCA MODULE 0 MODE REGISTER */ +SFR( PCA0CPM1, 0xDB ); /* PCA MODULE 1 MODE REGISTER */ +SFR( PCA0CPM2, 0xDC ); /* PCA MODULE 2 MODE REGISTER */ +SFR( CRC0IN, 0xDD ); /* CRC0 Data Input */ +SFR( CRC0DAT, 0xDE ); /* CRC0 Data Output */ +SFR( ADC0PWR, 0xDF ); /* ADC0 Power Control */ +SFR( ACC, 0xE0 ); /* ACCUMULATOR */ +SFR( XBR0, 0xE1 ); /* PORT MUX CONFIGURATION REGISTER 0 */ +SFR( XBR1, 0xE2 ); /* PORT MUX CONFIGURATION REGISTER 1 */ +SFR( XBR2, 0xE3 ); /* PORT MUX CONFIGURATION REGISTER 2 */ +SFR( IT01CF, 0xE4 ); /* INT0/INT1 CONFIGURATION REGISTER */ +SFR( EIE1, 0xE6 ); /* EXTERNAL INTERRUPT ENABLE 1 */ +SFR( ADC0CN0, 0xE8 ); /* ADC 0 CONTROL */ +SFR( PCA0CPL1, 0xE9 ); /* PCA CAPTURE 1 LOW */ +SFR( PCA0CPH1, 0xEA ); /* PCA CAPTURE 1 HIGH */ +SFR( PCA0CPL2, 0xEB ); /* PCA CAPTURE 2 LOW */ +SFR( PCA0CPH2, 0xEC ); /* PCA CAPTURE 2 HIGH */ +SFR( P1MAT, 0xED ); /* Port 1 Match */ +SFR( P1MASK, 0xEE ); /* Port 1 Mask */ +SFR( RSTSRC, 0xEF ); /* RESET SOURCE */ +SFR( B, 0xF0 ); /* B REGISTER */ +SFR( P0MDIN, 0xF1 ); /* PORT 0 INPUT MODE CONFIGURATION */ +SFR( P1MDIN, 0xF2 ); /* PORT 1 INPUT MODE CONFIGURATION */ +SFR( EIP1, 0xF3 ); /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +SFR( PRTDRV, 0xF6 ); /* Port Drive Strength */ +SFR( PCA0PWM, 0xF7 ); /* PCA PWM Configuration */ +SFR( SPI0CN0, 0xF8 ); /* SPI0 CONTROL */ +SFR( PCA0L, 0xF9 ); /* PCA COUNTER LOW */ +SFR( PCA0H, 0xFA ); /* PCA COUNTER HIGH */ +SFR( PCA0CPL0, 0xFB ); /* PCA CAPTURE 0 LOW */ +SFR( PCA0CPH0, 0xFC ); /* PCA CAPTURE 0 HIGH */ +SFR( P0MAT, 0xFD ); /* Port 0 Match */ +SFR( P0MASK, 0xFE ); /* Port 0 Mask */ +SFR( VDM0CN, 0xFF ); /* Supply Monitor Control */ + + +/* WORD/DWORD Registers */ + +SFR16E( TMR0, 0x8C8A ); /* TIMER 0 COUNTER */ +SFR16E( TMR1, 0x8D8B ); /* TIMER 1 COUNTER */ +SFR16( TMR2, 0xCC ); /* TIMER 2 COUNTER */ +SFR16( TMR2RL, 0xCA ); /* TIMER 2 CAPTURE REGISTER WORD */ +SFR16( TMR3, 0x94 ); /* TIMER 3 COUNTER */ +SFR16( TMR3RL, 0x92 ); /* TIMER 3 CAPTURE REGISTER WORD */ +SFR16( ADC0, 0xBD ); /* ADC 0 DATA WORD */ +SFR16( ADC0GT, 0xC3 ); /* ADC 0 GREATER-THAN REGISTER WORD */ +SFR16( ADC0LT, 0xC5 ); /* ADC 0 LESS-THAN REGISTER WORD */ +SFR16( PCA0, 0xF9 ); /* PCA COUNTER */ +SFR16( PCA0CP0, 0xFB ); /* PCA CAPTURE 0 WORD */ +SFR16( PCA0CP1, 0xE9 ); /* PCA CAPTURE 1 WORD */ +SFR16( PCA0CP2, 0xEB ); /* PCA CAPTURE 2 WORD */ + +/* BIT Registers */ + +/* P0 0x80 */ +SBIT( P0_0, 0x80, 0 ); /* Port 0 bit 0 */ +SBIT( P0_1, 0x80, 1 ); /* Port 0 bit 1 */ +SBIT( P0_2, 0x80, 2 ); /* Port 0 bit 2 */ +SBIT( P0_3, 0x80, 3 ); /* Port 0 bit 3 */ +SBIT( P0_4, 0x80, 4 ); /* Port 0 bit 4 */ +SBIT( P0_5, 0x80, 5 ); /* Port 0 bit 5 */ +SBIT( P0_6, 0x80, 6 ); /* Port 0 bit 6 */ +SBIT( P0_7, 0x80, 7 ); /* Port 0 bit 7 */ + +/* TCON 0x88 */ +SBIT( IT0, 0x88, 0 ); /* TCON.0 - EXT. INTERRUPT 0 TYPE */ +SBIT( IE0, 0x88, 1 ); /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */ +SBIT( IT1, 0x88, 2 ); /* TCON.2 - EXT. INTERRUPT 1 TYPE */ +SBIT( IE1, 0x88, 3 ); /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */ +SBIT( TR0, 0x88, 4 ); /* TCON.4 - TIMER 0 ON/OFF CONTROL */ +SBIT( TF0, 0x88, 5 ); /* TCON.5 - TIMER 0 OVERFLOW FLAG */ +SBIT( TR1, 0x88, 6 ); /* TCON.6 - TIMER 1 ON/OFF CONTROL */ +SBIT( TF1, 0x88, 7 ); /* TCON.7 - TIMER 1 OVERFLOW FLAG */ + +/* P1 0x90 */ +SBIT( P1_0, 0x90, 0 ); /* Port 1 bit 0 */ +SBIT( P1_1, 0x90, 1 ); /* Port 1 bit 1 */ +SBIT( P1_2, 0x90, 2 ); /* Port 1 bit 2 */ +SBIT( P1_3, 0x90, 3 ); /* Port 1 bit 3 */ +SBIT( P1_4, 0x90, 4 ); /* Port 1 bit 4 */ +SBIT( P1_5, 0x90, 5 ); /* Port 1 bit 5 */ +SBIT( P1_6, 0x90, 6 ); /* Port 1 bit 6 */ +SBIT( P1_7, 0x90, 7 ); /* Port 1 bit 7 */ + +/* SCON 0x98 */ +SBIT( RI, 0x98, 0 ); /* SCON.0 - RECEIVE INTERRUPT FLAG */ +SBIT( RI0, 0x98, 0 ); /* SCON.0 - RECEIVE INTERRUPT FLAG */ +SBIT( TI, 0x98, 1 ); /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +SBIT( TI0, 0x98, 1 ); /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +SBIT( RB8, 0x98, 2 ); /* SCON.2 - RECEIVE BIT 8 */ +SBIT( RB80, 0x98, 2 ); /* SCON.2 - RECEIVE BIT 8 */ +SBIT( TB8, 0x98, 3 ); /* SCON.3 - TRANSMIT BIT 8 */ +SBIT( TB80, 0x98, 3 ); /* SCON.3 - TRANSMIT BIT 8 */ +SBIT( REN, 0x98, 4 ); /* SCON.4 - RECEIVE ENABLE */ +SBIT( REN0, 0x98, 4 ); /* SCON.4 - RECEIVE ENABLE */ +SBIT( SM2, 0x98, 5 ); /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +SBIT( MCE0, 0x98, 5 ); /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +SBIT( SM0, 0x98, 7 ); /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ +SBIT( S0MODE, 0x98, 7 ); /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ +SBIT( SMODE, 0x98, 7 ); /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ + +/* P2 0xA0 */ +SBIT( P2_0, 0xA0, 0 ); /* Port 2 bit 0 */ +SBIT( P2_1, 0xA0, 1 ); /* Port 2 bit 1 */ +SBIT( P2_2, 0xA0, 2 ); /* Port 2 bit 2 */ +SBIT( P2_3, 0xA0, 3 ); /* Port 2 bit 3 */ +SBIT( P2_4, 0xA0, 4 ); /* Port 2 bit 4 */ +SBIT( P2_5, 0xA0, 5 ); /* Port 2 bit 5 */ +SBIT( P2_6, 0xA0, 6 ); /* Port 2 bit 6 */ +SBIT( P2_7, 0xA0, 7 ); /* Port 2 bit 7 */ + +/* IE 0xA8 */ +SBIT( EX0, 0xA8, 0 ); /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */ +SBIT( ET0, 0xA8, 1 ); /* IE.1 - TIMER 0 INTERRUPT ENABLE */ +SBIT( EX1, 0xA8, 2 ); /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */ +SBIT( ET1, 0xA8, 3 ); /* IE.3 - TIMER 1 INTERRUPT ENABLE */ +SBIT( ES, 0xA8, 4 ); /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +SBIT( ES0, 0xA8, 4 ); /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +SBIT( ET2, 0xA8, 5 ); /* IE.5 - TIMER 2 INTERRUPT ENABLE */ +SBIT( ESPI0, 0xA8, 6 ); /* IE.6 - SPI0 INTERRUPT ENABLE */ +SBIT( EA, 0xA8, 7 ); /* IE.7 - GLOBAL INTERRUPT ENABLE */ + +/* IP 0xB8 */ +SBIT( PX0, 0xB8, 0 ); /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */ +SBIT( PT0, 0xB8, 1 ); /* IP.1 - TIMER 0 PRIORITY */ +SBIT( PX1, 0xB8, 2 ); /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */ +SBIT( PT1, 0xB8, 3 ); /* IP.3 - TIMER 1 PRIORITY */ +SBIT( PS, 0xB8, 4 ); /* IP.4 - SERIAL PORT PRIORITY */ +SBIT( PS0, 0xB8, 4 ); /* IP.4 - SERIAL PORT PRIORITY */ +SBIT( PT2, 0xB8, 5 ); /* IP.5 - TIMER 2 PRIORITY */ +SBIT( PSPI0, 0xB8, 6 ); /* IP.6 - SPI0 PRIORITY */ + +/* SMB0CN 0xC0 */ +SBIT( SI, 0xC0, 0 ); /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */ +SBIT( ACK, 0xC0, 1 ); /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */ +SBIT( ARBLOST, 0xC0, 2 ); /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */ +SBIT( ACKRQ, 0xC0, 3 ); /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */ +SBIT( STO, 0xC0, 4 ); /* SMB0CN.4 - SMBUS 0 STOP FLAG */ +SBIT( STA, 0xC0, 5 ); /* SMB0CN.5 - SMBUS 0 START FLAG */ +SBIT( TXMODE, 0xC0, 6 ); /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */ +SBIT( MASTER, 0xC0, 7 ); /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */ + +/* TMR2CN 0xC8 */ +SBIT( T2XCLK, 0xC8, 0 ); /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */ +SBIT( TR2, 0xC8, 2 ); /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */ +SBIT( T2SPLIT, 0xC8, 3 ); /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */ +SBIT( TF2CEN, 0xC8, 4 ); /* TMR2CN.5 - TIMER 2 CAPTURE ENABLE */ +SBIT( TF2LEN, 0xC8, 5 ); /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */ +SBIT( TF2L, 0xC8, 6 ); /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */ +SBIT( TF2, 0xC8, 7 ); /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */ +SBIT( TF2H, 0xC8, 7 ); /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */ + +/* PSW 0xD0 */ +SBIT( PARITY, 0xD0, 0 ); /* PSW.0 - ACCUMULATOR PARITY FLAG */ +SBIT( F1, 0xD0, 1 ); /* PSW.1 - FLAG 1 */ +SBIT( OV, 0xD0, 2 ); /* PSW.2 - OVERFLOW FLAG */ +SBIT( RS0, 0xD0, 3 ); /* PSW.3 - REGISTER BANK SELECT 0 */ +SBIT( RS1, 0xD0, 4 ); /* PSW.4 - REGISTER BANK SELECT 1 */ +SBIT( F0, 0xD0, 5 ); /* PSW.5 - FLAG 0 */ +SBIT( AC, 0xD0, 6 ); /* PSW.6 - AUXILIARY CARRY FLAG */ +SBIT( CY, 0xD0, 7 ); /* PSW.7 - CARRY FLAG */ + +/* PCA0CN 0xD8 */ +SBIT( CCF0, 0xD8, 0 ); /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */ +SBIT( CCF1, 0xD8, 1 ); /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */ +SBIT( CCF2, 0xD8, 2 ); /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */ +SBIT( CR, 0xD8, 6 ); /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */ +SBIT( CF, 0xD8, 7 ); /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */ + +/* ADC0CN 0xE8 */ +SBIT( ADCM0, 0xE8, 0 ); /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */ +SBIT( ADCM1, 0xE8, 1 ); /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */ +SBIT( ADCM2, 0xE8, 2 ); /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */ +SBIT( ADWINT, 0xE8, 3 ); /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */ +SBIT( AD0WINT, 0xE8, 3 ); /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */ +SBIT( ADBUSY, 0xE8, 4 ); /* ADC0CN.4 - ADC 0 BUSY FLAG */ +SBIT( AD0BUSY, 0xE8, 4 ); /* ADC0CN.4 - ADC 0 BUSY FLAG */ +SBIT( ADINT, 0xE8, 5 ); /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ +SBIT( AD0INT, 0xE8, 5 ); /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ +SBIT( ADBMEN, 0xE8, 6 ); /* ADC0CN.6 - ADC 0 BURST MODE ENABLE */ +SBIT( ADEN, 0xE8, 7 ); /* ADC0CN.7 - ADC 0 ENABLE */ +SBIT( AD0EN, 0xE8, 7 ); /* ADC0CN.7 - ADC 0 ENABLE */ + +/* SPI0CN 0xF8 */ +SBIT( SPIEN, 0xF8, 0 ); /* SPI0CN.0 - SPI0 ENABLE */ +SBIT( TXBMT, 0xF8, 1 ); /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */ +SBIT( NSSMD0, 0xF8, 2 ); /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */ +SBIT( NSSMD1, 0xF8, 3 ); /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */ +SBIT( RXOVRN, 0xF8, 4 ); /* SPI0CN.4 - RECEIVE OVERRUN FLAG */ +SBIT( MODF, 0xF8, 5 ); /* SPI0CN.5 - MODE FAULT FLAG */ +SBIT( WCOL, 0xF8, 6 ); /* SPI0CN.6 - WRITE COLLISION FLAG */ +SBIT( SPIF, 0xF8, 7 ); /* SPI0CN.7 - SPI0 INTERRUPT FLAG */ + + +/* Predefined SFR Bit Masks */ + +#define PCON_IDLE 0x01 /* PCON */ +#define PCON_STOP 0x02 /* PCON */ +#define T1M 0x08 /* CKCON */ +#define PSWE 0x01 /* PSCTL */ +#define PSEE 0x02 /* PSCTL */ +#define ECP0 0x20 /* EIE1 */ +#define ECP1 0x40 /* EIE1 */ +#define PORSF 0x02 /* RSTSRC */ +#define SWRSF 0x10 /* RSTSRC */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ +#define PWM16 0x80 /* PCA0CPMn */ +#define CP0E 0x10 /* XBR0 */ +#define CP0OEN 0x10 /* XBR0 */ +#define CP0AE 0x20 /* XBR0 */ +#define CP0AOEN 0x20 /* XBR0 */ +#define CP1E 0x40 /* XBR0 */ +#define CP1AE 0x80 /* XBR0 */ + +/* Interrupts */ + +#define EXT0_VECTOR 0 /* External Interrupt 0 */ +#define TIMER0_VECTOR 1 /* Timer0 Overflow */ +#define EXT1_VECTOR 2 /* External Interrupt 1 */ +#define TIMER1_VECTOR 3 /* Timer1 Overflow */ +#define UART0_VECTOR 4 /* Serial Port 0 */ +#define TIMER2_VECTOR 5 /* Timer2 Overflow */ +#define SPI0_VECTOR 6 /* Serial Peripheral Interface 0 */ +#define SMBUS0_VECTOR 7 /* SMBus0 Interface */ +#define PMAT_VECTOR 8 /* Port Match */ +#define ADC0_WINDOW_VECTOR 9 /* ADC0 Window Comparison */ +#define ADC0_EOC_VECTOR 10 /* ADC0 End Of Conversion */ +#define PCA0_VECTOR 11 /* PCA0 Peripheral */ +#define CMP0_VECTOR 12 /* Comparator0 */ +#define CMP1_VECTOR 13 /* Comparator1 */ +#define TIMER3_VECTOR 14 /* Timer3 Overflow */ + +/*------------------------------------------------------------------------------ */ +/* ADC0CN0 Enums (ADC0 Control 0 @ 0xE8) */ +/*------------------------------------------------------------------------------ */ +#define ADCM__FMASK 0x07 /* Start of Conversion Mode Select */ +#define ADCM__SHIFT 0x00 /* Start of Conversion Mode Select */ +#define ADCM__ADBUSY 0x00 /* ADC0 conversion initiated on write of 1 to ADBUSY. */ +#define ADCM__TIMER0 0x01 /* ADC0 conversion initiated on overflow of Timer 0. */ +#define ADCM__TIMER2 0x02 /* ADC0 conversion initiated on overflow of Timer 2. */ +#define ADCM__TIMER3 0x03 /* ADC0 conversion initiated on overflow of Timer 3. */ +#define ADCM__CNVSTR 0x04 /* ADC0 conversion initiated on rising edge of CNVSTR. */ + +#define ADWINT__BMASK 0x08 /* Window Compare Interrupt Flag */ +#define ADWINT__SHIFT 0x03 /* Window Compare Interrupt Flag */ +#define ADWINT__NOT_SET 0x00 /* An ADC window compare event did not occur. */ +#define ADWINT__SET 0x08 /* An ADC window compare event occurred. */ + +#define ADBUSY__BMASK 0x10 /* ADC Busy */ +#define ADBUSY__SHIFT 0x04 /* ADC Busy */ +#define ADBUSY__NOT_SET 0x00 /* An ADC0 conversion is not currently in progress. */ +#define ADBUSY__SET 0x10 /* ADC0 conversion is in progress or start an ADC0 conversion. */ + +#define ADINT__BMASK 0x20 /* Conversion Complete Interrupt Flag */ +#define ADINT__SHIFT 0x05 /* Conversion Complete Interrupt Flag */ +#define ADINT__NOT_SET 0x00 /* ADC0 has not completed a conversion since the last time ADINT was cleared. */ +#define ADINT__SET 0x20 /* ADC0 completed a data conversion. */ + +#define ADBMEN__BMASK 0x40 /* Burst Mode Enable */ +#define ADBMEN__SHIFT 0x06 /* Burst Mode Enable */ +#define ADBMEN__BURST_DISABLED 0x00 /* Disable ADC0 burst mode. */ +#define ADBMEN__BURST_ENABLED 0x40 /* Enable ADC0 burst mode. */ + +#define ADEN__BMASK 0x80 /* ADC Enable */ +#define ADEN__SHIFT 0x07 /* ADC Enable */ +#define ADEN__DISABLED 0x00 /* Disable ADC0 (low-power shutdown). */ +#define ADEN__ENABLED 0x80 /* Enable ADC0 (active and ready for data conversions). */ + +/*------------------------------------------------------------------------------ */ +/* ADC0AC Enums (ADC0 Accumulator Configuration @ 0xB3) */ +/*------------------------------------------------------------------------------ */ +#define AD0RPT__FMASK 0x07 /* Repeat Count */ +#define AD0RPT__SHIFT 0x00 /* Repeat Count */ +#define AD0RPT__ACC_1 0x00 /* Perform and Accumulate 1 conversion (not used in 12-bit mode). */ +#define AD0RPT__ACC_4 0x01 /* Perform and Accumulate 4 conversions (1 conversion in 12-bit mode). */ +#define AD0RPT__ACC_8 0x02 /* Perform and Accumulate 8 conversions (2 conversions in 12-bit mode). */ +#define AD0RPT__ACC_16 0x03 /* Perform and Accumulate 16 conversions (4 conversions in 12-bit mode). */ +#define AD0RPT__ACC_32 0x04 /* Perform and Accumulate 32 conversions (8 conversions in 12-bit mode). */ +#define AD0RPT__ACC_64 0x05 /* Perform and Accumulate 64 conversions (16 conversions in 12-bit mode). */ + +#define AD0SJST__FMASK 0x38 /* Accumulator Shift and Justify */ +#define AD0SJST__SHIFT 0x03 /* Accumulator Shift and Justify */ +#define AD0SJST__RIGHT_NO_SHIFT 0x00 /* Right justified. No shifting applied. */ +#define AD0SJST__RIGHT_SHIFT_1 0x08 /* Right justified. Shifted right by 1 bit. */ +#define AD0SJST__RIGHT_SHIFT_2 0x10 /* Right justified. Shifted right by 2 bits. */ +#define AD0SJST__RIGHT_SHIFT_3 0x18 /* Right justified. Shifted right by 3 bits. */ +#define AD0SJST__LEFT_NO_SHIFT 0x20 /* Left justified. No shifting applied. */ + +#define AD0AE__BMASK 0x40 /* Accumulate Enable */ +#define AD0AE__SHIFT 0x06 /* Accumulate Enable */ +#define AD0AE__ACC_DISABLED 0x00 /* ADC0H:ADC0L contain the result of the latest conversion when Burst Mode is disabled. */ +#define AD0AE__ACC_ENABLED 0x40 /* ADC0H:ADC0L contain the accumulated conversion results when Burst Mode is disabled. Firmware must write 0x0000 to ADC0H:ADC0L to clear the accumulated result. */ + +#define AD12BE__BMASK 0x80 /* 12-Bit Mode Enable */ +#define AD12BE__SHIFT 0x07 /* 12-Bit Mode Enable */ +#define AD12BE__12_BIT_DISABLED 0x00 /* Disable 12-bit mode. */ +#define AD12BE__12_BIT_ENABLED 0x80 /* Enable 12-bit mode. */ + +/*------------------------------------------------------------------------------ */ +/* ADC0CF Enums (ADC0 Configuration @ 0xBC) */ +/*------------------------------------------------------------------------------ */ +#define ADGN__BMASK 0x01 /* Gain Control */ +#define ADGN__SHIFT 0x00 /* Gain Control */ +#define ADGN__GAIN_0P5 0x00 /* The on-chip PGA gain is 0.5. */ +#define ADGN__GAIN_1 0x01 /* The on-chip PGA gain is 1. */ + +#define ADTM__BMASK 0x02 /* Track Mode */ +#define ADTM__SHIFT 0x01 /* Track Mode */ +#define ADTM__TRACK_NORMAL 0x00 /* Normal Track Mode. When ADC0 is enabled, conversion begins immediately following the start-of-conversion signal. */ +#define ADTM__TRACK_DELAYED 0x02 /* Delayed Track Mode. When ADC0 is enabled, conversion begins 4 SAR clock cycles following the start-of-conversion signal. The ADC is allowed to track during this time. */ + +#define AD8BE__BMASK 0x04 /* 8-Bit Mode Enable */ +#define AD8BE__SHIFT 0x02 /* 8-Bit Mode Enable */ +#define AD8BE__NORMAL 0x00 /* ADC0 operates in 10-bit or 12-bit mode (normal operation). */ +#define AD8BE__8_BIT 0x04 /* ADC0 operates in 8-bit mode. */ + +#define ADSC__FMASK 0xF8 /* SAR Clock Divider */ +#define ADSC__SHIFT 0x03 /* SAR Clock Divider */ + +/*------------------------------------------------------------------------------ */ +/* P0MDIN Enums (Port 0 Input Mode @ 0xF1) */ +/*------------------------------------------------------------------------------ */ +#define B0__BMASK 0x01 /* Port 0 Bit 0 Input Mode */ +#define B0__SHIFT 0x00 /* Port 0 Bit 0 Input Mode */ +#define B0__ANALOG 0x00 /* P0.0 pin is configured for analog mode. */ +#define B0__DIGITAL 0x01 /* P0.0 pin is configured for digital mode. */ + +#define B1__BMASK 0x02 /* Port 0 Bit 1 Input Mode */ +#define B1__SHIFT 0x01 /* Port 0 Bit 1 Input Mode */ +#define B1__ANALOG 0x00 /* P0.1 pin is configured for analog mode. */ +#define B1__DIGITAL 0x02 /* P0.1 pin is configured for digital mode. */ + +#define B2__BMASK 0x04 /* Port 0 Bit 2 Input Mode */ +#define B2__SHIFT 0x02 /* Port 0 Bit 2 Input Mode */ +#define B2__ANALOG 0x00 /* P0.2 pin is configured for analog mode. */ +#define B2__DIGITAL 0x04 /* P0.2 pin is configured for digital mode. */ + +#define B3__BMASK 0x08 /* Port 0 Bit 3 Input Mode */ +#define B3__SHIFT 0x03 /* Port 0 Bit 3 Input Mode */ +#define B3__ANALOG 0x00 /* P0.3 pin is configured for analog mode. */ +#define B3__DIGITAL 0x08 /* P0.3 pin is configured for digital mode. */ + +#define B4__BMASK 0x10 /* Port 0 Bit 4 Input Mode */ +#define B4__SHIFT 0x04 /* Port 0 Bit 4 Input Mode */ +#define B4__ANALOG 0x00 /* P0.4 pin is configured for analog mode. */ +#define B4__DIGITAL 0x10 /* P0.4 pin is configured for digital mode. */ + +#define B5__BMASK 0x20 /* Port 0 Bit 5 Input Mode */ +#define B5__SHIFT 0x05 /* Port 0 Bit 5 Input Mode */ +#define B5__ANALOG 0x00 /* P0.5 pin is configured for analog mode. */ +#define B5__DIGITAL 0x20 /* P0.5 pin is configured for digital mode. */ + +#define B6__BMASK 0x40 /* Port 0 Bit 6 Input Mode */ +#define B6__SHIFT 0x06 /* Port 0 Bit 6 Input Mode */ +#define B6__ANALOG 0x00 /* P0.6 pin is configured for analog mode. */ +#define B6__DIGITAL 0x40 /* P0.6 pin is configured for digital mode. */ + +#define B7__BMASK 0x80 /* Port 0 Bit 7 Input Mode */ +#define B7__SHIFT 0x07 /* Port 0 Bit 7 Input Mode */ +#define B7__ANALOG 0x00 /* P0.7 pin is configured for analog mode. */ +#define B7__DIGITAL 0x80 /* P0.7 pin is configured for digital mode. */ + +/*------------------------------------------------------------------------------ */ +/* P0MDOUT Enums (Port 0 Output Mode @ 0xA4) */ +/*------------------------------------------------------------------------------ */ +#define B0__BMASK 0x01 /* Port 0 Bit 0 Output Mode */ +#define B0__SHIFT 0x00 /* Port 0 Bit 0 Output Mode */ +#define B0__OPEN_DRAIN 0x00 /* P0.0 output is open-drain. */ +#define B0__PUSH_PULL 0x01 /* P0.0 output is push-pull. */ + +#define B1__BMASK 0x02 /* Port 0 Bit 1 Output Mode */ +#define B1__SHIFT 0x01 /* Port 0 Bit 1 Output Mode */ +#define B1__OPEN_DRAIN 0x00 /* P0.1 output is open-drain. */ +#define B1__PUSH_PULL 0x02 /* P0.1 output is push-pull. */ + +#define B2__BMASK 0x04 /* Port 0 Bit 2 Output Mode */ +#define B2__SHIFT 0x02 /* Port 0 Bit 2 Output Mode */ +#define B2__OPEN_DRAIN 0x00 /* P0.2 output is open-drain. */ +#define B2__PUSH_PULL 0x04 /* P0.2 output is push-pull. */ + +#define B3__BMASK 0x08 /* Port 0 Bit 3 Output Mode */ +#define B3__SHIFT 0x03 /* Port 0 Bit 3 Output Mode */ +#define B3__OPEN_DRAIN 0x00 /* P0.3 output is open-drain. */ +#define B3__PUSH_PULL 0x08 /* P0.3 output is push-pull. */ + +#define B4__BMASK 0x10 /* Port 0 Bit 4 Output Mode */ +#define B4__SHIFT 0x04 /* Port 0 Bit 4 Output Mode */ +#define B4__OPEN_DRAIN 0x00 /* P0.4 output is open-drain. */ +#define B4__PUSH_PULL 0x10 /* P0.4 output is push-pull. */ + +#define B5__BMASK 0x20 /* Port 0 Bit 5 Output Mode */ +#define B5__SHIFT 0x05 /* Port 0 Bit 5 Output Mode */ +#define B5__OPEN_DRAIN 0x00 /* P0.5 output is open-drain. */ +#define B5__PUSH_PULL 0x20 /* P0.5 output is push-pull. */ + +#define B6__BMASK 0x40 /* Port 0 Bit 6 Output Mode */ +#define B6__SHIFT 0x06 /* Port 0 Bit 6 Output Mode */ +#define B6__OPEN_DRAIN 0x00 /* P0.6 output is open-drain. */ +#define B6__PUSH_PULL 0x40 /* P0.6 output is push-pull. */ + +#define B7__BMASK 0x80 /* Port 0 Bit 7 Output Mode */ +#define B7__SHIFT 0x07 /* Port 0 Bit 7 Output Mode */ +#define B7__OPEN_DRAIN 0x00 /* P0.7 output is open-drain. */ +#define B7__PUSH_PULL 0x80 /* P0.7 output is push-pull. */ + +/*------------------------------------------------------------------------------ */ +/* P0SKIP Enums (Port 0 Skip @ 0xD4) */ +/*------------------------------------------------------------------------------ */ +#define B0__BMASK 0x01 /* Port 0 Bit 0 Skip */ +#define B0__SHIFT 0x00 /* Port 0 Bit 0 Skip */ +#define B0__NOT_SKIPPED 0x00 /* P0.0 pin is not skipped by the crossbar. */ +#define B0__SKIPPED 0x01 /* P0.0 pin is skipped by the crossbar. */ + +#define B1__BMASK 0x02 /* Port 0 Bit 1 Skip */ +#define B1__SHIFT 0x01 /* Port 0 Bit 1 Skip */ +#define B1__NOT_SKIPPED 0x00 /* P0.1 pin is not skipped by the crossbar. */ +#define B1__SKIPPED 0x02 /* P0.1 pin is skipped by the crossbar. */ + +#define B2__BMASK 0x04 /* Port 0 Bit 2 Skip */ +#define B2__SHIFT 0x02 /* Port 0 Bit 2 Skip */ +#define B2__NOT_SKIPPED 0x00 /* P0.2 pin is not skipped by the crossbar. */ +#define B2__SKIPPED 0x04 /* P0.2 pin is skipped by the crossbar. */ + +#define B3__BMASK 0x08 /* Port 0 Bit 3 Skip */ +#define B3__SHIFT 0x03 /* Port 0 Bit 3 Skip */ +#define B3__NOT_SKIPPED 0x00 /* P0.3 pin is not skipped by the crossbar. */ +#define B3__SKIPPED 0x08 /* P0.3 pin is skipped by the crossbar. */ + +#define B4__BMASK 0x10 /* Port 0 Bit 4 Skip */ +#define B4__SHIFT 0x04 /* Port 0 Bit 4 Skip */ +#define B4__NOT_SKIPPED 0x00 /* P0.4 pin is not skipped by the crossbar. */ +#define B4__SKIPPED 0x10 /* P0.4 pin is skipped by the crossbar. */ + +#define B5__BMASK 0x20 /* Port 0 Bit 5 Skip */ +#define B5__SHIFT 0x05 /* Port 0 Bit 5 Skip */ +#define B5__NOT_SKIPPED 0x00 /* P0.5 pin is not skipped by the crossbar. */ +#define B5__SKIPPED 0x20 /* P0.5 pin is skipped by the crossbar. */ + +#define B6__BMASK 0x40 /* Port 0 Bit 6 Skip */ +#define B6__SHIFT 0x06 /* Port 0 Bit 6 Skip */ +#define B6__NOT_SKIPPED 0x00 /* P0.6 pin is not skipped by the crossbar. */ +#define B6__SKIPPED 0x40 /* P0.6 pin is skipped by the crossbar. */ + +#define B7__BMASK 0x80 /* Port 0 Bit 7 Skip */ +#define B7__SHIFT 0x07 /* Port 0 Bit 7 Skip */ +#define B7__NOT_SKIPPED 0x00 /* P0.7 pin is not skipped by the crossbar. */ +#define B7__SKIPPED 0x80 /* P0.7 pin is skipped by the crossbar. */ + +/*------------------------------------------------------------------------------ */ +/* P0 Enums (Port 0 Pin Latch @ 0x80) */ +/*------------------------------------------------------------------------------ */ +#define B0__BMASK 0x01 /* Port 0 Bit 0 Latch */ +#define B0__SHIFT 0x00 /* Port 0 Bit 0 Latch */ +#define B0__LOW 0x00 /* P0.0 is low. Set P0.0 to drive low. */ +#define B0__HIGH 0x01 /* P0.0 is high. Set P0.0 to drive or float high. */ + +#define B1__BMASK 0x02 /* Port 0 Bit 1 Latch */ +#define B1__SHIFT 0x01 /* Port 0 Bit 1 Latch */ +#define B1__LOW 0x00 /* P0.1 is low. Set P0.1 to drive low. */ +#define B1__HIGH 0x02 /* P0.1 is high. Set P0.1 to drive or float high. */ + +#define B2__BMASK 0x04 /* Port 0 Bit 2 Latch */ +#define B2__SHIFT 0x02 /* Port 0 Bit 2 Latch */ +#define B2__LOW 0x00 /* P0.2 is low. Set P0.2 to drive low. */ +#define B2__HIGH 0x04 /* P0.2 is high. Set P0.2 to drive or float high. */ + +#define B3__BMASK 0x08 /* Port 0 Bit 3 Latch */ +#define B3__SHIFT 0x03 /* Port 0 Bit 3 Latch */ +#define B3__LOW 0x00 /* P0.3 is low. Set P0.3 to drive low. */ +#define B3__HIGH 0x08 /* P0.3 is high. Set P0.3 to drive or float high. */ + +#define B4__BMASK 0x10 /* Port 0 Bit 4 Latch */ +#define B4__SHIFT 0x04 /* Port 0 Bit 4 Latch */ +#define B4__LOW 0x00 /* P0.4 is low. Set P0.4 to drive low. */ +#define B4__HIGH 0x10 /* P0.4 is high. Set P0.4 to drive or float high. */ + +#define B5__BMASK 0x20 /* Port 0 Bit 5 Latch */ +#define B5__SHIFT 0x05 /* Port 0 Bit 5 Latch */ +#define B5__LOW 0x00 /* P0.5 is low. Set P0.5 to drive low. */ +#define B5__HIGH 0x20 /* P0.5 is high. Set P0.5 to drive or float high. */ + +#define B6__BMASK 0x40 /* Port 0 Bit 6 Latch */ +#define B6__SHIFT 0x06 /* Port 0 Bit 6 Latch */ +#define B6__LOW 0x00 /* P0.6 is low. Set P0.6 to drive low. */ +#define B6__HIGH 0x40 /* P0.6 is high. Set P0.6 to drive or float high. */ + +#define B7__BMASK 0x80 /* Port 0 Bit 7 Latch */ +#define B7__SHIFT 0x07 /* Port 0 Bit 7 Latch */ +#define B7__LOW 0x00 /* P0.7 is low. Set P0.7 to drive low. */ +#define B7__HIGH 0x80 /* P0.7 is high. Set P0.7 to drive or float high. */ + +/*------------------------------------------------------------------------------ */ +/* P0MASK Enums (Port 0 Mask @ 0xFE) */ +/*------------------------------------------------------------------------------ */ +#define B0__BMASK 0x01 /* Port 0 Bit 0 Mask Value */ +#define B0__SHIFT 0x00 /* Port 0 Bit 0 Mask Value */ +#define B0__IGNORED 0x00 /* P0.0 pin logic value is ignored and will not cause a port mismatch event. */ +#define B0__COMPARED 0x01 /* P0.0 pin logic value is compared to P0MAT.0. */ + +#define B1__BMASK 0x02 /* Port 0 Bit 1 Mask Value */ +#define B1__SHIFT 0x01 /* Port 0 Bit 1 Mask Value */ +#define B1__IGNORED 0x00 /* P0.1 pin logic value is ignored and will not cause a port mismatch event. */ +#define B1__COMPARED 0x02 /* P0.1 pin logic value is compared to P0MAT.1. */ + +#define B2__BMASK 0x04 /* Port 0 Bit 2 Mask Value */ +#define B2__SHIFT 0x02 /* Port 0 Bit 2 Mask Value */ +#define B2__IGNORED 0x00 /* P0.2 pin logic value is ignored and will not cause a port mismatch event. */ +#define B2__COMPARED 0x04 /* P0.2 pin logic value is compared to P0MAT.2. */ + +#define B3__BMASK 0x08 /* Port 0 Bit 3 Mask Value */ +#define B3__SHIFT 0x03 /* Port 0 Bit 3 Mask Value */ +#define B3__IGNORED 0x00 /* P0.3 pin logic value is ignored and will not cause a port mismatch event. */ +#define B3__COMPARED 0x08 /* P0.3 pin logic value is compared to P0MAT.3. */ + +#define B4__BMASK 0x10 /* Port 0 Bit 4 Mask Value */ +#define B4__SHIFT 0x04 /* Port 0 Bit 4 Mask Value */ +#define B4__IGNORED 0x00 /* P0.4 pin logic value is ignored and will not cause a port mismatch event. */ +#define B4__COMPARED 0x10 /* P0.4 pin logic value is compared to P0MAT.4. */ + +#define B5__BMASK 0x20 /* Port 0 Bit 5 Mask Value */ +#define B5__SHIFT 0x05 /* Port 0 Bit 5 Mask Value */ +#define B5__IGNORED 0x00 /* P0.5 pin logic value is ignored and will not cause a port mismatch event. */ +#define B5__COMPARED 0x20 /* P0.5 pin logic value is compared to P0MAT.5. */ + +#define B6__BMASK 0x40 /* Port 0 Bit 6 Mask Value */ +#define B6__SHIFT 0x06 /* Port 0 Bit 6 Mask Value */ +#define B6__IGNORED 0x00 /* P0.6 pin logic value is ignored and will not cause a port mismatch event. */ +#define B6__COMPARED 0x40 /* P0.6 pin logic value is compared to P0MAT.6. */ + +#define B7__BMASK 0x80 /* Port 0 Bit 7 Mask Value */ +#define B7__SHIFT 0x07 /* Port 0 Bit 7 Mask Value */ +#define B7__IGNORED 0x00 /* P0.7 pin logic value is ignored and will not cause a port mismatch event. */ +#define B7__COMPARED 0x80 /* P0.7 pin logic value is compared to P0MAT.7. */ + +/*------------------------------------------------------------------------------ */ +/* P0MAT Enums (Port 0 Match @ 0xFD) */ +/*------------------------------------------------------------------------------ */ +#define B0__BMASK 0x01 /* Port 0 Bit 0 Match Value */ +#define B0__SHIFT 0x00 /* Port 0 Bit 0 Match Value */ +#define B0__LOW 0x00 /* P0.0 pin logic value is compared with logic LOW. */ +#define B0__HIGH 0x01 /* P0.0 pin logic value is compared with logic HIGH. */ + +#define B1__BMASK 0x02 /* Port 0 Bit 1 Match Value */ +#define B1__SHIFT 0x01 /* Port 0 Bit 1 Match Value */ +#define B1__LOW 0x00 /* P0.1 pin logic value is compared with logic LOW. */ +#define B1__HIGH 0x02 /* P0.1 pin logic value is compared with logic HIGH. */ + +#define B2__BMASK 0x04 /* Port 0 Bit 2 Match Value */ +#define B2__SHIFT 0x02 /* Port 0 Bit 2 Match Value */ +#define B2__LOW 0x00 /* P0.2 pin logic value is compared with logic LOW. */ +#define B2__HIGH 0x04 /* P0.2 pin logic value is compared with logic HIGH. */ + +#define B3__BMASK 0x08 /* Port 0 Bit 3 Match Value */ +#define B3__SHIFT 0x03 /* Port 0 Bit 3 Match Value */ +#define B3__LOW 0x00 /* P0.3 pin logic value is compared with logic LOW. */ +#define B3__HIGH 0x08 /* P0.3 pin logic value is compared with logic HIGH. */ + +#define B4__BMASK 0x10 /* Port 0 Bit 4 Match Value */ +#define B4__SHIFT 0x04 /* Port 0 Bit 4 Match Value */ +#define B4__LOW 0x00 /* P0.4 pin logic value is compared with logic LOW. */ +#define B4__HIGH 0x10 /* P0.4 pin logic value is compared with logic HIGH. */ + +#define B5__BMASK 0x20 /* Port 0 Bit 5 Match Value */ +#define B5__SHIFT 0x05 /* Port 0 Bit 5 Match Value */ +#define B5__LOW 0x00 /* P0.5 pin logic value is compared with logic LOW. */ +#define B5__HIGH 0x20 /* P0.5 pin logic value is compared with logic HIGH. */ + +#define B6__BMASK 0x40 /* Port 0 Bit 6 Match Value */ +#define B6__SHIFT 0x06 /* Port 0 Bit 6 Match Value */ +#define B6__LOW 0x00 /* P0.6 pin logic value is compared with logic LOW. */ +#define B6__HIGH 0x40 /* P0.6 pin logic value is compared with logic HIGH. */ + +#define B7__BMASK 0x80 /* Port 0 Bit 7 Match Value */ +#define B7__SHIFT 0x07 /* Port 0 Bit 7 Match Value */ +#define B7__LOW 0x00 /* P0.7 pin logic value is compared with logic LOW. */ +#define B7__HIGH 0x80 /* P0.7 pin logic value is compared with logic HIGH. */ + +/*------------------------------------------------------------------------------ */ +/* P1 Enums (Port 1 Pin Latch @ 0x90) */ +/*------------------------------------------------------------------------------ */ +#define B0__BMASK 0x01 /* Port 1 Bit 0 Latch */ +#define B0__SHIFT 0x00 /* Port 1 Bit 0 Latch */ +#define B0__LOW 0x00 /* P1.0 is low. Set P1.0 to drive low. */ +#define B0__HIGH 0x01 /* P1.0 is high. Set P1.0 to drive or float high. */ + +#define B1__BMASK 0x02 /* Port 1 Bit 1 Latch */ +#define B1__SHIFT 0x01 /* Port 1 Bit 1 Latch */ +#define B1__LOW 0x00 /* P1.1 is low. Set P1.1 to drive low. */ +#define B1__HIGH 0x02 /* P1.1 is high. Set P1.1 to drive or float high. */ + +#define B2__BMASK 0x04 /* Port 1 Bit 2 Latch */ +#define B2__SHIFT 0x02 /* Port 1 Bit 2 Latch */ +#define B2__LOW 0x00 /* P1.2 is low. Set P1.2 to drive low. */ +#define B2__HIGH 0x04 /* P1.2 is high. Set P1.2 to drive or float high. */ + +#define B3__BMASK 0x08 /* Port 1 Bit 3 Latch */ +#define B3__SHIFT 0x03 /* Port 1 Bit 3 Latch */ +#define B3__LOW 0x00 /* P1.3 is low. Set P1.3 to drive low. */ +#define B3__HIGH 0x08 /* P1.3 is high. Set P1.3 to drive or float high. */ + +#define B4__BMASK 0x10 /* Port 1 Bit 4 Latch */ +#define B4__SHIFT 0x04 /* Port 1 Bit 4 Latch */ +#define B4__LOW 0x00 /* P1.4 is low. Set P1.4 to drive low. */ +#define B4__HIGH 0x10 /* P1.4 is high. Set P1.4 to drive or float high. */ + +#define B5__BMASK 0x20 /* Port 1 Bit 5 Latch */ +#define B5__SHIFT 0x05 /* Port 1 Bit 5 Latch */ +#define B5__LOW 0x00 /* P1.5 is low. Set P1.5 to drive low. */ +#define B5__HIGH 0x20 /* P1.5 is high. Set P1.5 to drive or float high. */ + +#define B6__BMASK 0x40 /* Port 1 Bit 6 Latch */ +#define B6__SHIFT 0x06 /* Port 1 Bit 6 Latch */ +#define B6__LOW 0x00 /* P1.6 is low. Set P1.6 to drive low. */ +#define B6__HIGH 0x40 /* P1.6 is high. Set P1.6 to drive or float high. */ + +#define B7__BMASK 0x80 /* Port 1 Bit 7 Latch */ +#define B7__SHIFT 0x07 /* Port 1 Bit 7 Latch */ +#define B7__LOW 0x00 /* P1.7 is low. Set P1.7 to drive low. */ +#define B7__HIGH 0x80 /* P1.7 is high. Set P1.7 to drive or float high. */ + +/*------------------------------------------------------------------------------ */ +/* P1MASK Enums (Port 1 Mask @ 0xEE) */ +/*------------------------------------------------------------------------------ */ +#define B0__BMASK 0x01 /* Port 1 Bit 0 Mask Value */ +#define B0__SHIFT 0x00 /* Port 1 Bit 0 Mask Value */ +#define B0__IGNORED 0x00 /* P1.0 pin logic value is ignored and will not cause a port mismatch event. */ +#define B0__COMPARED 0x01 /* P1.0 pin logic value is compared to P1MAT.0. */ + +#define B1__BMASK 0x02 /* Port 1 Bit 1 Mask Value */ +#define B1__SHIFT 0x01 /* Port 1 Bit 1 Mask Value */ +#define B1__IGNORED 0x00 /* P1.1 pin logic value is ignored and will not cause a port mismatch event. */ +#define B1__COMPARED 0x02 /* P1.1 pin logic value is compared to P1MAT.1. */ + +#define B2__BMASK 0x04 /* Port 1 Bit 2 Mask Value */ +#define B2__SHIFT 0x02 /* Port 1 Bit 2 Mask Value */ +#define B2__IGNORED 0x00 /* P1.2 pin logic value is ignored and will not cause a port mismatch event. */ +#define B2__COMPARED 0x04 /* P1.2 pin logic value is compared to P1MAT.2. */ + +#define B3__BMASK 0x08 /* Port 1 Bit 3 Mask Value */ +#define B3__SHIFT 0x03 /* Port 1 Bit 3 Mask Value */ +#define B3__IGNORED 0x00 /* P1.3 pin logic value is ignored and will not cause a port mismatch event. */ +#define B3__COMPARED 0x08 /* P1.3 pin logic value is compared to P1MAT.3. */ + +#define B4__BMASK 0x10 /* Port 1 Bit 4 Mask Value */ +#define B4__SHIFT 0x04 /* Port 1 Bit 4 Mask Value */ +#define B4__IGNORED 0x00 /* P1.4 pin logic value is ignored and will not cause a port mismatch event. */ +#define B4__COMPARED 0x10 /* P1.4 pin logic value is compared to P1MAT.4. */ + +#define B5__BMASK 0x20 /* Port 1 Bit 5 Mask Value */ +#define B5__SHIFT 0x05 /* Port 1 Bit 5 Mask Value */ +#define B5__IGNORED 0x00 /* P1.5 pin logic value is ignored and will not cause a port mismatch event. */ +#define B5__COMPARED 0x20 /* P1.5 pin logic value is compared to P1MAT.5. */ + +#define B6__BMASK 0x40 /* Port 1 Bit 6 Mask Value */ +#define B6__SHIFT 0x06 /* Port 1 Bit 6 Mask Value */ +#define B6__IGNORED 0x00 /* P1.6 pin logic value is ignored and will not cause a port mismatch event. */ +#define B6__COMPARED 0x40 /* P1.6 pin logic value is compared to P1MAT.6. */ + +#define B7__BMASK 0x80 /* Port 1 Bit 7 Mask Value */ +#define B7__SHIFT 0x07 /* Port 1 Bit 7 Mask Value */ +#define B7__IGNORED 0x00 /* P1.7 pin logic value is ignored and will not cause a port mismatch event. */ +#define B7__COMPARED 0x80 /* P1.7 pin logic value is compared to P1MAT.7. */ + +/*------------------------------------------------------------------------------ */ +/* P1MAT Enums (Port 1 Match @ 0xED) */ +/*------------------------------------------------------------------------------ */ +#define B0__BMASK 0x01 /* Port 1 Bit 0 Match Value */ +#define B0__SHIFT 0x00 /* Port 1 Bit 0 Match Value */ +#define B0__LOW 0x00 /* P1.0 pin logic value is compared with logic LOW. */ +#define B0__HIGH 0x01 /* P1.0 pin logic value is compared with logic HIGH. */ + +#define B1__BMASK 0x02 /* Port 1 Bit 1 Match Value */ +#define B1__SHIFT 0x01 /* Port 1 Bit 1 Match Value */ +#define B1__LOW 0x00 /* P1.1 pin logic value is compared with logic LOW. */ +#define B1__HIGH 0x02 /* P1.1 pin logic value is compared with logic HIGH. */ + +#define B2__BMASK 0x04 /* Port 1 Bit 2 Match Value */ +#define B2__SHIFT 0x02 /* Port 1 Bit 2 Match Value */ +#define B2__LOW 0x00 /* P1.2 pin logic value is compared with logic LOW. */ +#define B2__HIGH 0x04 /* P1.2 pin logic value is compared with logic HIGH. */ + +#define B3__BMASK 0x08 /* Port 1 Bit 3 Match Value */ +#define B3__SHIFT 0x03 /* Port 1 Bit 3 Match Value */ +#define B3__LOW 0x00 /* P1.3 pin logic value is compared with logic LOW. */ +#define B3__HIGH 0x08 /* P1.3 pin logic value is compared with logic HIGH. */ + +#define B4__BMASK 0x10 /* Port 1 Bit 4 Match Value */ +#define B4__SHIFT 0x04 /* Port 1 Bit 4 Match Value */ +#define B4__LOW 0x00 /* P1.4 pin logic value is compared with logic LOW. */ +#define B4__HIGH 0x10 /* P1.4 pin logic value is compared with logic HIGH. */ + +#define B5__BMASK 0x20 /* Port 1 Bit 5 Match Value */ +#define B5__SHIFT 0x05 /* Port 1 Bit 5 Match Value */ +#define B5__LOW 0x00 /* P1.5 pin logic value is compared with logic LOW. */ +#define B5__HIGH 0x20 /* P1.5 pin logic value is compared with logic HIGH. */ + +#define B6__BMASK 0x40 /* Port 1 Bit 6 Match Value */ +#define B6__SHIFT 0x06 /* Port 1 Bit 6 Match Value */ +#define B6__LOW 0x00 /* P1.6 pin logic value is compared with logic LOW. */ +#define B6__HIGH 0x40 /* P1.6 pin logic value is compared with logic HIGH. */ + +#define B7__BMASK 0x80 /* Port 1 Bit 7 Match Value */ +#define B7__SHIFT 0x07 /* Port 1 Bit 7 Match Value */ +#define B7__LOW 0x00 /* P1.7 pin logic value is compared with logic LOW. */ +#define B7__HIGH 0x80 /* P1.7 pin logic value is compared with logic HIGH. */ + +/*------------------------------------------------------------------------------ */ +/* P1MDIN Enums (Port 1 Input Mode @ 0xF2) */ +/*------------------------------------------------------------------------------ */ +#define B0__BMASK 0x01 /* Port 1 Bit 0 Input Mode */ +#define B0__SHIFT 0x00 /* Port 1 Bit 0 Input Mode */ +#define B0__ANALOG 0x00 /* P1.0 pin is configured for analog mode. */ +#define B0__DIGITAL 0x01 /* P1.0 pin is configured for digital mode. */ + +#define B1__BMASK 0x02 /* Port 1 Bit 1 Input Mode */ +#define B1__SHIFT 0x01 /* Port 1 Bit 1 Input Mode */ +#define B1__ANALOG 0x00 /* P1.1 pin is configured for analog mode. */ +#define B1__DIGITAL 0x02 /* P1.1 pin is configured for digital mode. */ + +#define B2__BMASK 0x04 /* Port 1 Bit 2 Input Mode */ +#define B2__SHIFT 0x02 /* Port 1 Bit 2 Input Mode */ +#define B2__ANALOG 0x00 /* P1.2 pin is configured for analog mode. */ +#define B2__DIGITAL 0x04 /* P1.2 pin is configured for digital mode. */ + +#define B3__BMASK 0x08 /* Port 1 Bit 3 Input Mode */ +#define B3__SHIFT 0x03 /* Port 1 Bit 3 Input Mode */ +#define B3__ANALOG 0x00 /* P1.3 pin is configured for analog mode. */ +#define B3__DIGITAL 0x08 /* P1.3 pin is configured for digital mode. */ + +#define B4__BMASK 0x10 /* Port 1 Bit 4 Input Mode */ +#define B4__SHIFT 0x04 /* Port 1 Bit 4 Input Mode */ +#define B4__ANALOG 0x00 /* P1.4 pin is configured for analog mode. */ +#define B4__DIGITAL 0x10 /* P1.4 pin is configured for digital mode. */ + +#define B5__BMASK 0x20 /* Port 1 Bit 5 Input Mode */ +#define B5__SHIFT 0x05 /* Port 1 Bit 5 Input Mode */ +#define B5__ANALOG 0x00 /* P1.5 pin is configured for analog mode. */ +#define B5__DIGITAL 0x20 /* P1.5 pin is configured for digital mode. */ + +#define B6__BMASK 0x40 /* Port 1 Bit 6 Input Mode */ +#define B6__SHIFT 0x06 /* Port 1 Bit 6 Input Mode */ +#define B6__ANALOG 0x00 /* P1.6 pin is configured for analog mode. */ +#define B6__DIGITAL 0x40 /* P1.6 pin is configured for digital mode. */ + +#define B7__BMASK 0x80 /* Port 1 Bit 7 Input Mode */ +#define B7__SHIFT 0x07 /* Port 1 Bit 7 Input Mode */ +#define B7__ANALOG 0x00 /* P1.7 pin is configured for analog mode. */ +#define B7__DIGITAL 0x80 /* P1.7 pin is configured for digital mode. */ + +/*------------------------------------------------------------------------------ */ +/* P1MDOUT Enums (Port 1 Output Mode @ 0xA5) */ +/*------------------------------------------------------------------------------ */ +#define B0__BMASK 0x01 /* Port 1 Bit 0 Output Mode */ +#define B0__SHIFT 0x00 /* Port 1 Bit 0 Output Mode */ +#define B0__OPEN_DRAIN 0x00 /* P1.0 output is open-drain. */ +#define B0__PUSH_PULL 0x01 /* P1.0 output is push-pull. */ + +#define B1__BMASK 0x02 /* Port 1 Bit 1 Output Mode */ +#define B1__SHIFT 0x01 /* Port 1 Bit 1 Output Mode */ +#define B1__OPEN_DRAIN 0x00 /* P1.1 output is open-drain. */ +#define B1__PUSH_PULL 0x02 /* P1.1 output is push-pull. */ + +#define B2__BMASK 0x04 /* Port 1 Bit 2 Output Mode */ +#define B2__SHIFT 0x02 /* Port 1 Bit 2 Output Mode */ +#define B2__OPEN_DRAIN 0x00 /* P1.2 output is open-drain. */ +#define B2__PUSH_PULL 0x04 /* P1.2 output is push-pull. */ + +#define B3__BMASK 0x08 /* Port 1 Bit 3 Output Mode */ +#define B3__SHIFT 0x03 /* Port 1 Bit 3 Output Mode */ +#define B3__OPEN_DRAIN 0x00 /* P1.3 output is open-drain. */ +#define B3__PUSH_PULL 0x08 /* P1.3 output is push-pull. */ + +#define B4__BMASK 0x10 /* Port 1 Bit 4 Output Mode */ +#define B4__SHIFT 0x04 /* Port 1 Bit 4 Output Mode */ +#define B4__OPEN_DRAIN 0x00 /* P1.4 output is open-drain. */ +#define B4__PUSH_PULL 0x10 /* P1.4 output is push-pull. */ + +#define B5__BMASK 0x20 /* Port 1 Bit 5 Output Mode */ +#define B5__SHIFT 0x05 /* Port 1 Bit 5 Output Mode */ +#define B5__OPEN_DRAIN 0x00 /* P1.5 output is open-drain. */ +#define B5__PUSH_PULL 0x20 /* P1.5 output is push-pull. */ + +#define B6__BMASK 0x40 /* Port 1 Bit 6 Output Mode */ +#define B6__SHIFT 0x06 /* Port 1 Bit 6 Output Mode */ +#define B6__OPEN_DRAIN 0x00 /* P1.6 output is open-drain. */ +#define B6__PUSH_PULL 0x40 /* P1.6 output is push-pull. */ + +#define B7__BMASK 0x80 /* Port 1 Bit 7 Output Mode */ +#define B7__SHIFT 0x07 /* Port 1 Bit 7 Output Mode */ +#define B7__OPEN_DRAIN 0x00 /* P1.7 output is open-drain. */ +#define B7__PUSH_PULL 0x80 /* P1.7 output is push-pull. */ + +/*------------------------------------------------------------------------------ */ +/* P1SKIP Enums (Port 1 Skip @ 0xD5) */ +/*------------------------------------------------------------------------------ */ +#define B0__BMASK 0x01 /* Port 1 Bit 0 Skip */ +#define B0__SHIFT 0x00 /* Port 1 Bit 0 Skip */ +#define B0__NOT_SKIPPED 0x00 /* P1.0 pin is not skipped by the crossbar. */ +#define B0__SKIPPED 0x01 /* P1.0 pin is skipped by the crossbar. */ + +#define B1__BMASK 0x02 /* Port 1 Bit 1 Skip */ +#define B1__SHIFT 0x01 /* Port 1 Bit 1 Skip */ +#define B1__NOT_SKIPPED 0x00 /* P1.1 pin is not skipped by the crossbar. */ +#define B1__SKIPPED 0x02 /* P1.1 pin is skipped by the crossbar. */ + +#define B2__BMASK 0x04 /* Port 1 Bit 2 Skip */ +#define B2__SHIFT 0x02 /* Port 1 Bit 2 Skip */ +#define B2__NOT_SKIPPED 0x00 /* P1.2 pin is not skipped by the crossbar. */ +#define B2__SKIPPED 0x04 /* P1.2 pin is skipped by the crossbar. */ + +#define B3__BMASK 0x08 /* Port 1 Bit 3 Skip */ +#define B3__SHIFT 0x03 /* Port 1 Bit 3 Skip */ +#define B3__NOT_SKIPPED 0x00 /* P1.3 pin is not skipped by the crossbar. */ +#define B3__SKIPPED 0x08 /* P1.3 pin is skipped by the crossbar. */ + +#define B4__BMASK 0x10 /* Port 1 Bit 4 Skip */ +#define B4__SHIFT 0x04 /* Port 1 Bit 4 Skip */ +#define B4__NOT_SKIPPED 0x00 /* P1.4 pin is not skipped by the crossbar. */ +#define B4__SKIPPED 0x10 /* P1.4 pin is skipped by the crossbar. */ + +#define B5__BMASK 0x20 /* Port 1 Bit 5 Skip */ +#define B5__SHIFT 0x05 /* Port 1 Bit 5 Skip */ +#define B5__NOT_SKIPPED 0x00 /* P1.5 pin is not skipped by the crossbar. */ +#define B5__SKIPPED 0x20 /* P1.5 pin is skipped by the crossbar. */ + +#define B6__BMASK 0x40 /* Port 1 Bit 6 Skip */ +#define B6__SHIFT 0x06 /* Port 1 Bit 6 Skip */ +#define B6__NOT_SKIPPED 0x00 /* P1.6 pin is not skipped by the crossbar. */ +#define B6__SKIPPED 0x40 /* P1.6 pin is skipped by the crossbar. */ + +#define B7__BMASK 0x80 /* Port 1 Bit 7 Skip */ +#define B7__SHIFT 0x07 /* Port 1 Bit 7 Skip */ +#define B7__NOT_SKIPPED 0x00 /* P1.7 pin is not skipped by the crossbar. */ +#define B7__SKIPPED 0x80 /* P1.7 pin is skipped by the crossbar. */ + +/*------------------------------------------------------------------------------ */ +/* P2 Enums (Port 2 Pin Latch @ 0xA0) */ +/*------------------------------------------------------------------------------ */ +#define B0__BMASK 0x01 /* Port 2 Bit 0 Latch */ +#define B0__SHIFT 0x00 /* Port 2 Bit 0 Latch */ +#define B0__LOW 0x00 /* P2.0 is low. Set P2.0 to drive low. */ +#define B0__HIGH 0x01 /* P2.0 is high. Set P2.0 to drive or float high. */ + +#define B1__BMASK 0x02 /* Port 2 Bit 1 Latch */ +#define B1__SHIFT 0x01 /* Port 2 Bit 1 Latch */ +#define B1__LOW 0x00 /* P2.1 is low. Set P2.1 to drive low. */ +#define B1__HIGH 0x02 /* P2.1 is high. Set P2.1 to drive or float high. */ + +/*------------------------------------------------------------------------------ */ +/* P2MDOUT Enums (Port 2 Output Mode @ 0xA6) */ +/*------------------------------------------------------------------------------ */ +#define B0__BMASK 0x01 /* Port 2 Bit 0 Output Mode */ +#define B0__SHIFT 0x00 /* Port 2 Bit 0 Output Mode */ +#define B0__OPEN_DRAIN 0x00 /* P2.0 output is open-drain. */ +#define B0__PUSH_PULL 0x01 /* P2.0 output is push-pull. */ + +#define B1__BMASK 0x02 /* Port 2 Bit 1 Output Mode */ +#define B1__SHIFT 0x01 /* Port 2 Bit 1 Output Mode */ +#define B1__OPEN_DRAIN 0x00 /* P2.1 output is open-drain. */ +#define B1__PUSH_PULL 0x02 /* P2.1 output is push-pull. */ + +/*------------------------------------------------------------------------------ */ +/* XBR0 Enums (Port I/O Crossbar 0 @ 0xE1) */ +/*------------------------------------------------------------------------------ */ +#define URT0E__BMASK 0x01 /* UART I/O Output Enable */ +#define URT0E__SHIFT 0x00 /* UART I/O Output Enable */ +#define URT0E__DISABLED 0x00 /* UART I/O unavailable at Port pin. */ +#define URT0E__ENABLED 0x01 /* UART TX, RX routed to Port pins P0.4 and P0.5. */ + +#define SPI0E__BMASK 0x02 /* SPI I/O Enable */ +#define SPI0E__SHIFT 0x01 /* SPI I/O Enable */ +#define SPI0E__DISABLED 0x00 /* SPI I/O unavailable at Port pins. */ +#define SPI0E__ENABLED 0x02 /* SPI I/O routed to Port pins. The SPI can be assigned either 3 or 4 GPIO pins. */ + +#define SMB0E__BMASK 0x04 /* SMB0 I/O Enable */ +#define SMB0E__SHIFT 0x02 /* SMB0 I/O Enable */ +#define SMB0E__DISABLED 0x00 /* SMBus 0 I/O unavailable at Port pins. */ +#define SMB0E__ENABLED 0x04 /* SMBus 0 I/O routed to Port pins. */ + +#define CP0E__BMASK 0x08 /* Comparator0 Output Enable */ +#define CP0E__SHIFT 0x03 /* Comparator0 Output Enable */ +#define CP0E__DISABLED 0x00 /* CP0 unavailable at Port pin. */ +#define CP0E__ENABLED 0x08 /* CP0 routed to Port pin. */ + +#define CP0AE__BMASK 0x10 /* Comparator0 Asynchronous Output Enable */ +#define CP0AE__SHIFT 0x04 /* Comparator0 Asynchronous Output Enable */ +#define CP0AE__DISABLED 0x00 /* Asynchronous CP0 unavailable at Port pin. */ +#define CP0AE__ENABLED 0x10 /* Asynchronous CP0 routed to Port pin. */ + +#define CP1E__BMASK 0x20 /* Comparator1 Output Enable */ +#define CP1E__SHIFT 0x05 /* Comparator1 Output Enable */ +#define CP1E__DISABLED 0x00 /* CP1 unavailable at Port pin. */ +#define CP1E__ENABLED 0x20 /* CP1 routed to Port pin. */ + +#define CP1AE__BMASK 0x40 /* Comparator1 Asynchronous Output Enable */ +#define CP1AE__SHIFT 0x06 /* Comparator1 Asynchronous Output Enable */ +#define CP1AE__DISABLED 0x00 /* Asynchronous CP1 unavailable at Port pin. */ +#define CP1AE__ENABLED 0x40 /* Asynchronous CP1 routed to Port pin. */ + +#define SYSCKE__BMASK 0x80 /* SYSCLK Output Enable */ +#define SYSCKE__SHIFT 0x07 /* SYSCLK Output Enable */ +#define SYSCKE__DISABLED 0x00 /* SYSCLK unavailable at Port pin. */ +#define SYSCKE__ENABLED 0x80 /* SYSCLK output routed to Port pin. */ + +/*------------------------------------------------------------------------------ */ +/* XBR1 Enums (Port I/O Crossbar 1 @ 0xE2) */ +/*------------------------------------------------------------------------------ */ +#define PCA0ME__FMASK 0x03 /* PCA Module I/O Enable */ +#define PCA0ME__SHIFT 0x00 /* PCA Module I/O Enable */ +#define PCA0ME__DISABLED 0x00 /* All PCA I/O unavailable at Port pins. */ +#define PCA0ME__CEX0 0x01 /* CEX0 routed to Port pin. */ +#define PCA0ME__CEX0_CEX1 0x02 /* CEX0, CEX1 routed to Port pins. */ +#define PCA0ME__CEX0_CEX1_CEX2 0x03 /* CEX0, CEX1, CEX2 routed to Port pins. */ + +#define ECIE__BMASK 0x04 /* PCA0 External Counter Input Enable */ +#define ECIE__SHIFT 0x02 /* PCA0 External Counter Input Enable */ +#define ECIE__DISABLED 0x00 /* ECI unavailable at Port pin. */ +#define ECIE__ENABLED 0x04 /* ECI routed to Port pin. */ + +#define T0E__BMASK 0x08 /* T0 Enable */ +#define T0E__SHIFT 0x03 /* T0 Enable */ +#define T0E__DISABLED 0x00 /* T0 unavailable at Port pin. */ +#define T0E__ENABLED 0x08 /* T0 routed to Port pin. */ + +#define T1E__BMASK 0x10 /* T1 Enable */ +#define T1E__SHIFT 0x04 /* T1 Enable */ +#define T1E__DISABLED 0x00 /* T1 unavailable at Port pin. */ +#define T1E__ENABLED 0x10 /* T1 routed to Port pin. */ + +#define T2E__BMASK 0x20 /* T2 Enable */ +#define T2E__SHIFT 0x05 /* T2 Enable */ +#define T2E__DISABLED 0x00 /* T2 unavailable at Port pin. */ +#define T2E__ENABLED 0x20 /* T2 routed to Port pin. */ + +/*------------------------------------------------------------------------------ */ +/* XBR2 Enums (Port I/O Crossbar 2 @ 0xE3) */ +/*------------------------------------------------------------------------------ */ +#define XBARE__BMASK 0x40 /* Crossbar Enable */ +#define XBARE__SHIFT 0x06 /* Crossbar Enable */ +#define XBARE__DISABLED 0x00 /* Crossbar disabled. */ +#define XBARE__ENABLED 0x40 /* Crossbar enabled. */ + +#define WEAKPUD__BMASK 0x80 /* Port I/O Weak Pullup Disable */ +#define WEAKPUD__SHIFT 0x07 /* Port I/O Weak Pullup Disable */ +#define WEAKPUD__PULL_UPS_ENABLED 0x00 /* Weak Pullups enabled (except for Ports whose I/O are configured for analog mode). */ +#define WEAKPUD__PULL_UPS_DISABLED 0x80 /* Weak Pullups disabled. */ + +/*------------------------------------------------------------------------------ */ +/* ADC0CN1 Enums (ADC0 Control 1 @ 0xB2) */ +/*------------------------------------------------------------------------------ */ +#define ADCMBE__BMASK 0x01 /* Common Mode Buffer Enable */ +#define ADCMBE__SHIFT 0x00 /* Common Mode Buffer Enable */ +#define ADCMBE__CM_BUFFER_DISABLED 0x00 /* Disable the common mode buffer. This setting should be used only if the tracking time of the signal is greater than 1.5 us. */ +#define ADCMBE__CM_BUFFER_ENABLED 0x01 /* Enable the common mode buffer. This setting should be used in most cases, and will give the best dynamic ADC performance. The common mode buffer must be enabled if signal tracking time is less than or equal to 1.5 us. */ + +/*------------------------------------------------------------------------------ */ +/* ADC0GTH Enums (ADC0 Greater-Than High Byte @ 0xC4) */ +/*------------------------------------------------------------------------------ */ +#define ADC0GTH__FMASK 0xFF /* Greater-Than High Byte */ +#define ADC0GTH__SHIFT 0x00 /* Greater-Than High Byte */ + +/*------------------------------------------------------------------------------ */ +/* ADC0GTL Enums (ADC0 Greater-Than Low Byte @ 0xC3) */ +/*------------------------------------------------------------------------------ */ +#define ADC0GTL__FMASK 0xFF /* Greater-Than Low Byte */ +#define ADC0GTL__SHIFT 0x00 /* Greater-Than Low Byte */ + +/*------------------------------------------------------------------------------ */ +/* ADC0H Enums (ADC0 Data Word High Byte @ 0xBE) */ +/*------------------------------------------------------------------------------ */ +#define ADC0H__FMASK 0xFF /* Data Word High Byte */ +#define ADC0H__SHIFT 0x00 /* Data Word High Byte */ + +/*------------------------------------------------------------------------------ */ +/* ADC0L Enums (ADC0 Data Word Low Byte @ 0xBD) */ +/*------------------------------------------------------------------------------ */ +#define ADC0L__FMASK 0xFF /* Data Word Low Byte */ +#define ADC0L__SHIFT 0x00 /* Data Word Low Byte */ + +/*------------------------------------------------------------------------------ */ +/* ADC0LTH Enums (ADC0 Less-Than High Byte @ 0xC6) */ +/*------------------------------------------------------------------------------ */ +#define ADC0LTH__FMASK 0xFF /* Less-Than High Byte */ +#define ADC0LTH__SHIFT 0x00 /* Less-Than High Byte */ + +/*------------------------------------------------------------------------------ */ +/* ADC0LTL Enums (ADC0 Less-Than Low Byte @ 0xC5) */ +/*------------------------------------------------------------------------------ */ +#define ADC0LTL__FMASK 0xFF /* Less-Than Low Byte */ +#define ADC0LTL__SHIFT 0x00 /* Less-Than Low Byte */ + +/*------------------------------------------------------------------------------ */ +/* ADC0MX Enums (ADC0 Multiplexer Selection @ 0xBB) */ +/*------------------------------------------------------------------------------ */ +#define ADC0MX__FMASK 0x1F /* AMUX0 Positive Input Selection */ +#define ADC0MX__SHIFT 0x00 /* AMUX0 Positive Input Selection */ +#define ADC0MX__ADC0P0 0x00 /* Select ADC0.0. */ +#define ADC0MX__ADC0P1 0x01 /* Select ADC0.1. */ +#define ADC0MX__ADC0P2 0x02 /* Select ADC0.2. */ +#define ADC0MX__ADC0P3 0x03 /* Select ADC0.3. */ +#define ADC0MX__ADC0P4 0x04 /* Select ADC0.4. */ +#define ADC0MX__ADC0P5 0x05 /* Select ADC0.5. */ +#define ADC0MX__ADC0P6 0x06 /* Select ADC0.6. */ +#define ADC0MX__ADC0P7 0x07 /* Select ADC0.7. */ +#define ADC0MX__ADC0P8 0x08 /* Select ADC0.8. */ +#define ADC0MX__ADC0P9 0x09 /* Select ADC0.9. */ +#define ADC0MX__ADC0P10 0x0A /* Select ADC0.10. */ +#define ADC0MX__ADC0P11 0x0B /* Select ADC0.11. */ +#define ADC0MX__ADC0P12 0x0C /* Select ADC0.12. */ +#define ADC0MX__ADC0P13 0x0D /* Select ADC0.13. */ +#define ADC0MX__ADC0P14 0x0E /* Select ADC0.14. */ +#define ADC0MX__ADC0P15 0x0F /* Select ADC0.15. */ +#define ADC0MX__TEMP 0x10 /* Select ADC0.16. */ +#define ADC0MX__LDO_OUT 0x11 /* Select ADC0.17. */ +#define ADC0MX__VDD 0x12 /* Select ADC0.18. */ +#define ADC0MX__GND 0x13 /* Select ADC0.19. */ +#define ADC0MX__NONE 0x1F /* No input selected. */ + +/*------------------------------------------------------------------------------ */ +/* ADC0PWR Enums (ADC0 Power Control @ 0xDF) */ +/*------------------------------------------------------------------------------ */ +#define ADPWR__FMASK 0x0F /* Burst Mode Power Up Time */ +#define ADPWR__SHIFT 0x00 /* Burst Mode Power Up Time */ + +#define ADLPM__BMASK 0x10 /* Low Power Mode Enable */ +#define ADLPM__SHIFT 0x04 /* Low Power Mode Enable */ +#define ADLPM__LP_BUFFER_DISABLED 0x00 /* Disable low power mode. */ +#define ADLPM__LP_BUFFER_ENABLED 0x10 /* Enable low power mode (requires extended tracking time). */ + +#define ADMXLP__BMASK 0x20 /* Mux and Reference Low Power Mode Enable */ +#define ADMXLP__SHIFT 0x05 /* Mux and Reference Low Power Mode Enable */ +#define ADMXLP__LP_MUX_VREF_DISABLED 0x00 /* Low power mode disabled. */ +#define ADMXLP__LP_MUX_VREF_ENABLED 0x20 /* Low power mode enabled (SAR clock < 4 MHz). */ + +#define ADBIAS__FMASK 0xC0 /* Bias Power Select */ +#define ADBIAS__SHIFT 0x06 /* Bias Power Select */ +#define ADBIAS__MODE0 0x00 /* Select bias current mode 0. Recommended to use modes 1, 2, or 3. */ +#define ADBIAS__MODE1 0x40 /* Select bias current mode 1 (SARCLK <= 16 MHz). */ +#define ADBIAS__MODE2 0x80 /* Select bias current mode 2. */ +#define ADBIAS__MODE3 0xC0 /* Select bias current mode 3 (SARCLK <= 4 MHz). */ + +/*------------------------------------------------------------------------------ */ +/* ADC0TK Enums (ADC0 Burst Mode Track Time @ 0xB9) */ +/*------------------------------------------------------------------------------ */ +#define ADTK__FMASK 0x3F /* Burst Mode Tracking Time */ +#define ADTK__SHIFT 0x00 /* Burst Mode Tracking Time */ + +#define AD12SM__BMASK 0x80 /* 12-Bit Sampling Mode */ +#define AD12SM__SHIFT 0x07 /* 12-Bit Sampling Mode */ +#define AD12SM__SAMPLE_FOUR 0x00 /* The ADC will re-track and sample the input four times during a 12-bit conversion. */ +#define AD12SM__SAMPLE_ONCE 0x80 /* The ADC will sample the input once at the beginning of each 12-bit conversion. The ADTK field can be set to 63 to maximize throughput. */ + +/*------------------------------------------------------------------------------ */ +/* REF0CN Enums (Voltage Reference Control @ 0xD1) */ +/*------------------------------------------------------------------------------ */ +#define TEMPE__BMASK 0x04 /* Temperature Sensor Enable */ +#define TEMPE__SHIFT 0x02 /* Temperature Sensor Enable */ +#define TEMPE__TEMP_DISABLED 0x00 /* Disable the Temperature Sensor. */ +#define TEMPE__TEMP_ENABLED 0x04 /* Enable the Temperature Sensor. */ + +#define REFSL__FMASK 0x18 /* Voltage Reference Select */ +#define REFSL__SHIFT 0x03 /* Voltage Reference Select */ +#define REFSL__VREF_PIN 0x00 /* The ADC0 voltage reference is the P0.0/VREF pin. */ +#define REFSL__VDD_PIN 0x08 /* The ADC0 voltage reference is the VDD pin. */ +#define REFSL__INTERNAL_LDO 0x10 /* The ADC0 voltage reference is the internal 1.8 V digital supply voltage. */ +#define REFSL__INTERNAL_VREF 0x18 /* The ADC0 voltage reference is the internal voltage reference. */ + +#define GNDSL__BMASK 0x20 /* Analog Ground Reference */ +#define GNDSL__SHIFT 0x05 /* Analog Ground Reference */ +#define GNDSL__GND_PIN 0x00 /* The ADC0 ground reference is the GND pin. */ +#define GNDSL__AGND_PIN 0x20 /* The ADC0 ground reference is the P0.1/AGND pin. */ + +#define IREFLVL__BMASK 0x80 /* Internal Voltage Reference Level */ +#define IREFLVL__SHIFT 0x07 /* Internal Voltage Reference Level */ +#define IREFLVL__1P65 0x00 /* The internal reference operates at 1.65 V nominal. */ +#define IREFLVL__2P4 0x80 /* The internal reference operates at 2.4 V nominal. */ + +/*------------------------------------------------------------------------------ */ +/* REG0CN Enums (Voltage Regulator 0 Control @ 0xC9) */ +/*------------------------------------------------------------------------------ */ +#define STOPCF__BMASK 0x08 /* Stop Mode Configuration */ +#define STOPCF__SHIFT 0x03 /* Stop Mode Configuration */ +#define STOPCF__ACTIVE 0x00 /* Regulator is still active in stop mode. Any enabled reset source will reset the device. */ +#define STOPCF__SHUTDOWN 0x08 /* Regulator is shut down in stop mode. Only the RSTb pin or power cycle can reset the device. */ + +/*------------------------------------------------------------------------------ */ +/* CLKSEL Enums (Clock Select @ 0xA9) */ +/*------------------------------------------------------------------------------ */ +#define CLKSL__FMASK 0x03 /* Clock Source Select */ +#define CLKSL__SHIFT 0x00 /* Clock Source Select */ +#define CLKSL__HFOSC 0x00 /* Clock derived from the Internal High-Frequency Oscillator. */ +#define CLKSL__EXTOSC 0x01 /* Clock derived from the External CMOS clock circuit. */ +#define CLKSL__LFOSC 0x02 /* Clock derived from the Internal Low-Frequency Oscillator. */ + +#define CLKDIV__FMASK 0x70 /* Clock Source Divider */ +#define CLKDIV__SHIFT 0x04 /* Clock Source Divider */ +#define CLKDIV__SYSCLK_DIV_1 0x00 /* SYSCLK is equal to selected clock source divided by 1. */ +#define CLKDIV__SYSCLK_DIV_2 0x10 /* SYSCLK is equal to selected clock source divided by 2. */ +#define CLKDIV__SYSCLK_DIV_4 0x20 /* SYSCLK is equal to selected clock source divided by 4. */ +#define CLKDIV__SYSCLK_DIV_8 0x30 /* SYSCLK is equal to selected clock source divided by 8. */ +#define CLKDIV__SYSCLK_DIV_16 0x40 /* SYSCLK is equal to selected clock source divided by 16. */ +#define CLKDIV__SYSCLK_DIV_32 0x50 /* SYSCLK is equal to selected clock source divided by 32. */ +#define CLKDIV__SYSCLK_DIV_64 0x60 /* SYSCLK is equal to selected clock source divided by 64. */ +#define CLKDIV__SYSCLK_DIV_128 0x70 /* SYSCLK is equal to selected clock source divided by 128. */ + +/*------------------------------------------------------------------------------ */ +/* TMR2CN0 Enums (Timer 2 Control 0 @ 0xC8) */ +/*------------------------------------------------------------------------------ */ +#define T2XCLK__BMASK 0x01 /* Timer 2 External Clock Select */ +#define T2XCLK__SHIFT 0x00 /* Timer 2 External Clock Select */ +#define T2XCLK__SYSCLK_DIV_12 0x00 /* Timer 2 clock is the system clock divided by 12. */ +#define T2XCLK__EXTOSC_DIV_8 0x01 /* Timer 2 clock is the external oscillator divided by 8 (synchronized with SYSCLK). */ + +#define TR2__BMASK 0x04 /* Timer 2 Run Control */ +#define TR2__SHIFT 0x02 /* Timer 2 Run Control */ +#define TR2__STOP 0x00 /* Stop Timer 2. */ +#define TR2__RUN 0x04 /* Start Timer 2 running. */ + +#define T2SPLIT__BMASK 0x08 /* Timer 2 Split Mode Enable */ +#define T2SPLIT__SHIFT 0x03 /* Timer 2 Split Mode Enable */ +#define T2SPLIT__16_BIT_RELOAD 0x00 /* Timer 2 operates in 16-bit auto-reload mode. */ +#define T2SPLIT__8_BIT_RELOAD 0x08 /* Timer 2 operates as two 8-bit auto-reload timers. */ + +#define TF2CEN__BMASK 0x10 /* Timer 2 Capture Enable */ +#define TF2CEN__SHIFT 0x04 /* Timer 2 Capture Enable */ +#define TF2CEN__DISABLED 0x00 /* Disable capture mode. */ +#define TF2CEN__ENABLED 0x10 /* Enable capture mode. */ + +#define TF2LEN__BMASK 0x20 /* Timer 2 Low Byte Interrupt Enable */ +#define TF2LEN__SHIFT 0x05 /* Timer 2 Low Byte Interrupt Enable */ +#define TF2LEN__DISABLED 0x00 /* Disable low byte interrupts. */ +#define TF2LEN__ENABLED 0x20 /* Enable low byte interrupts. */ + +#define TF2L__BMASK 0x40 /* Timer 2 Low Byte Overflow Flag */ +#define TF2L__SHIFT 0x06 /* Timer 2 Low Byte Overflow Flag */ +#define TF2L__NOT_SET 0x00 /* Timer 2 low byte did not overflow. */ +#define TF2L__SET 0x40 /* Timer 2 low byte overflowed. */ + +#define TF2H__BMASK 0x80 /* Timer 2 High Byte Overflow Flag */ +#define TF2H__SHIFT 0x07 /* Timer 2 High Byte Overflow Flag */ +#define TF2H__NOT_SET 0x00 /* Timer 2 8-bit high byte or 16-bit value did not overflow. */ +#define TF2H__SET 0x80 /* Timer 2 8-bit high byte or 16-bit value overflowed. */ + +/*------------------------------------------------------------------------------ */ +/* TMR3CN0 Enums (Timer 3 Control 0 @ 0x91) */ +/*------------------------------------------------------------------------------ */ +#define T3XCLK__BMASK 0x01 /* Timer 3 External Clock Select */ +#define T3XCLK__SHIFT 0x00 /* Timer 3 External Clock Select */ +#define T3XCLK__SYSCLK_DIV_12 0x00 /* Timer 3 clock is the system clock divided by 12. */ +#define T3XCLK__EXTOSC_DIV_8 0x01 /* Timer 3 clock is the external oscillator divided by 8 (synchronized with SYSCLK). */ + +#define TR3__BMASK 0x04 /* Timer 3 Run Control */ +#define TR3__SHIFT 0x02 /* Timer 3 Run Control */ +#define TR3__STOP 0x00 /* Stop Timer 3. */ +#define TR3__RUN 0x04 /* Start Timer 3 running. */ + +#define T3SPLIT__BMASK 0x08 /* Timer 3 Split Mode Enable */ +#define T3SPLIT__SHIFT 0x03 /* Timer 3 Split Mode Enable */ +#define T3SPLIT__16_BIT_RELOAD 0x00 /* Timer 3 operates in 16-bit auto-reload mode. */ +#define T3SPLIT__8_BIT_RELOAD 0x08 /* Timer 3 operates as two 8-bit auto-reload timers. */ + +#define TF3CEN__BMASK 0x10 /* Timer 3 Capture Enable */ +#define TF3CEN__SHIFT 0x04 /* Timer 3 Capture Enable */ +#define TF3CEN__DISABLED 0x00 /* Disable capture mode. */ +#define TF3CEN__ENABLED 0x10 /* Enable capture mode. */ + +#define TF3LEN__BMASK 0x20 /* Timer 3 Low Byte Interrupt Enable */ +#define TF3LEN__SHIFT 0x05 /* Timer 3 Low Byte Interrupt Enable */ +#define TF3LEN__DISABLED 0x00 /* Disable low byte interrupts. */ +#define TF3LEN__ENABLED 0x20 /* Enable low byte interrupts. */ + +#define TF3L__BMASK 0x40 /* Timer 3 Low Byte Overflow Flag */ +#define TF3L__SHIFT 0x06 /* Timer 3 Low Byte Overflow Flag */ +#define TF3L__NOT_SET 0x00 /* Timer 3 low byte did not overflow. */ +#define TF3L__SET 0x40 /* Timer 3 low byte overflowed. */ + +#define TF3H__BMASK 0x80 /* Timer 3 High Byte Overflow Flag */ +#define TF3H__SHIFT 0x07 /* Timer 3 High Byte Overflow Flag */ +#define TF3H__NOT_SET 0x00 /* Timer 3 8-bit high byte or 16-bit value did not overflow. */ +#define TF3H__SET 0x80 /* Timer 3 8-bit high byte or 16-bit value overflowed. */ + +/*------------------------------------------------------------------------------ */ +/* PCA0CPM0 Enums (PCA Channel 0 Capture/Compare Mode @ 0xDA) */ +/*------------------------------------------------------------------------------ */ +#define ECCF__BMASK 0x01 /* Channel 0 Capture/Compare Flag Interrupt Enable */ +#define ECCF__SHIFT 0x00 /* Channel 0 Capture/Compare Flag Interrupt Enable */ +#define ECCF__DISABLED 0x00 /* Disable CCF0 interrupts. */ +#define ECCF__ENABLED 0x01 /* Enable a Capture/Compare Flag interrupt request when CCF0 is set. */ + +#define PWM__BMASK 0x02 /* Channel 0 Pulse Width Modulation Mode Enable */ +#define PWM__SHIFT 0x01 /* Channel 0 Pulse Width Modulation Mode Enable */ +#define PWM__DISABLED 0x00 /* Disable PWM function. */ +#define PWM__ENABLED 0x02 /* Enable PWM function. */ + +#define TOG__BMASK 0x04 /* Channel 0 Toggle Function Enable */ +#define TOG__SHIFT 0x02 /* Channel 0 Toggle Function Enable */ +#define TOG__DISABLED 0x00 /* Disable toggle function. */ +#define TOG__ENABLED 0x04 /* Enable toggle function. */ + +#define MAT__BMASK 0x08 /* Channel 0 Match Function Enable */ +#define MAT__SHIFT 0x03 /* Channel 0 Match Function Enable */ +#define MAT__DISABLED 0x00 /* Disable match function. */ +#define MAT__ENABLED 0x08 /* Enable match function. */ + +#define CAPN__BMASK 0x10 /* Channel 0 Capture Negative Function Enable */ +#define CAPN__SHIFT 0x04 /* Channel 0 Capture Negative Function Enable */ +#define CAPN__DISABLED 0x00 /* Disable negative edge capture. */ +#define CAPN__ENABLED 0x10 /* Enable negative edge capture. */ + +#define CAPP__BMASK 0x20 /* Channel 0 Capture Positive Function Enable */ +#define CAPP__SHIFT 0x05 /* Channel 0 Capture Positive Function Enable */ +#define CAPP__DISABLED 0x00 /* Disable positive edge capture. */ +#define CAPP__ENABLED 0x20 /* Enable positive edge capture. */ + +#define ECOM__BMASK 0x40 /* Channel 0 Comparator Function Enable */ +#define ECOM__SHIFT 0x06 /* Channel 0 Comparator Function Enable */ +#define ECOM__DISABLED 0x00 /* Disable comparator function. */ +#define ECOM__ENABLED 0x40 /* Enable comparator function. */ + +#define PWM16__BMASK 0x80 /* Channel 0 16-bit Pulse Width Modulation Enable */ +#define PWM16__SHIFT 0x07 /* Channel 0 16-bit Pulse Width Modulation Enable */ +#define PWM16__8_BIT 0x00 /* 8 to 11-bit PWM selected. */ +#define PWM16__16_BIT 0x80 /* 16-bit PWM selected. */ + +/*------------------------------------------------------------------------------ */ +/* PCA0CPM1 Enums (PCA Channel 1 Capture/Compare Mode @ 0xDB) */ +/*------------------------------------------------------------------------------ */ +#define ECCF__BMASK 0x01 /* Channel 1 Capture/Compare Flag Interrupt Enable */ +#define ECCF__SHIFT 0x00 /* Channel 1 Capture/Compare Flag Interrupt Enable */ +#define ECCF__DISABLED 0x00 /* Disable CCF1 interrupts. */ +#define ECCF__ENABLED 0x01 /* Enable a Capture/Compare Flag interrupt request when CCF1 is set. */ + +#define PWM__BMASK 0x02 /* Channel 1 Pulse Width Modulation Mode Enable */ +#define PWM__SHIFT 0x01 /* Channel 1 Pulse Width Modulation Mode Enable */ +#define PWM__DISABLED 0x00 /* Disable PWM function. */ +#define PWM__ENABLED 0x02 /* Enable PWM function. */ + +#define TOG__BMASK 0x04 /* Channel 1 Toggle Function Enable */ +#define TOG__SHIFT 0x02 /* Channel 1 Toggle Function Enable */ +#define TOG__DISABLED 0x00 /* Disable toggle function. */ +#define TOG__ENABLED 0x04 /* Enable toggle function. */ + +#define MAT__BMASK 0x08 /* Channel 1 Match Function Enable */ +#define MAT__SHIFT 0x03 /* Channel 1 Match Function Enable */ +#define MAT__DISABLED 0x00 /* Disable match function. */ +#define MAT__ENABLED 0x08 /* Enable match function. */ + +#define CAPN__BMASK 0x10 /* Channel 1 Capture Negative Function Enable */ +#define CAPN__SHIFT 0x04 /* Channel 1 Capture Negative Function Enable */ +#define CAPN__DISABLED 0x00 /* Disable negative edge capture. */ +#define CAPN__ENABLED 0x10 /* Enable negative edge capture. */ + +#define CAPP__BMASK 0x20 /* Channel 1 Capture Positive Function Enable */ +#define CAPP__SHIFT 0x05 /* Channel 1 Capture Positive Function Enable */ +#define CAPP__DISABLED 0x00 /* Disable positive edge capture. */ +#define CAPP__ENABLED 0x20 /* Enable positive edge capture. */ + +#define ECOM__BMASK 0x40 /* Channel 1 Comparator Function Enable */ +#define ECOM__SHIFT 0x06 /* Channel 1 Comparator Function Enable */ +#define ECOM__DISABLED 0x00 /* Disable comparator function. */ +#define ECOM__ENABLED 0x40 /* Enable comparator function. */ + +#define PWM16__BMASK 0x80 /* Channel 1 16-bit Pulse Width Modulation Enable */ +#define PWM16__SHIFT 0x07 /* Channel 1 16-bit Pulse Width Modulation Enable */ +#define PWM16__8_BIT 0x00 /* 8 to 11-bit PWM selected. */ +#define PWM16__16_BIT 0x80 /* 16-bit PWM selected. */ + +/*------------------------------------------------------------------------------ */ +/* PCA0CPM2 Enums (PCA Channel 2 Capture/Compare Mode @ 0xDC) */ +/*------------------------------------------------------------------------------ */ +#define ECCF__BMASK 0x01 /* Channel 2 Capture/Compare Flag Interrupt Enable */ +#define ECCF__SHIFT 0x00 /* Channel 2 Capture/Compare Flag Interrupt Enable */ +#define ECCF__DISABLED 0x00 /* Disable CCF2 interrupts. */ +#define ECCF__ENABLED 0x01 /* Enable a Capture/Compare Flag interrupt request */ +/* when CCF2 is set. */ + +#define PWM__BMASK 0x02 /* Channel 2 Pulse Width Modulation Mode Enable */ +#define PWM__SHIFT 0x01 /* Channel 2 Pulse Width Modulation Mode Enable */ +#define PWM__DISABLED 0x00 /* Disable PWM function. */ +#define PWM__ENABLED 0x02 /* Enable PWM function. */ + +#define TOG__BMASK 0x04 /* Channel 2 Toggle Function Enable */ +#define TOG__SHIFT 0x02 /* Channel 2 Toggle Function Enable */ +#define TOG__DISABLED 0x00 /* Disable toggle function. */ +#define TOG__ENABLED 0x04 /* Enable toggle function. */ + +#define MAT__BMASK 0x08 /* Channel 2 Match Function Enable */ +#define MAT__SHIFT 0x03 /* Channel 2 Match Function Enable */ +#define MAT__DISABLED 0x00 /* Disable match function. */ +#define MAT__ENABLED 0x08 /* Enable match function. */ + +#define CAPN__BMASK 0x10 /* Channel 2 Capture Negative Function Enable */ +#define CAPN__SHIFT 0x04 /* Channel 2 Capture Negative Function Enable */ +#define CAPN__DISABLED 0x00 /* Disable negative edge capture. */ +#define CAPN__ENABLED 0x10 /* Enable negative edge capture. */ + +#define CAPP__BMASK 0x20 /* Channel 2 Capture Positive Function Enable */ +#define CAPP__SHIFT 0x05 /* Channel 2 Capture Positive Function Enable */ +#define CAPP__DISABLED 0x00 /* Disable positive edge capture. */ +#define CAPP__ENABLED 0x20 /* Enable positive edge capture. */ + +#define ECOM__BMASK 0x40 /* Channel 2 Comparator Function Enable */ +#define ECOM__SHIFT 0x06 /* Channel 2 Comparator Function Enable */ +#define ECOM__DISABLED 0x00 /* Disable comparator function. */ +#define ECOM__ENABLED 0x40 /* Enable comparator function. */ + +#define PWM16__BMASK 0x80 /* Channel 2 16-bit Pulse Width Modulation Enable */ +#define PWM16__SHIFT 0x07 /* Channel 2 16-bit Pulse Width Modulation Enable */ +#define PWM16__8_BIT 0x00 /* 8 to 11-bit PWM selected. */ +#define PWM16__16_BIT 0x80 /* 16-bit PWM selected. */ + +/*------------------------------------------------------------------------------ */ +/* PCA0CENT Enums (PCA Center Alignment Enable @ 0x9E) */ +/*------------------------------------------------------------------------------ */ +#define CEX0CEN__BMASK 0x01 /* CEX0 Center Alignment Enable */ +#define CEX0CEN__SHIFT 0x00 /* CEX0 Center Alignment Enable */ +#define CEX0CEN__EDGE 0x00 /* Edge-aligned. */ +#define CEX0CEN__CENTER 0x01 /* Center-aligned. */ + +#define CEX1CEN__BMASK 0x02 /* CEX1 Center Alignment Enable */ +#define CEX1CEN__SHIFT 0x01 /* CEX1 Center Alignment Enable */ +#define CEX1CEN__EDGE 0x00 /* Edge-aligned. */ +#define CEX1CEN__CENTER 0x02 /* Center-aligned. */ + +#define CEX2CEN__BMASK 0x04 /* CEX2 Center Alignment Enable */ +#define CEX2CEN__SHIFT 0x02 /* CEX2 Center Alignment Enable */ +#define CEX2CEN__EDGE 0x00 /* Edge-aligned. */ +#define CEX2CEN__CENTER 0x04 /* Center-aligned. */ + +/*------------------------------------------------------------------------------ */ +/* PCA0CLR Enums (PCA Comparator Clear Control @ 0x9C) */ +/*------------------------------------------------------------------------------ */ +#define CPCE0__BMASK 0x01 /* Comparator Clear Enable for CEX0 */ +#define CPCE0__SHIFT 0x00 /* Comparator Clear Enable for CEX0 */ +#define CPCE0__DISABLED 0x00 /* Disable the comparator clear function on PCA channel 0. */ +#define CPCE0__ENABLED 0x01 /* Enable the comparator clear function on PCA channel 0. */ + +#define CPCE1__BMASK 0x02 /* Comparator Clear Enable for CEX1 */ +#define CPCE1__SHIFT 0x01 /* Comparator Clear Enable for CEX1 */ +#define CPCE1__DISABLED 0x00 /* Disable the comparator clear function on PCA channel 1. */ +#define CPCE1__ENABLED 0x02 /* Enable the comparator clear function on PCA channel 1. */ + +#define CPCE2__BMASK 0x04 /* Comparator Clear Enable for CEX2 */ +#define CPCE2__SHIFT 0x02 /* Comparator Clear Enable for CEX2 */ +#define CPCE2__DISABLED 0x00 /* Disable the comparator clear function on PCA channel 2. */ +#define CPCE2__ENABLED 0x04 /* Enable the comparator clear function on PCA channel 2. */ + +#define CPCPOL__BMASK 0x80 /* Comparator Clear Polarity */ +#define CPCPOL__SHIFT 0x07 /* Comparator Clear Polarity */ +#define CPCPOL__LOW 0x00 /* PCA channel(s) will be cleared when comparator result goes logic low. */ +#define CPCPOL__HIGH 0x80 /* PCA channel(s) will be cleared when comparator result goes logic high. */ + +/*------------------------------------------------------------------------------ */ +/* PCA0CN0 Enums (PCA Control @ 0xD8) */ +/*------------------------------------------------------------------------------ */ +#define CCF0__BMASK 0x01 /* PCA Module 0 Capture/Compare Flag */ +#define CCF0__SHIFT 0x00 /* PCA Module 0 Capture/Compare Flag */ +#define CCF0__NOT_SET 0x00 /* A match or capture did not occur on channel 0. */ +#define CCF0__SET 0x01 /* A match or capture occurred on channel 0. */ + +#define CCF1__BMASK 0x02 /* PCA Module 1 Capture/Compare Flag */ +#define CCF1__SHIFT 0x01 /* PCA Module 1 Capture/Compare Flag */ +#define CCF1__NOT_SET 0x00 /* A match or capture did not occur on channel 1. */ +#define CCF1__SET 0x02 /* A match or capture occurred on channel 1. */ + +#define CCF2__BMASK 0x04 /* PCA Module 2 Capture/Compare Flag */ +#define CCF2__SHIFT 0x02 /* PCA Module 2 Capture/Compare Flag */ +#define CCF2__NOT_SET 0x00 /* A match or capture did not occur on channel 2. */ +#define CCF2__SET 0x04 /* A match or capture occurred on channel 2. */ + +#define CR__BMASK 0x40 /* PCA Counter/Timer Run Control */ +#define CR__SHIFT 0x06 /* PCA Counter/Timer Run Control */ +#define CR__STOP 0x00 /* Stop the PCA Counter/Timer. */ +#define CR__RUN 0x40 /* Start the PCA Counter/Timer running. */ + +#define CF__BMASK 0x80 /* PCA Counter/Timer Overflow Flag */ +#define CF__SHIFT 0x07 /* PCA Counter/Timer Overflow Flag */ +#define CF__NOT_SET 0x00 /* The PCA counter/timer did not overflow. */ +#define CF__SET 0x80 /* The PCA counter/timer overflowed. */ + +/*------------------------------------------------------------------------------ */ +/* PCA0MD Enums (PCA Mode @ 0xD9) */ +/*------------------------------------------------------------------------------ */ +#define ECF__BMASK 0x01 /* PCA Counter/Timer Overflow Interrupt Enable */ +#define ECF__SHIFT 0x00 /* PCA Counter/Timer Overflow Interrupt Enable */ +#define ECF__OVF_INT_DISABLED 0x00 /* Disable the CF interrupt. */ +#define ECF__OVF_INT_ENABLED 0x01 /* Enable a PCA Counter/Timer Overflow interrupt request when CF is set. */ + +#define CPS__FMASK 0x0E /* PCA Counter/Timer Pulse Select */ +#define CPS__SHIFT 0x01 /* PCA Counter/Timer Pulse Select */ +#define CPS__SYSCLK_DIV_12 0x00 /* System clock divided by 12. */ +#define CPS__SYSCLK_DIV_4 0x02 /* System clock divided by 4. */ +#define CPS__T0_OVERFLOW 0x04 /* Timer 0 overflow. */ +#define CPS__ECI 0x06 /* High-to-low transitions on ECI (max rate = system clock divided by 4). */ +#define CPS__SYSCLK 0x08 /* System clock. */ +#define CPS__EXTOSC_DIV_8 0x0A /* External clock divided by 8 (synchronized with the system clock). */ +#define CPS__LFOSC_DIV_8 0x0C /* Low frequency oscillator divided by 8. */ + +#define CIDL__BMASK 0x80 /* PCA Counter/Timer Idle Control */ +#define CIDL__SHIFT 0x07 /* PCA Counter/Timer Idle Control */ +#define CIDL__NORMAL 0x00 /* PCA continues to function normally while the system controller is in Idle Mode. */ +#define CIDL__SUSPEND 0x80 /* PCA operation is suspended while the system controller is in Idle Mode. */ + +/*------------------------------------------------------------------------------ */ +/* PCA0POL Enums (PCA Output Polarity @ 0x96) */ +/*------------------------------------------------------------------------------ */ +#define CEX0POL__BMASK 0x01 /* CEX0 Output Polarity */ +#define CEX0POL__SHIFT 0x00 /* CEX0 Output Polarity */ +#define CEX0POL__DEFAULT 0x00 /* Use default polarity. */ +#define CEX0POL__INVERT 0x01 /* Invert polarity. */ + +#define CEX1POL__BMASK 0x02 /* CEX1 Output Polarity */ +#define CEX1POL__SHIFT 0x01 /* CEX1 Output Polarity */ +#define CEX1POL__DEFAULT 0x00 /* Use default polarity. */ +#define CEX1POL__INVERT 0x02 /* Invert polarity. */ + +#define CEX2POL__BMASK 0x04 /* CEX2 Output Polarity */ +#define CEX2POL__SHIFT 0x02 /* CEX2 Output Polarity */ +#define CEX2POL__DEFAULT 0x00 /* Use default polarity. */ +#define CEX2POL__INVERT 0x04 /* Invert polarity. */ + +/*------------------------------------------------------------------------------ */ +/* PCA0PWM Enums (PCA PWM Configuration @ 0xF7) */ +/*------------------------------------------------------------------------------ */ +#define CLSEL__FMASK 0x07 /* Cycle Length Select */ +#define CLSEL__SHIFT 0x00 /* Cycle Length Select */ +#define CLSEL__8_BITS 0x00 /* 8 bits. */ +#define CLSEL__9_BITS 0x01 /* 9 bits. */ +#define CLSEL__10_BITS 0x02 /* 10 bits. */ +#define CLSEL__11_BITS 0x03 /* 11 bits. */ + +#define COVF__BMASK 0x20 /* Cycle Overflow Flag */ +#define COVF__SHIFT 0x05 /* Cycle Overflow Flag */ +#define COVF__NO_OVERFLOW 0x00 /* No overflow has occurred since the last time this bit was cleared. */ +#define COVF__OVERFLOW 0x20 /* An overflow has occurred since the last time this bit was cleared. */ + +#define ECOV__BMASK 0x40 /* Cycle Overflow Interrupt Enable */ +#define ECOV__SHIFT 0x06 /* Cycle Overflow Interrupt Enable */ +#define ECOV__COVF_MASK_DISABLED 0x00 /* COVF will not generate PCA interrupts. */ +#define ECOV__COVF_MASK_ENABLED 0x40 /* A PCA interrupt will be generated when COVF is set. */ + +#define ARSEL__BMASK 0x80 /* Auto-Reload Register Select */ +#define ARSEL__SHIFT 0x07 /* Auto-Reload Register Select */ +#define ARSEL__CAPTURE_COMPARE 0x00 /* Read/Write Capture/Compare Registers at PCA0CPHn and PCA0CPLn. */ +#define ARSEL__AUTORELOAD 0x80 /* Read/Write Auto-Reload Registers at PCA0CPHn and PCA0CPLn. */ + +/*------------------------------------------------------------------------------ */ +/* SPI0CFG Enums (SPI0 Configuration @ 0xA1) */ +/*------------------------------------------------------------------------------ */ +#define RXBMT__BMASK 0x01 /* Receive Buffer Empty */ +#define RXBMT__SHIFT 0x00 /* Receive Buffer Empty */ +#define RXBMT__NOT_SET 0x00 /* New data is available in the receive buffer (Slave mode). */ +#define RXBMT__SET 0x01 /* No new data in the receive buffer (Slave mode). */ + +#define SRMT__BMASK 0x02 /* Shift Register Empty */ +#define SRMT__SHIFT 0x01 /* Shift Register Empty */ +#define SRMT__NOT_SET 0x00 /* The shift register is not empty. */ +#define SRMT__SET 0x02 /* The shift register is empty. */ + +#define NSSIN__BMASK 0x04 /* NSS Instantaneous Pin Input */ +#define NSSIN__SHIFT 0x02 /* NSS Instantaneous Pin Input */ +#define NSSIN__LOW 0x00 /* The NSS pin is low. */ +#define NSSIN__HIGH 0x04 /* The NSS pin is high. */ + +#define SLVSEL__BMASK 0x08 /* Slave Selected Flag */ +#define SLVSEL__SHIFT 0x03 /* Slave Selected Flag */ +#define SLVSEL__NOT_SELECTED 0x00 /* The Slave is not selected (NSS is high). */ +#define SLVSEL__SELECTED 0x08 /* The Slave is selected (NSS is low). */ + +#define CKPOL__BMASK 0x10 /* SPI0 Clock Polarity */ +#define CKPOL__SHIFT 0x04 /* SPI0 Clock Polarity */ +#define CKPOL__IDLE_LOW 0x00 /* SCK line low in idle state. */ +#define CKPOL__IDLE_HIGH 0x10 /* SCK line high in idle state. */ + +#define CKPHA__BMASK 0x20 /* SPI0 Clock Phase */ +#define CKPHA__SHIFT 0x05 /* SPI0 Clock Phase */ +#define CKPHA__DATA_CENTERED_FIRST 0x00 /* Data centered on first edge of SCK period. */ +#define CKPHA__DATA_CENTERED_SECOND 0x20 /* Data centered on second edge of SCK period. */ + +#define MSTEN__BMASK 0x40 /* Master Mode Enable */ +#define MSTEN__SHIFT 0x06 /* Master Mode Enable */ +#define MSTEN__MASTER_DISABLED 0x00 /* Disable master mode. Operate in slave mode. */ +#define MSTEN__MASTER_ENABLED 0x40 /* Enable master mode. Operate as a master. */ + +#define SPIBSY__BMASK 0x80 /* SPI Busy */ +#define SPIBSY__SHIFT 0x07 /* SPI Busy */ +#define SPIBSY__NOT_SET 0x00 /* A SPI transfer is not in progress. */ +#define SPIBSY__SET 0x80 /* A SPI transfer is in progress. */ + +/*------------------------------------------------------------------------------ */ +/* SPI0CN0 Enums (SPI0 Control @ 0xF8) */ +/*------------------------------------------------------------------------------ */ +#define SPIEN__BMASK 0x01 /* SPI0 Enable */ +#define SPIEN__SHIFT 0x00 /* SPI0 Enable */ +#define SPIEN__DISABLED 0x00 /* Disable the SPI module. */ +#define SPIEN__ENABLED 0x01 /* Enable the SPI module. */ + +#define TXBMT__BMASK 0x02 /* Transmit Buffer Empty */ +#define TXBMT__SHIFT 0x01 /* Transmit Buffer Empty */ +#define TXBMT__NOT_SET 0x00 /* The transmit buffer is not empty. */ +#define TXBMT__SET 0x02 /* The transmit buffer is empty. */ + +#define NSSMD__FMASK 0x0C /* Slave Select Mode */ +#define NSSMD__SHIFT 0x02 /* Slave Select Mode */ +#define NSSMD__3_WIRE 0x00 /* 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin. */ +#define NSSMD__4_WIRE_SLAVE 0x04 /* 4-Wire Slave or Multi-Master Mode. NSS is an input to the device. */ +#define NSSMD__4_WIRE_MASTER_NSS_LOW 0x08 /* 4-Wire Single-Master Mode. NSS is an output and logic low. */ +#define NSSMD__4_WIRE_MASTER_NSS_HIGH 0x0C /* 4-Wire Single-Master Mode. NSS is an output and logic high. */ + +#define RXOVRN__BMASK 0x10 /* Receive Overrun Flag */ +#define RXOVRN__SHIFT 0x04 /* Receive Overrun Flag */ +#define RXOVRN__NOT_SET 0x00 /* A receive overrun did not occur. */ +#define RXOVRN__SET 0x10 /* A receive overrun occurred. */ + +#define MODF__BMASK 0x20 /* Mode Fault Flag */ +#define MODF__SHIFT 0x05 /* Mode Fault Flag */ +#define MODF__NOT_SET 0x00 /* A master collision did not occur. */ +#define MODF__SET 0x20 /* A master collision occurred. */ + +#define WCOL__BMASK 0x40 /* Write Collision Flag */ +#define WCOL__SHIFT 0x06 /* Write Collision Flag */ +#define WCOL__NOT_SET 0x00 /* A write collision did not occur. */ +#define WCOL__SET 0x40 /* A write collision occurred. */ + +#define SPIF__BMASK 0x80 /* SPI0 Interrupt Flag */ +#define SPIF__SHIFT 0x07 /* SPI0 Interrupt Flag */ +#define SPIF__NOT_SET 0x00 /* A data transfer has not completed since the last time SPIF was cleared. */ +#define SPIF__SET 0x80 /* A data transfer completed. */ + +/*------------------------------------------------------------------------------ */ +/* EIE1 Enums (Extended Interrupt Enable 1 @ 0xE6) */ +/*------------------------------------------------------------------------------ */ +#define ESMB0__BMASK 0x01 /* SMBus (SMB0) Interrupt Enable */ +#define ESMB0__SHIFT 0x00 /* SMBus (SMB0) Interrupt Enable */ +#define ESMB0__DISABLED 0x00 /* Disable all SMB0 interrupts. */ +#define ESMB0__ENABLED 0x01 /* Enable interrupt requests generated by SMB0. */ + +#define EMAT__BMASK 0x02 /* Port Match Interrupts Enable */ +#define EMAT__SHIFT 0x01 /* Port Match Interrupts Enable */ +#define EMAT__DISABLED 0x00 /* Disable all Port Match interrupts. */ +#define EMAT__ENABLED 0x02 /* Enable interrupt requests generated by a Port Match. */ + +#define EWADC0__BMASK 0x04 /* ADC0 Window Comparison Interrupt Enable */ +#define EWADC0__SHIFT 0x02 /* ADC0 Window Comparison Interrupt Enable */ +#define EWADC0__DISABLED 0x00 /* Disable ADC0 Window Comparison interrupt. */ +#define EWADC0__ENABLED 0x04 /* Enable interrupt requests generated by ADC0 Window Compare flag (ADWINT). */ + +#define EADC0__BMASK 0x08 /* ADC0 Conversion Complete Interrupt Enable */ +#define EADC0__SHIFT 0x03 /* ADC0 Conversion Complete Interrupt Enable */ +#define EADC0__DISABLED 0x00 /* Disable ADC0 Conversion Complete interrupt. */ +#define EADC0__ENABLED 0x08 /* Enable interrupt requests generated by the ADINT flag. */ + +#define EPCA0__BMASK 0x10 /* Programmable Counter Array (PCA0) Interrupt Enable */ +#define EPCA0__SHIFT 0x04 /* Programmable Counter Array (PCA0) Interrupt Enable */ +#define EPCA0__DISABLED 0x00 /* Disable all PCA0 interrupts. */ +#define EPCA0__ENABLED 0x10 /* Enable interrupt requests generated by PCA0. */ + +#define ECP0__BMASK 0x20 /* Comparator0 (CP0) Interrupt Enable */ +#define ECP0__SHIFT 0x05 /* Comparator0 (CP0) Interrupt Enable */ +#define ECP0__DISABLED 0x00 /* Disable CP0 interrupts. */ +#define ECP0__ENABLED 0x20 /* Enable interrupt requests generated by the comparator 0 CPRIF or CPFIF flags. */ + +#define ECP1__BMASK 0x40 /* Comparator1 (CP1) Interrupt Enable */ +#define ECP1__SHIFT 0x06 /* Comparator1 (CP1) Interrupt Enable */ +#define ECP1__DISABLED 0x00 /* Disable CP1 interrupts. */ +#define ECP1__ENABLED 0x40 /* Enable interrupt requests generated by the comparator 1 CPRIF or CPFIF flags. */ + +#define ET3__BMASK 0x80 /* Timer 3 Interrupt Enable */ +#define ET3__SHIFT 0x07 /* Timer 3 Interrupt Enable */ +#define ET3__DISABLED 0x00 /* Disable Timer 3 interrupts. */ +#define ET3__ENABLED 0x80 /* Enable interrupt requests generated by the TF3L or TF3H flags. */ + +/*------------------------------------------------------------------------------ */ +/* EIP1 Enums (Extended Interrupt Priority 1 @ 0xF3) */ +/*------------------------------------------------------------------------------ */ +#define PSMB0__BMASK 0x01 /* SMBus (SMB0) Interrupt Priority Control */ +#define PSMB0__SHIFT 0x00 /* SMBus (SMB0) Interrupt Priority Control */ +#define PSMB0__LOW 0x00 /* SMB0 interrupt set to low priority level. */ +#define PSMB0__HIGH 0x01 /* SMB0 interrupt set to high priority level. */ + +#define PMAT__BMASK 0x02 /* Port Match Interrupt Priority Control */ +#define PMAT__SHIFT 0x01 /* Port Match Interrupt Priority Control */ +#define PMAT__LOW 0x00 /* Port Match interrupt set to low priority level. */ +#define PMAT__HIGH 0x02 /* Port Match interrupt set to high priority level. */ + +#define PWADC0__BMASK 0x04 /* ADC0 Window Comparator Interrupt Priority Control */ +#define PWADC0__SHIFT 0x02 /* ADC0 Window Comparator Interrupt Priority Control */ +#define PWADC0__LOW 0x00 /* ADC0 Window interrupt set to low priority level. */ +#define PWADC0__HIGH 0x04 /* ADC0 Window interrupt set to high priority level. */ + +#define PADC0__BMASK 0x08 /* ADC0 Conversion Complete Interrupt Priority Control */ +#define PADC0__SHIFT 0x03 /* ADC0 Conversion Complete Interrupt Priority Control */ +#define PADC0__LOW 0x00 /* ADC0 Conversion Complete interrupt set to low priority level. */ +#define PADC0__HIGH 0x08 /* ADC0 Conversion Complete interrupt set to high priority level. */ + +#define PPCA0__BMASK 0x10 /* Programmable Counter Array (PCA0) Interrupt Priority Control */ +#define PPCA0__SHIFT 0x04 /* Programmable Counter Array (PCA0) Interrupt Priority Control */ +#define PPCA0__LOW 0x00 /* PCA0 interrupt set to low priority level. */ +#define PPCA0__HIGH 0x10 /* PCA0 interrupt set to high priority level. */ + +#define PCP0__BMASK 0x20 /* Comparator0 (CP0) Interrupt Priority Control */ +#define PCP0__SHIFT 0x05 /* Comparator0 (CP0) Interrupt Priority Control */ +#define PCP0__LOW 0x00 /* CP0 interrupt set to low priority level. */ +#define PCP0__HIGH 0x20 /* CP0 interrupt set to high priority level. */ + +#define PCP1__BMASK 0x40 /* Comparator1 (CP1) Interrupt Priority Control */ +#define PCP1__SHIFT 0x06 /* Comparator1 (CP1) Interrupt Priority Control */ +#define PCP1__LOW 0x00 /* CP1 interrupt set to low priority level. */ +#define PCP1__HIGH 0x40 /* CP1 interrupt set to high priority level. */ + +#define PT3__BMASK 0x80 /* Timer 3 Interrupt Priority Control */ +#define PT3__SHIFT 0x07 /* Timer 3 Interrupt Priority Control */ +#define PT3__LOW 0x00 /* Timer 3 interrupts set to low priority level. */ +#define PT3__HIGH 0x80 /* Timer 3 interrupts set to high priority level. */ + +/*------------------------------------------------------------------------------ */ +/* IE Enums (Interrupt Enable @ 0xA8) */ +/*------------------------------------------------------------------------------ */ +#define EX0__BMASK 0x01 /* External Interrupt 0 Enable */ +#define EX0__SHIFT 0x00 /* External Interrupt 0 Enable */ +#define EX0__DISABLED 0x00 /* Disable external interrupt 0. */ +#define EX0__ENABLED 0x01 /* Enable interrupt requests generated by the INT0 input. */ + +#define ET0__BMASK 0x02 /* Timer 0 Interrupt Enable */ +#define ET0__SHIFT 0x01 /* Timer 0 Interrupt Enable */ +#define ET0__DISABLED 0x00 /* Disable all Timer 0 interrupt. */ +#define ET0__ENABLED 0x02 /* Enable interrupt requests generated by the TF0 flag. */ + +#define EX1__BMASK 0x04 /* External Interrupt 1 Enable */ +#define EX1__SHIFT 0x02 /* External Interrupt 1 Enable */ +#define EX1__DISABLED 0x00 /* Disable external interrupt 1. */ +#define EX1__ENABLED 0x04 /* Enable interrupt requests generated by the INT1 input. */ + +#define ET1__BMASK 0x08 /* Timer 1 Interrupt Enable */ +#define ET1__SHIFT 0x03 /* Timer 1 Interrupt Enable */ +#define ET1__DISABLED 0x00 /* Disable all Timer 1 interrupt. */ +#define ET1__ENABLED 0x08 /* Enable interrupt requests generated by the TF1 flag. */ + +#define ES0__BMASK 0x10 /* UART0 Interrupt Enable */ +#define ES0__SHIFT 0x04 /* UART0 Interrupt Enable */ +#define ES0__DISABLED 0x00 /* Disable UART0 interrupt. */ +#define ES0__ENABLED 0x10 /* Enable UART0 interrupt. */ + +#define ET2__BMASK 0x20 /* Timer 2 Interrupt Enable */ +#define ET2__SHIFT 0x05 /* Timer 2 Interrupt Enable */ +#define ET2__DISABLED 0x00 /* Disable Timer 2 interrupt. */ +#define ET2__ENABLED 0x20 /* Enable interrupt requests generated by the TF2L or TF2H flags. */ + +#define ESPI0__BMASK 0x40 /* SPI0 Interrupt Enable */ +#define ESPI0__SHIFT 0x06 /* SPI0 Interrupt Enable */ +#define ESPI0__DISABLED 0x00 /* Disable all SPI0 interrupts. */ +#define ESPI0__ENABLED 0x40 /* Enable interrupt requests generated by SPI0. */ + +#define EA__BMASK 0x80 /* All Interrupts Enable */ +#define EA__SHIFT 0x07 /* All Interrupts Enable */ +#define EA__DISABLED 0x00 /* Disable all interrupt sources. */ +#define EA__ENABLED 0x80 /* Enable each interrupt according to its individual mask setting. */ + +/*------------------------------------------------------------------------------ */ +/* SMB0ADM Enums (SMBus 0 Slave Address Mask @ 0xD6) */ +/*------------------------------------------------------------------------------ */ +#define EHACK__BMASK 0x01 /* Hardware Acknowledge Enable */ +#define EHACK__SHIFT 0x00 /* Hardware Acknowledge Enable */ +#define EHACK__ADR_ACK_MANUAL 0x00 /* Firmware must manually acknowledge all incoming address and data bytes. */ +#define EHACK__ADR_ACK_AUTOMATIC 0x01 /* Automatic slave address recognition and hardware acknowledge is enabled. */ + +#define SLVM__FMASK 0xFE /* SMBus Slave Address Mask */ +#define SLVM__SHIFT 0x01 /* SMBus Slave Address Mask */ + +/*------------------------------------------------------------------------------ */ +/* SMB0ADR Enums (SMBus 0 Slave Address @ 0xD7) */ +/*------------------------------------------------------------------------------ */ +#define GC__BMASK 0x01 /* General Call Address Enable */ +#define GC__SHIFT 0x00 /* General Call Address Enable */ +#define GC__IGNORED 0x00 /* General Call Address is ignored. */ +#define GC__RECOGNIZED 0x01 /* General Call Address is recognized. */ + +#define SLV__FMASK 0xFE /* SMBus Hardware Slave Address */ +#define SLV__SHIFT 0x01 /* SMBus Hardware Slave Address */ + +/*------------------------------------------------------------------------------ */ +/* SMB0CF Enums (SMBus 0 Configuration @ 0xC1) */ +/*------------------------------------------------------------------------------ */ +#define SMBCS__FMASK 0x03 /* SMBus Clock Source Selection */ +#define SMBCS__SHIFT 0x00 /* SMBus Clock Source Selection */ +#define SMBCS__TIMER0 0x00 /* Timer 0 Overflow. */ +#define SMBCS__TIMER1 0x01 /* Timer 1 Overflow. */ +#define SMBCS__TIMER2_HIGH 0x02 /* Timer 2 High Byte Overflow. */ +#define SMBCS__TIMER2_LOW 0x03 /* Timer 2 Low Byte Overflow. */ + +#define SMBFTE__BMASK 0x04 /* SMBus Free Timeout Detection Enable */ +#define SMBFTE__SHIFT 0x02 /* SMBus Free Timeout Detection Enable */ +#define SMBFTE__FREE_TO_DISABLED 0x00 /* Disable bus free timeouts. */ +#define SMBFTE__FREE_TO_ENABLED 0x04 /* Enable bus free timeouts. The bus the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods. */ + +#define SMBTOE__BMASK 0x08 /* SMBus SCL Timeout Detection Enable */ +#define SMBTOE__SHIFT 0x03 /* SMBus SCL Timeout Detection Enable */ +#define SMBTOE__SCL_TO_DISABLED 0x00 /* Disable SCL low timeouts. */ +#define SMBTOE__SCL_TO_ENABLED 0x08 /* Enable SCL low timeouts. */ + +#define EXTHOLD__BMASK 0x10 /* SMBus Setup and Hold Time Extension Enable */ +#define EXTHOLD__SHIFT 0x04 /* SMBus Setup and Hold Time Extension Enable */ +#define EXTHOLD__DISABLED 0x00 /* Disable SDA extended setup and hold times. */ +#define EXTHOLD__ENABLED 0x10 /* Enable SDA extended setup and hold times. */ + +#define BUSY__BMASK 0x20 /* SMBus Busy Indicator */ +#define BUSY__SHIFT 0x05 /* SMBus Busy Indicator */ +#define BUSY__NOT_SET 0x00 /* The bus is not busy. */ +#define BUSY__SET 0x20 /* The bus is busy and a transfer is currently in progress. */ + +#define INH__BMASK 0x40 /* SMBus Slave Inhibit */ +#define INH__SHIFT 0x06 /* SMBus Slave Inhibit */ +#define INH__SLAVE_ENABLED 0x00 /* Slave states are enabled. */ +#define INH__SLAVE_DISABLED 0x40 /* Slave states are inhibited. */ + +#define ENSMB__BMASK 0x80 /* SMBus Enable */ +#define ENSMB__SHIFT 0x07 /* SMBus Enable */ +#define ENSMB__DISABLED 0x00 /* Disable the SMBus module. */ +#define ENSMB__ENABLED 0x80 /* Enable the SMBus module. */ + +/*------------------------------------------------------------------------------ */ +/* SMB0CN0 Enums (SMBus 0 Control @ 0xC0) */ +/*------------------------------------------------------------------------------ */ +#define SI__BMASK 0x01 /* SMBus Interrupt Flag */ +#define SI__SHIFT 0x00 /* SMBus Interrupt Flag */ +#define SI__NOT_SET 0x00 /* */ +#define SI__SET 0x01 /* */ + +#define ACK__BMASK 0x02 /* SMBus Acknowledge */ +#define ACK__SHIFT 0x01 /* SMBus Acknowledge */ +#define ACK__NOT_SET 0x00 /* Generate a NACK, or the response was a NACK. */ +#define ACK__SET 0x02 /* Generate an ACK, or the response was an ACK. */ + +#define ARBLOST__BMASK 0x04 /* SMBus Arbitration Lost Indicator */ +#define ARBLOST__SHIFT 0x02 /* SMBus Arbitration Lost Indicator */ +#define ARBLOST__NOT_SET 0x00 /* No arbitration error. */ +#define ARBLOST__ERROR 0x04 /* Arbitration error occurred. */ + +#define ACKRQ__BMASK 0x08 /* SMBus Acknowledge Request */ +#define ACKRQ__SHIFT 0x03 /* SMBus Acknowledge Request */ +#define ACKRQ__NOT_SET 0x00 /* No ACK requested. */ +#define ACKRQ__REQUESTED 0x08 /* ACK requested. */ + +#define STO__BMASK 0x10 /* SMBus Stop Flag */ +#define STO__SHIFT 0x04 /* SMBus Stop Flag */ +#define STO__NOT_SET 0x00 /* A STOP is not pending. */ +#define STO__SET 0x10 /* Generate a STOP or a STOP is currently pending. */ + +#define STA__BMASK 0x20 /* SMBus Start Flag */ +#define STA__SHIFT 0x05 /* SMBus Start Flag */ +#define STA__NOT_SET 0x00 /* A START was not detected. */ +#define STA__SET 0x20 /* Generate a START, repeated START, or a START is currently pending. */ + +#define TXMODE__BMASK 0x40 /* SMBus Transmit Mode Indicator */ +#define TXMODE__SHIFT 0x06 /* SMBus Transmit Mode Indicator */ +#define TXMODE__RECEIVER 0x00 /* SMBus in Receiver Mode. */ +#define TXMODE__TRANSMITTER 0x40 /* SMBus in Transmitter Mode. */ + +#define MASTER__BMASK 0x80 /* SMBus Master/Slave Indicator */ +#define MASTER__SHIFT 0x07 /* SMBus Master/Slave Indicator */ +#define MASTER__SLAVE 0x00 /* SMBus operating in slave mode. */ +#define MASTER__MASTER 0x80 /* SMBus operating in master mode. */ + +/*------------------------------------------------------------------------------ */ +/* SMB0TC Enums (SMBus 0 Timing and Pin Control @ 0xAC) */ +/*------------------------------------------------------------------------------ */ +#define SDD__FMASK 0x03 /* SMBus Start Detection Window */ +#define SDD__SHIFT 0x00 /* SMBus Start Detection Window */ +#define SDD__NONE 0x00 /* No additional hold time window (0-1 SYSCLK). */ +#define SDD__ADD_2_SYSCLKS 0x01 /* Increase hold time window to 2-3 SYSCLKs. */ +#define SDD__ADD_4_SYSCLKS 0x02 /* Increase hold time window to 4-5 SYSCLKs. */ +#define SDD__ADD_8_SYSCLKS 0x03 /* Increase hold time window to 8-9 SYSCLKs. */ + +#define SWAP__BMASK 0x80 /* SMBus Swap Pins */ +#define SWAP__SHIFT 0x07 /* SMBus Swap Pins */ +#define SWAP__SDA_LOW_PIN 0x00 /* SDA is mapped to the lower-numbered port pin, and SCL is mapped to the higher-numbered port pin. */ +#define SWAP__SDA_HIGH_PIN 0x80 /* SCL is mapped to the lower-numbered port pin, and SDA is mapped to the higher-numbered port pin. */ + +/*------------------------------------------------------------------------------ */ +/* SCON0 Enums (UART0 Serial Port Control @ 0x98) */ +/*------------------------------------------------------------------------------ */ +#define RI__BMASK 0x01 /* Receive Interrupt Flag */ +#define RI__SHIFT 0x00 /* Receive Interrupt Flag */ +#define RI__NOT_SET 0x00 /* A byte of data has not been received by UART0. */ +#define RI__SET 0x01 /* UART0 received a byte of data. */ + +#define TI__BMASK 0x02 /* Transmit Interrupt Flag */ +#define TI__SHIFT 0x01 /* Transmit Interrupt Flag */ +#define TI__NOT_SET 0x00 /* A byte of data has not been transmitted by UART0. */ +#define TI__SET 0x02 /* UART0 transmitted a byte of data. */ + +#define RB8__BMASK 0x04 /* Ninth Receive Bit */ +#define RB8__SHIFT 0x02 /* Ninth Receive Bit */ +#define RB8__CLEARED_TO_0 0x00 /* In Mode 0, the STOP bit was 0. In Mode 1, the 9th bit was 0. */ +#define RB8__SET_TO_1 0x04 /* In Mode 0, the STOP bit was 1. In Mode 1, the 9th bit was 1. */ + +#define TB8__BMASK 0x08 /* Ninth Transmission Bit */ +#define TB8__SHIFT 0x03 /* Ninth Transmission Bit */ +#define TB8__CLEARED_TO_0 0x00 /* In Mode 1, set the 9th transmission bit to 0. */ +#define TB8__SET_TO_1 0x08 /* In Mode 1, set the 9th transmission bit to 1. */ + +#define REN__BMASK 0x10 /* Receive Enable */ +#define REN__SHIFT 0x04 /* Receive Enable */ +#define REN__RECEIVE_DISABLED 0x00 /* UART0 reception disabled. */ +#define REN__RECEIVE_ENABLED 0x10 /* UART0 reception enabled. */ + +#define MCE__BMASK 0x20 /* Multiprocessor Communication Enable */ +#define MCE__SHIFT 0x05 /* Multiprocessor Communication Enable */ +#define MCE__MULTI_DISABLED 0x00 /* Ignore level of 9th bit / Stop bit. */ +#define MCE__MULTI_ENABLED 0x20 /* RI is set and an interrupt is generated only when the stop bit is logic 1 (Mode 0) or when the 9th bit is logic 1 (Mode 1). */ + +#define SMODE__BMASK 0x80 /* Serial Port 0 Operation Mode */ +#define SMODE__SHIFT 0x07 /* Serial Port 0 Operation Mode */ +#define SMODE__8_BIT 0x00 /* 8-bit UART with Variable Baud Rate (Mode 0). */ +#define SMODE__9_BIT 0x80 /* 9-bit UART with Variable Baud Rate (Mode 1). */ + +/*------------------------------------------------------------------------------ */ +/* CMP0CN0 Enums (Comparator 0 Control 0 @ 0x9B) */ +/*------------------------------------------------------------------------------ */ +#define CPHYN__FMASK 0x03 /* Comparator Negative Hysteresis Control */ +#define CPHYN__SHIFT 0x00 /* Comparator Negative Hysteresis Control */ +#define CPHYN__DISABLED 0x00 /* Negative Hysteresis disabled. */ +#define CPHYN__ENABLED_MODE1 0x01 /* Negative Hysteresis = Hysteresis 1. */ +#define CPHYN__ENABLED_MODE2 0x02 /* Negative Hysteresis = Hysteresis 2. */ +#define CPHYN__ENABLED_MODE3 0x03 /* Negative Hysteresis = Hysteresis 3 (Maximum). */ + +#define CPHYP__FMASK 0x0C /* Comparator Positive Hysteresis Control */ +#define CPHYP__SHIFT 0x02 /* Comparator Positive Hysteresis Control */ +#define CPHYP__DISABLED 0x00 /* Positive Hysteresis disabled. */ +#define CPHYP__ENABLED_MODE1 0x04 /* Positive Hysteresis = Hysteresis 1. */ +#define CPHYP__ENABLED_MODE2 0x08 /* Positive Hysteresis = Hysteresis 2. */ +#define CPHYP__ENABLED_MODE3 0x0C /* Positive Hysteresis = Hysteresis 3 (Maximum). */ + +#define CPFIF__BMASK 0x10 /* Comparator Falling-Edge Flag */ +#define CPFIF__SHIFT 0x04 /* Comparator Falling-Edge Flag */ +#define CPFIF__NOT_SET 0x00 /* No comparator falling edge has occurred since this flag was last cleared. */ +#define CPFIF__FALLING_EDGE 0x10 /* Comparator falling edge has occurred. */ + +#define CPRIF__BMASK 0x20 /* Comparator Rising-Edge Flag */ +#define CPRIF__SHIFT 0x05 /* Comparator Rising-Edge Flag */ +#define CPRIF__NOT_SET 0x00 /* No comparator rising edge has occurred since this flag was last cleared. */ +#define CPRIF__RISING_EDGE 0x20 /* Comparator rising edge has occurred. */ + +#define CPOUT__BMASK 0x40 /* Comparator Output State Flag */ +#define CPOUT__SHIFT 0x06 /* Comparator Output State Flag */ +#define CPOUT__POS_LESS_THAN_NEG 0x00 /* Voltage on CP0P < CP0N. */ +#define CPOUT__POS_GREATER_THAN_NEG 0x40 /* Voltage on CP0P > CP0N. */ + +#define CPEN__BMASK 0x80 /* Comparator Enable */ +#define CPEN__SHIFT 0x07 /* Comparator Enable */ +#define CPEN__DISABLED 0x00 /* Comparator disabled. */ +#define CPEN__ENABLED 0x80 /* Comparator enabled. */ + +/*------------------------------------------------------------------------------ */ +/* CMP0MD Enums (Comparator 0 Mode @ 0x9D) */ +/*------------------------------------------------------------------------------ */ +#define CPMD__FMASK 0x03 /* Comparator Mode Select */ +#define CPMD__SHIFT 0x00 /* Comparator Mode Select */ +#define CPMD__MODE0 0x00 /* Mode 0 (Fastest Response Time, Highest Power */ +/* Consumption) */ +#define CPMD__MODE1 0x01 /* Mode 1 */ +#define CPMD__MODE2 0x02 /* Mode 2 */ +#define CPMD__MODE3 0x03 /* Mode 3 (Slowest Response Time, Lowest Power */ +/* Consumption) */ + +#define CPFIE__BMASK 0x10 /* Comparator Falling-Edge Interrupt Enable */ +#define CPFIE__SHIFT 0x04 /* Comparator Falling-Edge Interrupt Enable */ +#define CPFIE__FALL_INT_DISABLED 0x00 /* Comparator falling-edge interrupt disabled. */ +#define CPFIE__FALL_INT_ENABLED 0x10 /* Comparator falling-edge interrupt enabled. */ + +#define CPRIE__BMASK 0x20 /* Comparator Rising-Edge Interrupt Enable */ +#define CPRIE__SHIFT 0x05 /* Comparator Rising-Edge Interrupt Enable */ +#define CPRIE__RISE_INT_DISABLED 0x00 /* Comparator rising-edge interrupt disabled. */ +#define CPRIE__RISE_INT_ENABLED 0x20 /* Comparator rising-edge interrupt enabled. */ + +#define CPLOUT__BMASK 0x80 /* Comparator Latched Output Flag */ +#define CPLOUT__SHIFT 0x07 /* Comparator Latched Output Flag */ +#define CPLOUT__LOW 0x00 /* Comparator output was logic low at last PCA overflow. */ +#define CPLOUT__HIGH 0x80 /* Comparator output was logic high at last PCA overflow. */ +#define CPMD__FMASK 0x03 /* Comparator Mode Select */ +#define CPMD__SHIFT 0x00 /* Comparator Mode Select */ +#define CPMD__MODE0 0x00 /* Mode 0 (Fastest Response Time, Highest Power Consumption) */ +#define CPMD__MODE1 0x01 /* Mode 1 */ +#define CPMD__MODE2 0x02 /* Mode 2 */ +#define CPMD__MODE3 0x03 /* Mode 3 (Slowest Response Time, Lowest Power Consumption) */ + +#define CPFIE__BMASK 0x10 /* Comparator Falling-Edge Interrupt Enable */ +#define CPFIE__SHIFT 0x04 /* Comparator Falling-Edge Interrupt Enable */ +#define CPFIE__FALL_INT_DISABLED 0x00 /* Comparator falling-edge interrupt disabled. */ +#define CPFIE__FALL_INT_ENABLED 0x10 /* Comparator falling-edge interrupt enabled. */ + +#define CPRIE__BMASK 0x20 /* Comparator Rising-Edge Interrupt Enable */ +#define CPRIE__SHIFT 0x05 /* Comparator Rising-Edge Interrupt Enable */ +#define CPRIE__RISE_INT_DISABLED 0x00 /* Comparator rising-edge interrupt disabled. */ +#define CPRIE__RISE_INT_ENABLED 0x20 /* Comparator rising-edge interrupt enabled. */ + +#define CPLOUT__BMASK 0x80 /* Comparator Latched Output Flag */ +#define CPLOUT__SHIFT 0x07 /* Comparator Latched Output Flag */ +#define CPLOUT__LOW 0x00 /* Comparator output was logic low at last PCA overflow. */ +#define CPLOUT__HIGH 0x80 /* Comparator output was logic high at last PCA overflow. */ + +/*------------------------------------------------------------------------------ */ +/* CMP0MX Enums (Comparator 0 Multiplexer Selection @ 0x9F) */ +/*------------------------------------------------------------------------------ */ +#define CMXP__FMASK 0x0F /* Comparator Positive Input MUX Selection */ +#define CMXP__SHIFT 0x00 /* Comparator Positive Input MUX Selection */ +#define CMXP__CMP0P0 0x00 /* External pin CMP0P.0. */ +#define CMXP__CMP0P1 0x01 /* External pin CMP0P.1. */ +#define CMXP__CMP0P2 0x02 /* External pin CMP0P.2. */ +#define CMXP__CMP0P3 0x03 /* External pin CMP0P.3. */ +#define CMXP__CMP0P4 0x04 /* External pin CMP0P.4. */ +#define CMXP__CMP0P5 0x05 /* External pin CMP0P.5. */ +#define CMXP__CMP0P6 0x06 /* External pin CMP0P.6. */ +#define CMXP__CMP0P7 0x07 /* External pin CMP0P.7. */ +#define CMXP__LDO_OUT 0x08 /* External pin CMP0P.8. */ +#define CMXP__NONE 0x0F /* No input selected. */ + +#define CMXN__FMASK 0xF0 /* Comparator Negative Input MUX Selection */ +#define CMXN__SHIFT 0x04 /* Comparator Negative Input MUX Selection */ +#define CMXN__CMP0N0 0x00 /* External pin CMP0N.0. */ +#define CMXN__CMP0N1 0x10 /* External pin CMP0N.1. */ +#define CMXN__CMP0N2 0x20 /* External pin CMP0N.2. */ +#define CMXN__CMP0N3 0x30 /* External pin CMP0N.3. */ +#define CMXN__CMP0N4 0x40 /* External pin CMP0N.4. */ +#define CMXN__CMP0N5 0x50 /* External pin CMP0N.5. */ +#define CMXN__CMP0N6 0x60 /* External pin CMP0N.6. */ +#define CMXN__CMP0N7 0x70 /* External pin CMP0N.7. */ +#define CMXN__GND 0x80 /* External pin CMP0N.8. */ +#define CMXN__NONE 0xF0 /* No input selected. */ + +/*------------------------------------------------------------------------------ */ +/* CMP1CN0 Enums (Comparator 1 Control 0 @ 0xBF) */ +/*------------------------------------------------------------------------------ */ +#define CPHYN__FMASK 0x03 /* Comparator Negative Hysteresis Control */ +#define CPHYN__SHIFT 0x00 /* Comparator Negative Hysteresis Control */ +#define CPHYN__DISABLED 0x00 /* Negative Hysteresis disabled. */ +#define CPHYN__ENABLED_MODE1 0x01 /* Negative Hysteresis = Hysteresis 1. */ +#define CPHYN__ENABLED_MODE2 0x02 /* Negative Hysteresis = Hysteresis 2. */ +#define CPHYN__ENABLED_MODE3 0x03 /* Negative Hysteresis = Hysteresis 3 (Maximum). */ + +#define CPHYP__FMASK 0x0C /* Comparator Positive Hysteresis Control */ +#define CPHYP__SHIFT 0x02 /* Comparator Positive Hysteresis Control */ +#define CPHYP__DISABLED 0x00 /* Positive Hysteresis disabled. */ +#define CPHYP__ENABLED_MODE1 0x04 /* Positive Hysteresis = Hysteresis 1. */ +#define CPHYP__ENABLED_MODE2 0x08 /* Positive Hysteresis = Hysteresis 2. */ +#define CPHYP__ENABLED_MODE3 0x0C /* Positive Hysteresis = Hysteresis 3 (Maximum). */ + +#define CPFIF__BMASK 0x10 /* Comparator Falling-Edge Flag */ +#define CPFIF__SHIFT 0x04 /* Comparator Falling-Edge Flag */ +#define CPFIF__NOT_SET 0x00 /* No comparator falling edge has occurred since this flag was last cleared. */ +#define CPFIF__FALLING_EDGE 0x10 /* Comparator falling edge has occurred. */ + +#define CPRIF__BMASK 0x20 /* Comparator Rising-Edge Flag */ +#define CPRIF__SHIFT 0x05 /* Comparator Rising-Edge Flag */ +#define CPRIF__NOT_SET 0x00 /* No comparator rising edge has occurred since this flag was last cleared. */ +#define CPRIF__RISING_EDGE 0x20 /* Comparator rising edge has occurred. */ + +#define CPOUT__BMASK 0x40 /* Comparator Output State Flag */ +#define CPOUT__SHIFT 0x06 /* Comparator Output State Flag */ +#define CPOUT__POS_LESS_THAN_NEG 0x00 /* Voltage on CP1P < CP1N. */ +#define CPOUT__POS_GREATER_THAN_NEG 0x40 /* Voltage on CP1P > CP1N. */ + +#define CPEN__BMASK 0x80 /* Comparator Enable */ +#define CPEN__SHIFT 0x07 /* Comparator Enable */ +#define CPEN__DISABLED 0x00 /* Comparator disabled. */ +#define CPEN__ENABLED 0x80 /* Comparator enabled. */ + +/*------------------------------------------------------------------------------ */ +/* CMP1MD Enums (Comparator 1 Mode @ 0xAB) */ +/*------------------------------------------------------------------------------ */ +#define CPMD__FMASK 0x03 /* Comparator Mode Select */ +#define CPMD__SHIFT 0x00 /* Comparator Mode Select */ +#define CPMD__MODE0 0x00 /* Mode 0 (Fastest Response Time, Highest Power Consumption) */ +#define CPMD__MODE1 0x01 /* Mode 1 */ +#define CPMD__MODE2 0x02 /* Mode 2 */ +#define CPMD__MODE3 0x03 /* Mode 3 (Slowest Response Time, Lowest Power Consumption) */ + +#define CPFIE__BMASK 0x10 /* Comparator Falling-Edge Interrupt Enable */ +#define CPFIE__SHIFT 0x04 /* Comparator Falling-Edge Interrupt Enable */ +#define CPFIE__FALL_INT_DISABLED 0x00 /* Comparator falling-edge interrupt disabled. */ +#define CPFIE__FALL_INT_ENABLED 0x10 /* Comparator falling-edge interrupt enabled. */ + +#define CPRIE__BMASK 0x20 /* Comparator Rising-Edge Interrupt Enable */ +#define CPRIE__SHIFT 0x05 /* Comparator Rising-Edge Interrupt Enable */ +#define CPRIE__RISE_INT_DISABLED 0x00 /* Comparator rising-edge interrupt disabled. */ +#define CPRIE__RISE_INT_ENABLED 0x20 /* Comparator rising-edge interrupt enabled. */ + +#define CPLOUT__BMASK 0x80 /* Comparator Latched Output Flag */ +#define CPLOUT__SHIFT 0x07 /* Comparator Latched Output Flag */ +#define CPLOUT__LOW 0x00 /* Comparator output was logic low at last PCA overflow. */ +#define CPLOUT__HIGH 0x80 /* Comparator output was logic high at last PCA overflow. */ + +/*------------------------------------------------------------------------------ */ +/* CMP1MX Enums (Comparator 1 Multiplexer Selection @ 0xAA) */ +/*------------------------------------------------------------------------------ */ +#define CMXP__FMASK 0x0F /* Comparator Positive Input MUX Selection */ +#define CMXP__SHIFT 0x00 /* Comparator Positive Input MUX Selection */ +#define CMXP__CMP1P0 0x00 /* External pin CMP1P.0. */ +#define CMXP__CMP1P1 0x01 /* External pin CMP1P.1. */ +#define CMXP__CMP1P2 0x02 /* External pin CMP1P.2. */ +#define CMXP__CMP1P3 0x03 /* External pin CMP1P.3. */ +#define CMXP__CMP1P4 0x04 /* External pin CMP1P.4. */ +#define CMXP__CMP1P5 0x05 /* External pin CMP1P.5. */ +#define CMXP__CMP1P6 0x06 /* External pin CMP1P.6. */ +#define CMXP__CMP1P7 0x07 /* External pin CMP1P.7. */ +#define CMXP__LDO_OUT 0x08 /* External pin CMP1P.8. */ +#define CMXP__NONE 0x0F /* No input selected. */ + +#define CMXN__FMASK 0xF0 /* Comparator Negative Input MUX Selection */ +#define CMXN__SHIFT 0x04 /* Comparator Negative Input MUX Selection */ +#define CMXN__CMP1N0 0x00 /* External pin CMP1N.0. */ +#define CMXN__CMP1N1 0x10 /* External pin CMP1N.1. */ +#define CMXN__CMP1N2 0x20 /* External pin CMP1N.2. */ +#define CMXN__CMP1N3 0x30 /* External pin CMP1N.3. */ +#define CMXN__CMP1N4 0x40 /* External pin CMP1N.4. */ +#define CMXN__CMP1N5 0x50 /* External pin CMP1N.5. */ +#define CMXN__CMP1N6 0x60 /* External pin CMP1N.6. */ +#define CMXN__CMP1N7 0x70 /* External pin CMP1N.7. */ +#define CMXN__GND 0x80 /* External pin CMP1N.8. */ +#define CMXN__NONE 0xF0 /* No input selected. */ + +/*------------------------------------------------------------------------------ */ +/* CRC0AUTO Enums (CRC0 Automatic Control @ 0xD2) */ +/*------------------------------------------------------------------------------ */ +#define CRCST__FMASK 0x3F /* Automatic CRC Calculation Starting Block */ +#define CRCST__SHIFT 0x00 /* Automatic CRC Calculation Starting Block */ + +#define AUTOEN__BMASK 0x80 /* Automatic CRC Calculation Enable */ +#define AUTOEN__SHIFT 0x07 /* Automatic CRC Calculation Enable */ +#define AUTOEN__DISABLED 0x00 /* Disable automatic CRC operations on flash. */ +#define AUTOEN__ENABLED 0x80 /* Enable automatic CRC operations on flash. */ + +/*------------------------------------------------------------------------------ */ +/* CRC0CN0 Enums (CRC0 Control 0 @ 0xCE) */ +/*------------------------------------------------------------------------------ */ +#define CRCPNT__BMASK 0x01 /* CRC Result Pointer */ +#define CRCPNT__SHIFT 0x00 /* CRC Result Pointer */ +#define CRCPNT__ACCESS_LOWER 0x00 /* CRC0DAT accesses bits 7-0 of the 16-bit CRC result. */ +#define CRCPNT__ACCESS_UPPER 0x01 /* CRC0DAT accesses bits 15-8 of the 16-bit CRC result. */ + +#define CRCVAL__BMASK 0x04 /* CRC Initialization Value */ +#define CRCVAL__SHIFT 0x02 /* CRC Initialization Value */ +#define CRCVAL__SET_ZEROES 0x00 /* CRC result is set to 0x0000 on write of 1 to CRCINIT. */ +#define CRCVAL__SET_ONES 0x04 /* CRC result is set to 0xFFFF on write of 1 to CRCINIT. */ + +#define CRCINIT__BMASK 0x08 /* CRC Initialization Enable */ +#define CRCINIT__SHIFT 0x03 /* CRC Initialization Enable */ +#define CRCINIT__DO_NOT_INIT 0x00 /* Do not initialize the CRC result. */ +#define CRCINIT__INIT 0x08 /* Initialize the CRC result to ones or zeroes vased on the value of CRCVAL. */ + +/*------------------------------------------------------------------------------ */ +/* CRC0CNT Enums (CRC0 Automatic Flash Sector Count @ 0xD3) */ +/*------------------------------------------------------------------------------ */ +#define CRCCNT__FMASK 0x1F /* Automatic CRC Calculation Block Count */ +#define CRCCNT__SHIFT 0x00 /* Automatic CRC Calculation Block Count */ + +#define CRCDN__BMASK 0x80 /* Automatic CRC Calculation Complete */ +#define CRCDN__SHIFT 0x07 /* Automatic CRC Calculation Complete */ +#define CRCDN__NOT_SET 0x00 /* A CRC calculation is in progress. */ +#define CRCDN__SET 0x80 /* A CRC calculation is not in progress. */ + + +/*------------------------------------------------------------------------------ */ +/* DERIVID Enums (Derivative Identification @ 0xAD) */ +/*------------------------------------------------------------------------------ */ +#define DERIVID__FMASK 0xFF /* Derivative ID */ +#define DERIVID__SHIFT 0x00 /* Derivative ID */ +#define DERIVID__EFM8BB10F8G_QSOP24 0x01 /* EFM8BB10F8G-{R}-QSOP24 */ +#define DERIVID__EFM8BB10F8G_QFN20 0x02 /* EFM8BB10F8G-{R}-QFN20 */ +#define DERIVID__EFM8BB10F8G_SOIC16 0x03 /* EFM8BB10F8G-{R}-SOIC16 */ +#define DERIVID__EFM8BB10F4G_QFN20 0x05 /* EFM8BB10F4G-{R}-QFN20 */ +#define DERIVID__EFM8BB10F2G_QFN20 0x08 /* EFM8BB10F2G-{R}-QFN20 */ + +/*------------------------------------------------------------------------------ */ +/* REVID Enums (Revision Identifcation @ 0xB6) */ +/*------------------------------------------------------------------------------ */ +#define REVID__FMASK 0xFF /* Revision ID */ +#define REVID__SHIFT 0x00 /* Revision ID */ +#define REVID__REV_A 0x02 /* Revision A */ + +/*------------------------------------------------------------------------------ */ +/* IT01CF Enums (INT0/INT1 Configuration @ 0xE4) */ +/*------------------------------------------------------------------------------ */ +#define IN0SL__FMASK 0x07 /* INT0 Port Pin Selection */ +#define IN0SL__SHIFT 0x00 /* INT0 Port Pin Selection */ +#define IN0SL__P0_0 0x00 /* Select P0.0. */ +#define IN0SL__P0_1 0x01 /* Select P0.1. */ +#define IN0SL__P0_2 0x02 /* Select P0.2. */ +#define IN0SL__P0_3 0x03 /* Select P0.3. */ +#define IN0SL__P0_4 0x04 /* Select P0.4. */ +#define IN0SL__P0_5 0x05 /* Select P0.5. */ +#define IN0SL__P0_6 0x06 /* Select P0.6. */ +#define IN0SL__P0_7 0x07 /* Select P0.7. */ + +#define IN0PL__BMASK 0x08 /* INT0 Polarity */ +#define IN0PL__SHIFT 0x03 /* INT0 Polarity */ +#define IN0PL__ACTIVE_LOW 0x00 /* INT0 input is active low. */ +#define IN0PL__ACTIVE_HIGH 0x08 /* INT0 input is active high. */ + +#define IN1SL__FMASK 0x70 /* INT1 Port Pin Selection */ +#define IN1SL__SHIFT 0x04 /* INT1 Port Pin Selection */ +#define IN1SL__P0_0 0x00 /* Select P0.0. */ +#define IN1SL__P0_1 0x10 /* Select P0.1. */ +#define IN1SL__P0_2 0x20 /* Select P0.2. */ +#define IN1SL__P0_3 0x30 /* Select P0.3. */ +#define IN1SL__P0_4 0x40 /* Select P0.4. */ +#define IN1SL__P0_5 0x50 /* Select P0.5. */ +#define IN1SL__P0_6 0x60 /* Select P0.6. */ +#define IN1SL__P0_7 0x70 /* Select P0.7. */ + +#define IN1PL__BMASK 0x80 /* INT1 Polarity */ +#define IN1PL__SHIFT 0x07 /* INT1 Polarity */ +#define IN1PL__ACTIVE_LOW 0x00 /* INT1 input is active low. */ +#define IN1PL__ACTIVE_HIGH 0x80 /* INT1 input is active high. */ + +/*------------------------------------------------------------------------------ */ +/* FLKEY Enums (Flash Lock and Key @ 0xB7) */ +/*------------------------------------------------------------------------------ */ +#define FLKEY__FMASK 0xFF /* Flash Lock and Key */ +#define FLKEY__SHIFT 0x00 /* Flash Lock and Key */ +#define FLKEY__LOCKED 0x00 /* Flash is write/erase locked. */ +#define FLKEY__FIRST 0x01 /* The first key code has been written (0xA5). */ +#define FLKEY__UNLOCKED 0x02 /* Flash is unlocked (writes/erases allowed). */ +#define FLKEY__DISABLED 0x03 /* Flash writes/erases are disabled until the next reset. */ +#define FLKEY__KEY1 0xA5 /* Flash writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY register. */ +#define FLKEY__KEY2 0xF1 /* Flash writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY register. */ + +/*------------------------------------------------------------------------------ */ +/* PSCTL Enums (Program Store Control @ 0x8F) */ +/*------------------------------------------------------------------------------ */ +#define PSWE__BMASK 0x01 /* Program Store Write Enable */ +#define PSWE__SHIFT 0x00 /* Program Store Write Enable */ +#define PSWE__WRITE_DISABLED 0x00 /* Writes to flash program memory disabled. */ +#define PSWE__WRITE_ENABLED 0x01 /* Writes to flash program memory enabled; the MOVX write instruction targets flash memory. */ + +#define PSEE__BMASK 0x02 /* Program Store Erase Enable */ +#define PSEE__SHIFT 0x01 /* Program Store Erase Enable */ +#define PSEE__ERASE_DISABLED 0x00 /* Flash program memory erasure disabled. */ +#define PSEE__ERASE_ENABLED 0x02 /* Flash program memory erasure enabled. */ + +/*------------------------------------------------------------------------------ */ +/* IP Enums (Interrupt Priority @ 0xB8) */ +/*------------------------------------------------------------------------------ */ +#define PX0__BMASK 0x01 /* External Interrupt 0 Priority Control */ +#define PX0__SHIFT 0x00 /* External Interrupt 0 Priority Control */ +#define PX0__LOW 0x00 /* External Interrupt 0 set to low priority level. */ +#define PX0__HIGH 0x01 /* External Interrupt 0 set to high priority level. */ + +#define PT0__BMASK 0x02 /* Timer 0 Interrupt Priority Control */ +#define PT0__SHIFT 0x01 /* Timer 0 Interrupt Priority Control */ +#define PT0__LOW 0x00 /* Timer 0 interrupt set to low priority level. */ +#define PT0__HIGH 0x02 /* Timer 0 interrupt set to high priority level. */ + +#define PX1__BMASK 0x04 /* External Interrupt 1 Priority Control */ +#define PX1__SHIFT 0x02 /* External Interrupt 1 Priority Control */ +#define PX1__LOW 0x00 /* External Interrupt 1 set to low priority level. */ +#define PX1__HIGH 0x04 /* External Interrupt 1 set to high priority level. */ + +#define PT1__BMASK 0x08 /* Timer 1 Interrupt Priority Control */ +#define PT1__SHIFT 0x03 /* Timer 1 Interrupt Priority Control */ +#define PT1__LOW 0x00 /* Timer 1 interrupt set to low priority level. */ +#define PT1__HIGH 0x08 /* Timer 1 interrupt set to high priority level. */ + +#define PS0__BMASK 0x10 /* UART0 Interrupt Priority Control */ +#define PS0__SHIFT 0x04 /* UART0 Interrupt Priority Control */ +#define PS0__LOW 0x00 /* UART0 interrupt set to low priority level. */ +#define PS0__HIGH 0x10 /* UART0 interrupt set to high priority level. */ + +#define PT2__BMASK 0x20 /* Timer 2 Interrupt Priority Control */ +#define PT2__SHIFT 0x05 /* Timer 2 Interrupt Priority Control */ +#define PT2__LOW 0x00 /* Timer 2 interrupt set to low priority level. */ +#define PT2__HIGH 0x20 /* Timer 2 interrupt set to high priority level. */ + +#define PSPI0__BMASK 0x40 /* Serial Peripheral Interface (SPI0) Interrupt Priority Control */ +#define PSPI0__SHIFT 0x06 /* Serial Peripheral Interface (SPI0) Interrupt Priority Control */ +#define PSPI0__LOW 0x00 /* SPI0 interrupt set to low priority level. */ +#define PSPI0__HIGH 0x40 /* SPI0 interrupt set to high priority level. */ + +/*------------------------------------------------------------------------------ */ +/* LFO0CN Enums (Low Frequency Oscillator Control @ 0xB1) */ +/*------------------------------------------------------------------------------ */ +typedef union { + uint8_t reg; + struct { + uint8_t OSCLD : 2; + uint8_t OSCLF : 4; + uint8_t OSCLRDY : 1; + uint8_t OSCLEN : 1; + } bf; +} LFO0CN_t; + +#define OSCLD__DIVIDE_BY_8 0x00 /* Divide by 8 selected. */ +#define OSCLD__DIVIDE_BY_4 0x01 /* Divide by 4 selected. */ +#define OSCLD__DIVIDE_BY_2 0x02 /* Divide by 2 selected. */ +#define OSCLD__DIVIDE_BY_1 0x03 /* Divide by 1 selected. */ + +#define OSCLRDY__NOT_SET 0x00 /* Internal L-F Oscillator frequency not stabilized. */ +#define OSCLRDY__SET 0x01 /* Internal L-F Oscillator frequency stabilized. */ + +#define OSCLEN__DISABLED 0x00 /* Internal L-F Oscillator Disabled. */ +#define OSCLEN__ENABLED 0x01 /* Internal L-F Oscillator Enabled. */ + +/*------------------------------------------------------------------------------ */ +/* PRTDRV Enums (Port Drive Strength @ 0xF6) */ +/*------------------------------------------------------------------------------ */ +#define P0DRV__BMASK 0x01 /* Port 0 Drive Strength */ +#define P0DRV__SHIFT 0x00 /* Port 0 Drive Strength */ +#define P0DRV__LOW_DRIVE 0x00 /* All pins on P0 use low drive strength. */ +#define P0DRV__HIGH_DRIVE 0x01 /* All pins on P0 use high drive strength. */ + +#define P1DRV__BMASK 0x02 /* Port 1 Drive Strength */ +#define P1DRV__SHIFT 0x01 /* Port 1 Drive Strength */ +#define P1DRV__LOW_DRIVE 0x00 /* All pins on P1 use low drive strength. */ +#define P1DRV__HIGH_DRIVE 0x02 /* All pins on P1 use high drive strength. */ + +#define P2DRV__BMASK 0x04 /* Port 2 Drive Strength */ +#define P2DRV__SHIFT 0x02 /* Port 2 Drive Strength */ +#define P2DRV__LOW_DRIVE 0x00 /* All pins on P2 use low drive strength. */ +#define P2DRV__HIGH_DRIVE 0x04 /* All pins on P2 use high drive strength. */ + +/*------------------------------------------------------------------------------ */ +/* PCON0 Enums (Power Control @ 0x87) */ +/*------------------------------------------------------------------------------ */ +#define IDLE__BMASK 0x01 /* Idle Mode Select */ +#define IDLE__SHIFT 0x00 /* Idle Mode Select */ +#define IDLE__NORMAL 0x00 /* Idle mode not activated. */ +#define IDLE__IDLE 0x01 /* CPU goes into Idle mode (shuts off clock to CPU, but clocks to enabled peripherals are still active). */ + +#define STOP__BMASK 0x02 /* Stop Mode Select */ +#define STOP__SHIFT 0x01 /* Stop Mode Select */ +#define STOP__NORMAL 0x00 /* Stop mode not activated. */ +#define STOP__STOP 0x02 /* CPU goes into Stop mode (internal oscillator stopped). */ + +#define GF0__BMASK 0x04 /* General Purpose Flag 0 */ +#define GF0__SHIFT 0x02 /* General Purpose Flag 0 */ +#define GF0__NOT_SET 0x00 /* The GF0 flag is not set. Clear the GF0 flag. */ +#define GF0__SET 0x04 /* The GF0 flag is set. Set the GF0 flag. */ + +#define GF1__BMASK 0x08 /* General Purpose Flag 1 */ +#define GF1__SHIFT 0x03 /* General Purpose Flag 1 */ +#define GF1__NOT_SET 0x00 /* The GF1 flag is not set. Clear the GF1 flag. */ +#define GF1__SET 0x08 /* The GF1 flag is set. Set the GF1 flag. */ + +#define GF2__BMASK 0x10 /* General Purpose Flag 2 */ +#define GF2__SHIFT 0x04 /* General Purpose Flag 2 */ +#define GF2__NOT_SET 0x00 /* The GF2 flag is not set. Clear the GF2 flag. */ +#define GF2__SET 0x10 /* The GF2 flag is set. Set the GF2 flag. */ + +#define GF3__BMASK 0x20 /* General Purpose Flag 3 */ +#define GF3__SHIFT 0x05 /* General Purpose Flag 3 */ +#define GF3__NOT_SET 0x00 /* The GF3 flag is not set. Clear the GF3 flag. */ +#define GF3__SET 0x20 /* The GF3 flag is set. Set the GF3 flag. */ + +#define GF4__BMASK 0x40 /* General Purpose Flag 4 */ +#define GF4__SHIFT 0x06 /* General Purpose Flag 4 */ +#define GF4__NOT_SET 0x00 /* The GF4 flag is not set. Clear the GF4 flag. */ +#define GF4__SET 0x40 /* The GF4 flag is set. Set the GF4 flag. */ + +#define GF5__BMASK 0x80 /* General Purpose Flag 5 */ +#define GF5__SHIFT 0x07 /* General Purpose Flag 5 */ +#define GF5__NOT_SET 0x00 /* The GF5 flag is not set. Clear the GF5 flag. */ +#define GF5__SET 0x80 /* The GF5 flag is set. Set the GF5 flag. */ + +/*------------------------------------------------------------------------------ */ +/* RSTSRC Enums (Reset Source @ 0xEF) */ +/*------------------------------------------------------------------------------ */ +#define PINRSF__BMASK 0x01 /* HW Pin Reset Flag */ +#define PINRSF__SHIFT 0x00 /* HW Pin Reset Flag */ +#define PINRSF__NOT_SET 0x00 /* The RSTb pin did not cause the last reset. */ +#define PINRSF__SET 0x01 /* The RSTb pin caused the last reset. */ + +#define PORSF__BMASK 0x02 /* Power-On / Supply Monitor Reset Flag, and Supply Monitor Reset Enable */ +#define PORSF__SHIFT 0x01 /* Power-On / Supply Monitor Reset Flag, and Supply Monitor Reset Enable */ +#define PORSF__NOT_SET 0x00 /* A power-on or supply monitor reset did not occur. */ +#define PORSF__SET 0x02 /* A power-on or supply monitor reset occurred. */ + +#define MCDRSF__BMASK 0x04 /* Missing Clock Detector Enable and Flag */ +#define MCDRSF__SHIFT 0x02 /* Missing Clock Detector Enable and Flag */ +#define MCDRSF__NOT_SET 0x00 /* A missing clock detector reset did not occur. */ +#define MCDRSF__SET 0x04 /* A missing clock detector reset occurred. */ + +#define WDTRSF__BMASK 0x08 /* Watchdog Timer Reset Flag */ +#define WDTRSF__SHIFT 0x03 /* Watchdog Timer Reset Flag */ +#define WDTRSF__NOT_SET 0x00 /* A watchdog timer overflow reset did not occur. */ +#define WDTRSF__SET 0x08 /* A watchdog timer overflow reset occurred. */ + +#define SWRSF__BMASK 0x10 /* Software Reset Force and Flag */ +#define SWRSF__SHIFT 0x04 /* Software Reset Force and Flag */ +#define SWRSF__NOT_SET 0x00 /* A software reset did not occur. */ +#define SWRSF__SET 0x10 /* A software reset occurred. */ + +#define C0RSEF__BMASK 0x20 /* Comparator0 Reset Enable and Flag */ +#define C0RSEF__SHIFT 0x05 /* Comparator0 Reset Enable and Flag */ +#define C0RSEF__NOT_SET 0x00 /* A Comparator 0 reset did not occur. */ +#define C0RSEF__SET 0x20 /* A Comparator 0 reset occurred. */ + +#define FERROR__BMASK 0x40 /* Flash Error Reset Flag */ +#define FERROR__SHIFT 0x06 /* Flash Error Reset Flag */ +#define FERROR__NOT_SET 0x00 /* A flash error reset did not occur. */ +#define FERROR__SET 0x40 /* A flash error reset occurred. */ + +/*------------------------------------------------------------------------------ */ +/* CKCON0 Enums (Clock Control 0 @ 0x8E) */ +/*------------------------------------------------------------------------------ */ +#define SCA__FMASK 0x03 /* Timer 0/1 Prescale */ +#define SCA__SHIFT 0x00 /* Timer 0/1 Prescale */ +#define SCA__SYSCLK_DIV_12 0x00 /* System clock divided by 12. */ +#define SCA__SYSCLK_DIV_4 0x01 /* System clock divided by 4. */ +#define SCA__SYSCLK_DIV_48 0x02 /* System clock divided by 48. */ +#define SCA__EXTOSC_DIV_8 0x03 /* External oscillator divided by 8 (synchronized with the system clock). */ + +#define T0M__PRESCALE 0x00 /* Counter/Timer 0 uses the clock defined by the prescale field, SCA. */ +#define T0M__SYSCLK 0x04 /* Counter/Timer 0 uses the system clock. */ + +#define T1M__PRESCALE 0x00 /* Timer 1 uses the clock defined by the prescale field, SCA. */ +#define T1M__SYSCLK 0x08 /* Timer 1 uses the system clock. */ + +#define T2ML__BMASK 0x10 /* Timer 2 Low Byte Clock Select */ +#define T2ML__SHIFT 0x04 /* Timer 2 Low Byte Clock Select */ +#define T2ML__EXTERNAL_CLOCK 0x00 /* Timer 2 low byte uses the clock defined by T2XCLK in TMR2CN0. */ +#define T2ML__SYSCLK 0x10 /* Timer 2 low byte uses the system clock. */ + +#define T2MH__BMASK 0x20 /* Timer 2 High Byte Clock Select */ +#define T2MH__SHIFT 0x05 /* Timer 2 High Byte Clock Select */ +#define T2MH__EXTERNAL_CLOCK 0x00 /* Timer 2 high byte uses the clock defined by T2XCLK in TMR2CN0. */ +#define T2MH__SYSCLK 0x20 /* Timer 2 high byte uses the system clock. */ + +#define T3ML__BMASK 0x40 /* Timer 3 Low Byte Clock Select */ +#define T3ML__SHIFT 0x06 /* Timer 3 Low Byte Clock Select */ +#define T3ML__EXTERNAL_CLOCK 0x00 /* Timer 3 low byte uses the clock defined by T3XCLK in TMR3CN0. */ +#define T3ML__SYSCLK 0x40 /* Timer 3 low byte uses the system clock. */ + +#define T3MH__BMASK 0x80 /* Timer 3 High Byte Clock Select */ +#define T3MH__SHIFT 0x07 /* Timer 3 High Byte Clock Select */ +#define T3MH__EXTERNAL_CLOCK 0x00 /* Timer 3 high byte uses the clock defined by T3XCLK in TMR3CN0. */ +#define T3MH__SYSCLK 0x80 /* Timer 3 high byte uses the system clock. */ + +/*------------------------------------------------------------------------------ */ +/* TCON Enums (Timer 0/1 Control @ 0x88) */ +/*------------------------------------------------------------------------------ */ +#define IT0__BMASK 0x01 /* Interrupt 0 Type Select */ +#define IT0__SHIFT 0x00 /* Interrupt 0 Type Select */ +#define IT0__LEVEL 0x00 /* INT0 is level triggered. */ +#define IT0__EDGE 0x01 /* INT0 is edge triggered. */ + +#define IE0__BMASK 0x02 /* External Interrupt 0 */ +#define IE0__SHIFT 0x01 /* External Interrupt 0 */ +#define IE0__NOT_SET 0x00 /* Edge/level not detected. */ +#define IE0__SET 0x02 /* Edge/level detected */ + +#define IT1__BMASK 0x04 /* Interrupt 1 Type Select */ +#define IT1__SHIFT 0x02 /* Interrupt 1 Type Select */ +#define IT1__LEVEL 0x00 /* INT1 is level triggered. */ +#define IT1__EDGE 0x04 /* INT1 is edge triggered. */ + +#define IE1__BMASK 0x08 /* External Interrupt 1 */ +#define IE1__SHIFT 0x03 /* External Interrupt 1 */ +#define IE1__NOT_SET 0x00 /* Edge/level not detected. */ +#define IE1__SET 0x08 /* Edge/level detected */ + +#define TR0__BMASK 0x10 /* Timer 0 Run Control */ +#define TR0__SHIFT 0x04 /* Timer 0 Run Control */ +#define TR0__STOP 0x00 /* Stop Timer 0. */ +#define TR0__RUN 0x10 /* Start Timer 0 running. */ + +#define TF0__BMASK 0x20 /* Timer 0 Overflow Flag */ +#define TF0__SHIFT 0x05 /* Timer 0 Overflow Flag */ +#define TF0__NOT_SET 0x00 /* Timer 0 did not overflow. */ +#define TF0__SET 0x20 /* Timer 0 overflowed. */ + +#define TR1__BMASK 0x40 /* Timer 1 Run Control */ +#define TR1__SHIFT 0x06 /* Timer 1 Run Control */ +#define TR1__STOP 0x00 /* Stop Timer 1. */ +#define TR1__RUN 0x40 /* Start Timer 1 running. */ + +#define TF1__BMASK 0x80 /* Timer 1 Overflow Flag */ +#define TF1__SHIFT 0x07 /* Timer 1 Overflow Flag */ +#define TF1__NOT_SET 0x00 /* Timer 1 did not overflow. */ +#define TF1__SET 0x80 /* Timer 1 overflowed. */ + +/*------------------------------------------------------------------------------ */ +/* TMOD Enums (Timer 0/1 Mode @ 0x89) */ +/*------------------------------------------------------------------------------ */ +#define T0M__MODE0 0x00 /* Mode 0, 13-bit Counter/Timer */ +#define T0M__MODE1 0x01 /* Mode 1, 16-bit Counter/Timer */ +#define T0M__MODE2 0x02 /* Mode 2, 8-bit Counter/Timer with Auto-Reload */ +#define T0M__MODE3 0x03 /* Mode 3, Two 8-bit Counter/Timers */ + +#define CT0__BMASK 0x04 /* Counter/Timer 0 Select */ +#define CT0__SHIFT 0x02 /* Counter/Timer 0 Select */ +#define CT0__TIMER 0x00 /* Timer Mode. Timer 0 increments on the clock defined by T0M in the CKCON0 register. */ +#define CT0__COUNTER 0x04 /* Counter Mode. Timer 0 increments on high-to-low transitions of an external pin (T0). */ + +#define GATE0__BMASK 0x08 /* Timer 0 Gate Control */ +#define GATE0__SHIFT 0x03 /* Timer 0 Gate Control */ +#define GATE0__DISABLED 0x00 /* Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level. */ +#define GATE0__ENABLED 0x08 /* Timer 0 enabled only when TR0 = 1 and INT0 is active as defined by bit IN0PL in register IT01CF. */ + +#define T1M__FMASK 0x30 /* Timer 1 Mode Select */ +#define T1M__SHIFT 0x04 /* Timer 1 Mode Select */ +#define T1M__MODE0 0x00 /* Mode 0, 13-bit Counter/Timer */ +#define T1M__MODE1 0x10 /* Mode 1, 16-bit Counter/Timer */ +#define T1M__MODE2 0x20 /* Mode 2, 8-bit Counter/Timer with Auto-Reload */ +#define T1M__MODE3 0x30 /* Mode 3, Timer 1 Inactive */ + +#define CT1__BMASK 0x40 /* Counter/Timer 1 Select */ +#define CT1__SHIFT 0x06 /* Counter/Timer 1 Select */ +#define CT1__TIMER 0x00 /* Timer Mode. Timer 1 increments on the clock defined by T1M in the CKCON0 register. */ +#define CT1__COUNTER 0x40 /* Counter Mode. Timer 1 increments on high-to-low transitions of an external pin (T1). */ + +#define GATE1__BMASK 0x80 /* Timer 1 Gate Control */ +#define GATE1__SHIFT 0x07 /* Timer 1 Gate Control */ +#define GATE1__DISABLED 0x00 /* Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level. */ +#define GATE1__ENABLED 0x80 /* Timer 1 enabled only when TR1 = 1 and INT1 is active as defined by bit IN1PL in register IT01CF. */ + +/*------------------------------------------------------------------------------ */ +/* VDM0CN Enums (Supply Monitor Control @ 0xFF) */ +/*------------------------------------------------------------------------------ */ +#define VDDSTAT__BMASK 0x40 /* Supply Status */ +#define VDDSTAT__SHIFT 0x06 /* Supply Status */ +#define VDDSTAT__BELOW 0x00 /* VDD is at or below the supply monitor threshold. */ +#define VDDSTAT__ABOVE 0x40 /* VDD is above the supply monitor threshold. */ + +#define VDMEN__BMASK 0x80 /* Supply Monitor Enable */ +#define VDMEN__SHIFT 0x07 /* Supply Monitor Enable */ +#define VDMEN__DISABLED 0x00 /* Supply Monitor Disabled. */ +#define VDMEN__ENABLED 0x80 /* Supply Monitor Enabled. */ + +/*------------------------------------------------------------------------------ */ +/* Watchdog Timer Control */ +/*------------------------------------------------------------------------------ */ + +#ifdef WDT_no + +#define WDT_lockout() +#define WDT_reset() +#define WDT_enable() +#define WDT_1ms() +#define WDT_2ms() +#define WDT_13ms() +#define WDT_51ms() +#define WDT_204ms() +#define WDT_819ms() +#define WDT_32767ms() +#define WDT_13107ms() + +#else + +#define WDT_lockout() WDTCN=0xff +#define WDT_reset() WDTCN=0xA5 +#define WDT_enable() WDTCN=0xA5 +#define WDT_1ms() WDTCN=0x00 +#define WDT_2ms() WDTCN=0x01 +#define WDT_13ms() WDTCN=0x02 +#define WDT_51ms() WDTCN=0x03 +#define WDT_204ms() WDTCN=0x04 +#define WDT_819ms() WDTCN=0x05 +#define WDT_32767ms() WDTCN=0x06 +#define WDT_13107ms() WDTCN=0x07 + +#endif /* WDT_no */ + +#endif /* EFM8BB1_H */ /*------------------------------------------------------------------------- SST89x5xRDx.h Register Declarations for SST SST89E516RD2, ST89E516RD, SST89V516RD2, and SST89V516RD Processors @@ -24337,6 +33685,8 @@ SFR(WDTRST, 0xA6); // Watchdog Timer Reset compiler.h Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl + Portions of this file are Copyright 2014 Silicon Laboratories, Inc. + http://developer.silabs.com/legal/version/v11/Silicon_Labs_Software_License_Agreement.txt This library is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the @@ -24414,6 +33764,12 @@ SFR(WDTRST, 0xA6); // Watchdog Timer Reset # define SFR32(name, addr) __sfr32 __at(((addr+3UL)<<24) | ((addr+2UL)<<16) | ((addr+1UL)<<8) | addr) name # define SFR32E(name, fulladdr) __sfr32 __at(fulladdr) name +# define INTERRUPT(name, vector) void name (void) __interrupt (vector) +# define INTERRUPT_USING(name, vector, regnum) void name (void) __interrupt (vector) __using (regnum) + +// NOP () macro support +#define NOP() __asm NOP __endasm + /** Keil C51 * http://www.keil.com */ @@ -24426,6 +33782,13 @@ SFR(WDTRST, 0xA6); // Watchdog Timer Reset # define SFR32(name, fulladdr) /* not supported */ # define SFR32E(name, fulladdr) /* not supported */ +# define INTERRUPT(name, vector) void name (void) interrupt vector +# define INTERRUPT_USING(name, vector, regnum) void name (void) interrupt vector using regnum + +// NOP () macro support +extern void _nop_ (void); +#define NOP() _nop_() + /** Raisonance * http://www.raisonance.com */ @@ -24438,6 +33801,12 @@ SFR(WDTRST, 0xA6); // Watchdog Timer Reset # define SFR32(name, fulladdr) /* not supported */ # define SFR32E(name, fulladdr) /* not supported */ +# define INTERRUPT(name, vector) void name (void) interrupt vector +# define INTERRUPT_USING(name, vector, regnum) void name (void) interrupt vector using regnum + +// NOP () macro support -- NOP is opcode 0x00 +#define NOP() asm { 0x00 } + /** IAR 8051 * http://www.iar.com */ @@ -24450,6 +33819,15 @@ SFR(WDTRST, 0xA6); // Watchdog Timer Reset # define SFR32(name, fulladdr) __sfr __no_init volatile unsigned long name @ addr # define SFR32E(name, fulladdr) /* not supported */ +# define _PPTOSTR_(x) #x +# define _PPARAM_(address) _PPTOSTR_(vector=address * 8 + 3) +# define _PPARAM2_(regbank) _PPTOSTR_(register_bank=regbank) +# define INTERRUPT(name, vector) _Pragma(_PPARAM_(vector)) __interrupt void name(void) +# define INTERRUPT_USING(name, vector, regnum) _Pragma(_PPARAM2_(regnum)) _Pragma(_PPARAM_(vector)) __interrupt void name(void) + +extern __intrinsic void __no_operation (void); +#define NOP() __no_operation() + /** Tasking / Altium * http://www.altium.com/tasking */ @@ -24466,6 +33844,13 @@ SFR(WDTRST, 0xA6); // Watchdog Timer Reset # define SFR32(name, fulladdr) /* not supported */ # define SFR32E(name, fulladdr) /* not supported */ +# define INTERRUPT(name, vector) _interrupt (vector) void name (void) +# define INTERRUPT_USING(name, vector, regnum) _interrupt (vector) _using(regnum) void name (void) + +// NOP () macro support +extern void _nop (void); +#define NOP() _nop() + /** Hi-Tech 8051 * http://www.htsoft.com */ @@ -24478,6 +33863,12 @@ SFR(WDTRST, 0xA6); // Watchdog Timer Reset # define SFR32(name, fulladdr) /* not supported */ # define SFR32E(name, fulladdr) /* not supported */ +# define INTERRUPT(name, vector) void name (void) interrupt vector +# define INTERRUPT_PROTO(name, vector) + +// NOP () macro support +#define NOP() asm(" nop ") + /** Crossware * http://www.crossware.com */ @@ -25222,7 +34613,7 @@ __sfr __at (0xB1) IEN1; //Interrupt Enable 1 __sfr __at (0xB8) IPL0; //Interrupt Priority 0 LOW __sbit __at (0xBE) PPCL;//PCA Interrupt Priority low bit. __sbit __at (0xBD) PT2L;//Timer 2 Interrupt Priority Low Bit. - __sbit __at (0xBC) PLS; //Serial Port Interrupt Priority Low Bit. + __sbit __at (0xBC) PSL; //Serial Port Interrupt Priority Low Bit. __sbit __at (0xBB) PT1L;//Timer 1 Interrupt Priority Low Bit. __sbit __at (0xBA) PX1L;//External Interrupt 1 Priority Low Bit. __sbit __at (0xB9) PT0L;//Timer 0 Interrupt Priority Low Bit. @@ -25231,7 +34622,7 @@ __sfr __at (0xB8) IPL0; //Interrupt Priority 0 LOW __sfr __at (0xB7) IPH0; //Interrupt Priority 0 HIGH #define PPCH 0x40 //PCA Interrupt Priority High Bit. #define PT2H 0x20 //Timer 2 Interrupt Priority High Bit. - #define PHS 0x10 //Serial Port Interrupt Priority High Bit. + #define PSH 0x10 //Serial Port Interrupt Priority High Bit. #define PT1H 0x08 //Timer 1 Interrupt Priority High Bit. #define PX1H 0x04 //External Interrupt 1 Priority High Bit. #define PT0H 0x02 //Timer 0 Interrupt Priority High Bit. @@ -25336,6 +34727,17 @@ __sfr __at (0xD2) EECON; //EEPROM Data Control #define EEE 0x02 //EEPROM Enable. '1'=use EEPROM, '0'=use XRAM #define EEBUSY 0x01 //EEPROM Busy. '1'=EEPROM is busy programming +// PCON bit definitions + #define SMOD1 0x80 + #define SMOD0 0x40 + #define POF 0x10 + +/* Interrupt numbers: address = (number * 8) + 3 */ +#define TF2_VECTOR 5 /* 0x2b timer 2 */ +#define PCA_VECTOR 6 /* 0x33 Programmable Counter Array */ +#define KBD_VECTOR 7 /* 0x3b Keyboard Interface */ +#define SPI_VECTOR 9 /* 0x4b Serial Port Interface */ + #endif /*REG_AT89C51ED2_H*/ /*------------------------------------------------------------------------- C8051F300.h - Register Declarations for the Cygnal/SiLabs C8051F30x @@ -27955,6 +37357,12 @@ SFRX(PGA1TRIM2X4X, 0xffe2); // PGA1 trim register SFRX(RTCDATH, 0xffbf); // Real-time clock data register high SFRX(RTCDATL, 0xffbe); // Real-time clock data register low #endif /*REG_P89LPC9321_H*/ +sdcc/device/include/mcs51 +------------------------- + +A lot of the include files in this subdirectory used to be in the directory +one level up from here. Since CVS doesn't support moving files, these files +were removed there and added here. /*------------------------------------------------------------------------- C8051F326.h - Register Declarations for the Cygnal/SiLabs C8051F326/7 Processor Range @@ -28138,6 +37546,75 @@ __sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG #define SWRSF 0x10 /* RSTSRC */ #endif +/*------------------------------------------------------------------------- + at89c51id2.h: Register Declarations for the Atmel AT89C51ID2 Processor + + Copyright (C) 2014, Victor Munoz / victor at munoz.name + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef REG_AT89C51ID2_H +#define REG_AT89C51ID2_H + +#include // Load definitions for the at89c51ed2.h + +//Clock control Register 0 CKCON0(0x8F) additional definitions + #define TWIX2 0x80 // 2-wire clock (CPU clock X2 only) '1'=12 ck/cy, '0'=6 ck/cy + +// Two wire interface control registers +__sfr __at (0x93) SSCON; // Synchronous Serial Control register (93h) + #define CR2 0x80 // Control Rate bit 2 + #define SSIE 0x40 // Synchronous Serial Interface Enable bit + #define STA 0x20 // Start flag + #define STO 0x10 // Stop flag + #define SI 0x08 // Synchronous Serial Interrupt flag + #define AA 0x04 // Assert Acknowledge flag + #define CR1 0x02 // Control Rate bit 1 + #define CR0 0x01 // Control Rate bit 0 +__sfr __at (0x94) SSCS; // Synchronous Serial Control and Status Register (read) (094h) + #define SC4 0x80 // Status Code bit 4 + #define SC3 0x40 // Status Code bit 3 + #define SC2 0x20 // Status Code bit 2 + #define SC1 0x10 // Status Code bit 1 + #define SC0 0x08 // Status Code bit 0 +__sfr __at (0x95) SSDAT; // Synchronous Serial Data register (read/write) (095h) +__sfr __at (0x96) SSADR; // Synchronous Serial Address Register (read/write) (096h) + #define GC 0x01 // General Call bit + +//Interrupt Enable 1 IEN1(0xB1) additional definitions + #define ETWI 0x02 // Two Wire Interrupt Enable bit. + +//Interrupt Priority 1 LOW IPL1(0xB2) additional definitions + #define TWIL 0x02 + +//Interrupt Priority 1 HIGH IPH1(0xB3) additional definitions + #define TWIH 0x02 + +/* Interrupt numbers: address = (number * 8) + 3 */ +#define TWI_VECTOR 8 /* 0x43 Two wire interface */ + +#endif /*REG_AT89C51ID2_H*/ /*-------------------------------------------------------------------------- P89c51RD2.H (English) @@ -33393,6 +42870,5212 @@ __sfr __at 0x3F ICR ; /* I/O base control register - does not *--------------------------------------------------------------------------- */ #endif /* __Z180_H__ */ +/*------------------------------------------------------------------------- + sdcc-lib.h - SDCC Library Main Header + + Copyright (C) 2004, Vangelis Rokas + Adopted for pic14 port library by Raphael Neider (2006) + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __PIC14_SDCC_LIB_H +#define __PIC14_SDCC_LIB_H 1 + +#include <../asm/pic14/features.h> + +#endif /* __PIC14_SDCC_LIB_H */ +/* + * pic16fam.h - PIC14 families + * + * This file is has been generated using ./pic16fam-h-gen.pl . + */ +#ifndef __SDCC_PIC16FAM_H__ +#define __SDCC_PIC16FAM_H__ 1 + +/* + * Define device class. + */ +#undef __SDCC_PIC14_ENHANCED + +#if defined(__SDCC_PIC12F1501) || \ + defined(__SDCC_PIC12F1571) || \ + defined(__SDCC_PIC12F1572) || \ + defined(__SDCC_PIC12F1612) || \ + defined(__SDCC_PIC12F1822) || \ + defined(__SDCC_PIC12F1840) || \ + defined(__SDCC_PIC12LF1552) || \ + defined(__SDCC_PIC16F1454) || \ + defined(__SDCC_PIC16F1455) || \ + defined(__SDCC_PIC16F1458) || \ + defined(__SDCC_PIC16F1459) || \ + defined(__SDCC_PIC16F1503) || \ + defined(__SDCC_PIC16F1507) || \ + defined(__SDCC_PIC16F1508) || \ + defined(__SDCC_PIC16F1509) || \ + defined(__SDCC_PIC16F1512) || \ + defined(__SDCC_PIC16F1513) || \ + defined(__SDCC_PIC16F1516) || \ + defined(__SDCC_PIC16F1517) || \ + defined(__SDCC_PIC16F1518) || \ + defined(__SDCC_PIC16F1519) || \ + defined(__SDCC_PIC16F1526) || \ + defined(__SDCC_PIC16F1527) || \ + defined(__SDCC_PIC16F1613) || \ + defined(__SDCC_PIC16F1703) || \ + defined(__SDCC_PIC16F1704) || \ + defined(__SDCC_PIC16F1705) || \ + defined(__SDCC_PIC16F1707) || \ + defined(__SDCC_PIC16F1708) || \ + defined(__SDCC_PIC16F1709) || \ + defined(__SDCC_PIC16F1713) || \ + defined(__SDCC_PIC16F1716) || \ + defined(__SDCC_PIC16F1717) || \ + defined(__SDCC_PIC16F1718) || \ + defined(__SDCC_PIC16F1719) || \ + defined(__SDCC_PIC16F1782) || \ + defined(__SDCC_PIC16F1783) || \ + defined(__SDCC_PIC16F1784) || \ + defined(__SDCC_PIC16F1786) || \ + defined(__SDCC_PIC16F1787) || \ + defined(__SDCC_PIC16F1788) || \ + defined(__SDCC_PIC16F1789) || \ + defined(__SDCC_PIC16F1823) || \ + defined(__SDCC_PIC16F1824) || \ + defined(__SDCC_PIC16F1825) || \ + defined(__SDCC_PIC16F1826) || \ + defined(__SDCC_PIC16F1827) || \ + defined(__SDCC_PIC16F1828) || \ + defined(__SDCC_PIC16F1829) || \ + defined(__SDCC_PIC16F1847) || \ + defined(__SDCC_PIC16F1933) || \ + defined(__SDCC_PIC16F1934) || \ + defined(__SDCC_PIC16F1936) || \ + defined(__SDCC_PIC16F1937) || \ + defined(__SDCC_PIC16F1938) || \ + defined(__SDCC_PIC16F1939) || \ + defined(__SDCC_PIC16F1946) || \ + defined(__SDCC_PIC16F1947) || \ + defined(__SDCC_PIC16LF1902) || \ + defined(__SDCC_PIC16LF1903) || \ + defined(__SDCC_PIC16LF1904) || \ + defined(__SDCC_PIC16LF1906) || \ + defined(__SDCC_PIC16LF1907) +#define __SDCC_PIC14_ENHANCED 1 + +#endif + +/* + * Define ADC style per device family. + */ +#undef __SDCC_ADC_STYLE + +#if defined(__SDCC_PIC12F609) || \ + defined(__SDCC_PIC12F629) || \ + defined(__SDCC_PIC12F635) || \ + defined(__SDCC_PIC12LF1552) || \ + defined(__SDCC_PIC16C62) || \ + defined(__SDCC_PIC16C63A) || \ + defined(__SDCC_PIC16C65B) || \ + defined(__SDCC_PIC16C432) || \ + defined(__SDCC_PIC16C554) || \ + defined(__SDCC_PIC16C557) || \ + defined(__SDCC_PIC16C558) || \ + defined(__SDCC_PIC16C620) || \ + defined(__SDCC_PIC16C620A) || \ + defined(__SDCC_PIC16C621) || \ + defined(__SDCC_PIC16C621A) || \ + defined(__SDCC_PIC16C622) || \ + defined(__SDCC_PIC16C622A) || \ + defined(__SDCC_PIC16CR73) || \ + defined(__SDCC_PIC16CR74) || \ + defined(__SDCC_PIC16CR76) || \ + defined(__SDCC_PIC16CR77) || \ + defined(__SDCC_PIC16CR620A) || \ + defined(__SDCC_PIC16F84) || \ + defined(__SDCC_PIC16F84A) || \ + defined(__SDCC_PIC16F87) || \ + defined(__SDCC_PIC16F610) || \ + defined(__SDCC_PIC16F627) || \ + defined(__SDCC_PIC16F627A) || \ + defined(__SDCC_PIC16F628) || \ + defined(__SDCC_PIC16F628A) || \ + defined(__SDCC_PIC16F630) || \ + defined(__SDCC_PIC16F631) || \ + defined(__SDCC_PIC16F636) || \ + defined(__SDCC_PIC16F639) || \ + defined(__SDCC_PIC16F648) || \ + defined(__SDCC_PIC16F648A) || \ + defined(__SDCC_PIC16F1454) || \ + defined(__SDCC_PIC16F1458) || \ + defined(__SDCC_PIC16HV610) +#define __SDCC_ADC_STYLE 0 + +#elif defined(__SDCC_PIC10F320) || \ + defined(__SDCC_PIC10F322) +#define __SDCC_ADC_STYLE 1003201 + +#elif defined(__SDCC_PIC12F615) || \ + defined(__SDCC_PIC12F617) +#define __SDCC_ADC_STYLE 1206151 + +#elif defined(__SDCC_PIC12F675) || \ + defined(__SDCC_PIC12F683) +#define __SDCC_ADC_STYLE 1206751 + +#elif defined(__SDCC_PIC12F752) +#define __SDCC_ADC_STYLE 1207521 + +#elif defined(__SDCC_PIC12F1501) +#define __SDCC_ADC_STYLE 1215011 + +#elif defined(__SDCC_PIC12F1571) || \ + defined(__SDCC_PIC12F1572) +#define __SDCC_ADC_STYLE 1215711 + +#elif defined(__SDCC_PIC12F1612) +#define __SDCC_ADC_STYLE 1216121 + +#elif defined(__SDCC_PIC12F1822) || \ + defined(__SDCC_PIC12F1840) +#define __SDCC_ADC_STYLE 1218221 + +#elif defined(__SDCC_PIC16C71) || \ + defined(__SDCC_PIC16C710) || \ + defined(__SDCC_PIC16C711) +#define __SDCC_ADC_STYLE 1600711 + +#elif defined(__SDCC_PIC16C72) || \ + defined(__SDCC_PIC16C73B) || \ + defined(__SDCC_PIC16F72) || \ + defined(__SDCC_PIC16F73) || \ + defined(__SDCC_PIC16F76) +#define __SDCC_ADC_STYLE 1600721 + +#elif defined(__SDCC_PIC16C74B) || \ + defined(__SDCC_PIC16F74) || \ + defined(__SDCC_PIC16F77) +#define __SDCC_ADC_STYLE 1600741 + +#elif defined(__SDCC_PIC16F88) +#define __SDCC_ADC_STYLE 1600881 + +#elif defined(__SDCC_PIC16C433) +#define __SDCC_ADC_STYLE 1604331 + +#elif defined(__SDCC_PIC16F616) || \ + defined(__SDCC_PIC16HV616) +#define __SDCC_ADC_STYLE 1606161 + +#elif defined(__SDCC_PIC16F676) || \ + defined(__SDCC_PIC16F684) || \ + defined(__SDCC_PIC16F688) +#define __SDCC_ADC_STYLE 1606761 + +#elif defined(__SDCC_PIC16F677) || \ + defined(__SDCC_PIC16F685) || \ + defined(__SDCC_PIC16F687) || \ + defined(__SDCC_PIC16F689) || \ + defined(__SDCC_PIC16F690) +#define __SDCC_ADC_STYLE 1606771 + +#elif defined(__SDCC_PIC16F707) +#define __SDCC_ADC_STYLE 1607071 + +#elif defined(__SDCC_PIC16C715) +#define __SDCC_ADC_STYLE 1607151 + +#elif defined(__SDCC_PIC16F716) +#define __SDCC_ADC_STYLE 1607161 + +#elif defined(__SDCC_PIC16C717) || \ + defined(__SDCC_PIC16C770) || \ + defined(__SDCC_PIC16C771) +#define __SDCC_ADC_STYLE 1607171 + +#elif defined(__SDCC_PIC16F720) || \ + defined(__SDCC_PIC16F721) +#define __SDCC_ADC_STYLE 1607201 + +#elif defined(__SDCC_PIC16F722) || \ + defined(__SDCC_PIC16F722A) || \ + defined(__SDCC_PIC16F723) || \ + defined(__SDCC_PIC16F723A) || \ + defined(__SDCC_PIC16F726) +#define __SDCC_ADC_STYLE 1607221 + +#elif defined(__SDCC_PIC16F724) || \ + defined(__SDCC_PIC16F727) +#define __SDCC_ADC_STYLE 1607241 + +#elif defined(__SDCC_PIC16F737) || \ + defined(__SDCC_PIC16F767) +#define __SDCC_ADC_STYLE 1607371 + +#elif defined(__SDCC_PIC16C745) +#define __SDCC_ADC_STYLE 1607451 + +#elif defined(__SDCC_PIC16F747) || \ + defined(__SDCC_PIC16F777) +#define __SDCC_ADC_STYLE 1607471 + +#elif defined(__SDCC_PIC16F753) || \ + defined(__SDCC_PIC16HV753) +#define __SDCC_ADC_STYLE 1607531 + +#elif defined(__SDCC_PIC16C765) +#define __SDCC_ADC_STYLE 1607651 + +#elif defined(__SDCC_PIC16C773) +#define __SDCC_ADC_STYLE 1607731 + +#elif defined(__SDCC_PIC16C774) +#define __SDCC_ADC_STYLE 1607741 + +#elif defined(__SDCC_PIC16C781) || \ + defined(__SDCC_PIC16C782) +#define __SDCC_ADC_STYLE 1607811 + +#elif defined(__SDCC_PIC16F785) || \ + defined(__SDCC_PIC16HV785) +#define __SDCC_ADC_STYLE 1607851 + +#elif defined(__SDCC_PIC16F818) || \ + defined(__SDCC_PIC16F819) +#define __SDCC_ADC_STYLE 1608181 + +#elif defined(__SDCC_PIC16F871) || \ + defined(__SDCC_PIC16F874) || \ + defined(__SDCC_PIC16F874A) || \ + defined(__SDCC_PIC16F877) || \ + defined(__SDCC_PIC16F877A) +#define __SDCC_ADC_STYLE 1608711 + +#elif defined(__SDCC_PIC16F882) || \ + defined(__SDCC_PIC16F883) || \ + defined(__SDCC_PIC16F886) +#define __SDCC_ADC_STYLE 1608821 + +#elif defined(__SDCC_PIC16F884) || \ + defined(__SDCC_PIC16F887) +#define __SDCC_ADC_STYLE 1608841 + +#elif defined(__SDCC_PIC16F913) || \ + defined(__SDCC_PIC16F916) +#define __SDCC_ADC_STYLE 1609131 + +#elif defined(__SDCC_PIC16F914) || \ + defined(__SDCC_PIC16F917) || \ + defined(__SDCC_PIC16F946) +#define __SDCC_ADC_STYLE 1609141 + +#elif defined(__SDCC_PIC16C925) || \ + defined(__SDCC_PIC16C926) || \ + defined(__SDCC_PIC16F870) || \ + defined(__SDCC_PIC16F872) || \ + defined(__SDCC_PIC16F873) || \ + defined(__SDCC_PIC16F873A) || \ + defined(__SDCC_PIC16F876) || \ + defined(__SDCC_PIC16F876A) +#define __SDCC_ADC_STYLE 1609251 + +#elif defined(__SDCC_PIC16F1455) +#define __SDCC_ADC_STYLE 1614551 + +#elif defined(__SDCC_PIC16F1459) +#define __SDCC_ADC_STYLE 1614591 + +#elif defined(__SDCC_PIC16F1503) +#define __SDCC_ADC_STYLE 1615031 + +#elif defined(__SDCC_PIC16F1507) || \ + defined(__SDCC_PIC16F1508) || \ + defined(__SDCC_PIC16F1509) +#define __SDCC_ADC_STYLE 1615071 + +#elif defined(__SDCC_PIC16F1512) || \ + defined(__SDCC_PIC16F1513) || \ + defined(__SDCC_PIC16F1516) || \ + defined(__SDCC_PIC16F1518) +#define __SDCC_ADC_STYLE 1615121 + +#elif defined(__SDCC_PIC16F1517) || \ + defined(__SDCC_PIC16F1519) +#define __SDCC_ADC_STYLE 1615171 + +#elif defined(__SDCC_PIC16F1526) || \ + defined(__SDCC_PIC16F1527) +#define __SDCC_ADC_STYLE 1615261 + +#elif defined(__SDCC_PIC16F1613) +#define __SDCC_ADC_STYLE 1616131 + +#elif defined(__SDCC_PIC16F1703) +#define __SDCC_ADC_STYLE 1617031 + +#elif defined(__SDCC_PIC16F1704) || \ + defined(__SDCC_PIC16F1705) +#define __SDCC_ADC_STYLE 1617041 + +#elif defined(__SDCC_PIC16F1707) +#define __SDCC_ADC_STYLE 1617071 + +#elif defined(__SDCC_PIC16F1708) +#define __SDCC_ADC_STYLE 1617081 + +#elif defined(__SDCC_PIC16F1709) +#define __SDCC_ADC_STYLE 1617091 + +#elif defined(__SDCC_PIC16F1713) || \ + defined(__SDCC_PIC16F1716) || \ + defined(__SDCC_PIC16F1718) +#define __SDCC_ADC_STYLE 1617131 + +#elif defined(__SDCC_PIC16F1717) || \ + defined(__SDCC_PIC16F1719) +#define __SDCC_ADC_STYLE 1617171 + +#elif defined(__SDCC_PIC16F1782) || \ + defined(__SDCC_PIC16F1783) || \ + defined(__SDCC_PIC16F1786) +#define __SDCC_ADC_STYLE 1617821 + +#elif defined(__SDCC_PIC16F1784) || \ + defined(__SDCC_PIC16F1787) +#define __SDCC_ADC_STYLE 1617841 + +#elif defined(__SDCC_PIC16F1788) +#define __SDCC_ADC_STYLE 1617881 + +#elif defined(__SDCC_PIC16F1789) +#define __SDCC_ADC_STYLE 1617891 + +#elif defined(__SDCC_PIC16F1823) +#define __SDCC_ADC_STYLE 1618231 + +#elif defined(__SDCC_PIC16F1824) || \ + defined(__SDCC_PIC16F1825) +#define __SDCC_ADC_STYLE 1618241 + +#elif defined(__SDCC_PIC16F1826) || \ + defined(__SDCC_PIC16F1827) || \ + defined(__SDCC_PIC16F1847) +#define __SDCC_ADC_STYLE 1618261 + +#elif defined(__SDCC_PIC16F1828) || \ + defined(__SDCC_PIC16F1829) +#define __SDCC_ADC_STYLE 1618281 + +#elif defined(__SDCC_PIC16LF1902) || \ + defined(__SDCC_PIC16LF1903) || \ + defined(__SDCC_PIC16LF1906) +#define __SDCC_ADC_STYLE 1619021 + +#elif defined(__SDCC_PIC16LF1904) || \ + defined(__SDCC_PIC16LF1907) +#define __SDCC_ADC_STYLE 1619041 + +#elif defined(__SDCC_PIC16F1933) || \ + defined(__SDCC_PIC16F1936) || \ + defined(__SDCC_PIC16F1938) +#define __SDCC_ADC_STYLE 1619331 + +#elif defined(__SDCC_PIC16F1934) || \ + defined(__SDCC_PIC16F1937) || \ + defined(__SDCC_PIC16F1939) +#define __SDCC_ADC_STYLE 1619341 + +#elif defined(__SDCC_PIC16F1946) || \ + defined(__SDCC_PIC16F1947) +#define __SDCC_ADC_STYLE 1619461 + +#else +#warning No ADC style associated with the target device. +#warning Please update your pic14/pic16fam.h manually and/or inform the maintainer. +#endif + +/* + * Define PWM style per device family. + */ +#undef __SDCC_PWM_STYLE + +#if defined(__SDCC_PIC12F609) || \ + defined(__SDCC_PIC12F629) || \ + defined(__SDCC_PIC12F635) || \ + defined(__SDCC_PIC12F675) || \ + defined(__SDCC_PIC12LF1552) || \ + defined(__SDCC_PIC16C71) || \ + defined(__SDCC_PIC16C432) || \ + defined(__SDCC_PIC16C433) || \ + defined(__SDCC_PIC16C554) || \ + defined(__SDCC_PIC16C557) || \ + defined(__SDCC_PIC16C558) || \ + defined(__SDCC_PIC16C620) || \ + defined(__SDCC_PIC16C620A) || \ + defined(__SDCC_PIC16C621) || \ + defined(__SDCC_PIC16C621A) || \ + defined(__SDCC_PIC16C622) || \ + defined(__SDCC_PIC16C622A) || \ + defined(__SDCC_PIC16C710) || \ + defined(__SDCC_PIC16C711) || \ + defined(__SDCC_PIC16C715) || \ + defined(__SDCC_PIC16C781) || \ + defined(__SDCC_PIC16C782) || \ + defined(__SDCC_PIC16CR73) || \ + defined(__SDCC_PIC16CR74) || \ + defined(__SDCC_PIC16CR76) || \ + defined(__SDCC_PIC16CR77) || \ + defined(__SDCC_PIC16CR620A) || \ + defined(__SDCC_PIC16F84) || \ + defined(__SDCC_PIC16F84A) || \ + defined(__SDCC_PIC16F610) || \ + defined(__SDCC_PIC16F630) || \ + defined(__SDCC_PIC16F631) || \ + defined(__SDCC_PIC16F636) || \ + defined(__SDCC_PIC16F639) || \ + defined(__SDCC_PIC16F648) || \ + defined(__SDCC_PIC16F676) || \ + defined(__SDCC_PIC16F677) || \ + defined(__SDCC_PIC16F687) || \ + defined(__SDCC_PIC16F688) || \ + defined(__SDCC_PIC16F689) || \ + defined(__SDCC_PIC16F1458) || \ + defined(__SDCC_PIC16HV610) || \ + defined(__SDCC_PIC16LF1902) || \ + defined(__SDCC_PIC16LF1903) || \ + defined(__SDCC_PIC16LF1904) || \ + defined(__SDCC_PIC16LF1906) || \ + defined(__SDCC_PIC16LF1907) +#define __SDCC_PWM_STYLE 0 + +#elif defined(__SDCC_PIC10F320) || \ + defined(__SDCC_PIC10F322) +#define __SDCC_PWM_STYLE 1003202 + +#elif defined(__SDCC_PIC12F615) || \ + defined(__SDCC_PIC12F617) +#define __SDCC_PWM_STYLE 1206152 + +#elif defined(__SDCC_PIC12F683) +#define __SDCC_PWM_STYLE 1206832 + +#elif defined(__SDCC_PIC12F752) +#define __SDCC_PWM_STYLE 1207522 + +#elif defined(__SDCC_PIC12F1501) +#define __SDCC_PWM_STYLE 1215012 + +#elif defined(__SDCC_PIC12F1571) || \ + defined(__SDCC_PIC12F1572) +#define __SDCC_PWM_STYLE 1215712 + +#elif defined(__SDCC_PIC12F1612) +#define __SDCC_PWM_STYLE 1216122 + +#elif defined(__SDCC_PIC12F1822) || \ + defined(__SDCC_PIC12F1840) +#define __SDCC_PWM_STYLE 1218222 + +#elif defined(__SDCC_PIC16C62) || \ + defined(__SDCC_PIC16C72) || \ + defined(__SDCC_PIC16C925) || \ + defined(__SDCC_PIC16C926) || \ + defined(__SDCC_PIC16F72) || \ + defined(__SDCC_PIC16F870) || \ + defined(__SDCC_PIC16F871) || \ + defined(__SDCC_PIC16F872) +#define __SDCC_PWM_STYLE 1600622 + +#elif defined(__SDCC_PIC16C63A) || \ + defined(__SDCC_PIC16C65B) || \ + defined(__SDCC_PIC16C73B) || \ + defined(__SDCC_PIC16C74B) || \ + defined(__SDCC_PIC16C745) || \ + defined(__SDCC_PIC16C765) || \ + defined(__SDCC_PIC16C773) || \ + defined(__SDCC_PIC16C774) || \ + defined(__SDCC_PIC16F73) || \ + defined(__SDCC_PIC16F74) || \ + defined(__SDCC_PIC16F76) || \ + defined(__SDCC_PIC16F77) || \ + defined(__SDCC_PIC16F873) || \ + defined(__SDCC_PIC16F873A) || \ + defined(__SDCC_PIC16F874) || \ + defined(__SDCC_PIC16F874A) || \ + defined(__SDCC_PIC16F876) || \ + defined(__SDCC_PIC16F876A) || \ + defined(__SDCC_PIC16F877) || \ + defined(__SDCC_PIC16F877A) +#define __SDCC_PWM_STYLE 1600632 + +#elif defined(__SDCC_PIC16F87) || \ + defined(__SDCC_PIC16F88) +#define __SDCC_PWM_STYLE 1600872 + +#elif defined(__SDCC_PIC16F616) || \ + defined(__SDCC_PIC16F684) || \ + defined(__SDCC_PIC16HV616) +#define __SDCC_PWM_STYLE 1606162 + +#elif defined(__SDCC_PIC16F627) || \ + defined(__SDCC_PIC16F627A) || \ + defined(__SDCC_PIC16F628) || \ + defined(__SDCC_PIC16F628A) || \ + defined(__SDCC_PIC16F648A) +#define __SDCC_PWM_STYLE 1606272 + +#elif defined(__SDCC_PIC16F685) || \ + defined(__SDCC_PIC16F690) +#define __SDCC_PWM_STYLE 1606852 + +#elif defined(__SDCC_PIC16F707) +#define __SDCC_PWM_STYLE 1607072 + +#elif defined(__SDCC_PIC16C717) || \ + defined(__SDCC_PIC16C770) || \ + defined(__SDCC_PIC16C771) || \ + defined(__SDCC_PIC16F716) +#define __SDCC_PWM_STYLE 1607172 + +#elif defined(__SDCC_PIC16F720) || \ + defined(__SDCC_PIC16F721) || \ + defined(__SDCC_PIC16F913) || \ + defined(__SDCC_PIC16F916) +#define __SDCC_PWM_STYLE 1607202 + +#elif defined(__SDCC_PIC16F722) || \ + defined(__SDCC_PIC16F722A) || \ + defined(__SDCC_PIC16F723) || \ + defined(__SDCC_PIC16F723A) || \ + defined(__SDCC_PIC16F724) || \ + defined(__SDCC_PIC16F726) || \ + defined(__SDCC_PIC16F727) +#define __SDCC_PWM_STYLE 1607222 + +#elif defined(__SDCC_PIC16F737) || \ + defined(__SDCC_PIC16F747) || \ + defined(__SDCC_PIC16F767) || \ + defined(__SDCC_PIC16F777) +#define __SDCC_PWM_STYLE 1607372 + +#elif defined(__SDCC_PIC16F753) || \ + defined(__SDCC_PIC16HV753) +#define __SDCC_PWM_STYLE 1607532 + +#elif defined(__SDCC_PIC16F785) || \ + defined(__SDCC_PIC16HV785) +#define __SDCC_PWM_STYLE 1607852 + +#elif defined(__SDCC_PIC16F818) || \ + defined(__SDCC_PIC16F819) +#define __SDCC_PWM_STYLE 1608182 + +#elif defined(__SDCC_PIC16F882) || \ + defined(__SDCC_PIC16F883) || \ + defined(__SDCC_PIC16F884) || \ + defined(__SDCC_PIC16F886) || \ + defined(__SDCC_PIC16F887) +#define __SDCC_PWM_STYLE 1608822 + +#elif defined(__SDCC_PIC16F914) || \ + defined(__SDCC_PIC16F917) || \ + defined(__SDCC_PIC16F946) +#define __SDCC_PWM_STYLE 1609142 + +#elif defined(__SDCC_PIC16F1454) || \ + defined(__SDCC_PIC16F1455) +#define __SDCC_PWM_STYLE 1614542 + +#elif defined(__SDCC_PIC16F1459) +#define __SDCC_PWM_STYLE 1614592 + +#elif defined(__SDCC_PIC16F1503) || \ + defined(__SDCC_PIC16F1507) || \ + defined(__SDCC_PIC16F1508) || \ + defined(__SDCC_PIC16F1509) +#define __SDCC_PWM_STYLE 1615032 + +#elif defined(__SDCC_PIC16F1512) || \ + defined(__SDCC_PIC16F1513) || \ + defined(__SDCC_PIC16F1516) || \ + defined(__SDCC_PIC16F1517) || \ + defined(__SDCC_PIC16F1518) || \ + defined(__SDCC_PIC16F1519) +#define __SDCC_PWM_STYLE 1615122 + +#elif defined(__SDCC_PIC16F1526) || \ + defined(__SDCC_PIC16F1527) +#define __SDCC_PWM_STYLE 1615262 + +#elif defined(__SDCC_PIC16F1613) +#define __SDCC_PWM_STYLE 1616132 + +#elif defined(__SDCC_PIC16F1703) +#define __SDCC_PWM_STYLE 1617032 + +#elif defined(__SDCC_PIC16F1704) || \ + defined(__SDCC_PIC16F1705) +#define __SDCC_PWM_STYLE 1617042 + +#elif defined(__SDCC_PIC16F1707) +#define __SDCC_PWM_STYLE 1617072 + +#elif defined(__SDCC_PIC16F1708) +#define __SDCC_PWM_STYLE 1617082 + +#elif defined(__SDCC_PIC16F1709) +#define __SDCC_PWM_STYLE 1617092 + +#elif defined(__SDCC_PIC16F1713) || \ + defined(__SDCC_PIC16F1716) || \ + defined(__SDCC_PIC16F1718) +#define __SDCC_PWM_STYLE 1617132 + +#elif defined(__SDCC_PIC16F1717) || \ + defined(__SDCC_PIC16F1719) +#define __SDCC_PWM_STYLE 1617172 + +#elif defined(__SDCC_PIC16F1782) || \ + defined(__SDCC_PIC16F1783) +#define __SDCC_PWM_STYLE 1617822 + +#elif defined(__SDCC_PIC16F1784) || \ + defined(__SDCC_PIC16F1787) +#define __SDCC_PWM_STYLE 1617842 + +#elif defined(__SDCC_PIC16F1786) +#define __SDCC_PWM_STYLE 1617862 + +#elif defined(__SDCC_PIC16F1788) +#define __SDCC_PWM_STYLE 1617882 + +#elif defined(__SDCC_PIC16F1789) +#define __SDCC_PWM_STYLE 1617892 + +#elif defined(__SDCC_PIC16F1823) +#define __SDCC_PWM_STYLE 1618232 + +#elif defined(__SDCC_PIC16F1824) || \ + defined(__SDCC_PIC16F1825) +#define __SDCC_PWM_STYLE 1618242 + +#elif defined(__SDCC_PIC16F1826) +#define __SDCC_PWM_STYLE 1618262 + +#elif defined(__SDCC_PIC16F1827) || \ + defined(__SDCC_PIC16F1847) +#define __SDCC_PWM_STYLE 1618272 + +#elif defined(__SDCC_PIC16F1828) || \ + defined(__SDCC_PIC16F1829) +#define __SDCC_PWM_STYLE 1618282 + +#elif defined(__SDCC_PIC16F1933) || \ + defined(__SDCC_PIC16F1936) || \ + defined(__SDCC_PIC16F1938) +#define __SDCC_PWM_STYLE 1619332 + +#elif defined(__SDCC_PIC16F1934) || \ + defined(__SDCC_PIC16F1937) || \ + defined(__SDCC_PIC16F1939) +#define __SDCC_PWM_STYLE 1619342 + +#elif defined(__SDCC_PIC16F1946) || \ + defined(__SDCC_PIC16F1947) +#define __SDCC_PWM_STYLE 1619462 + +#else +#warning No PWM style associated with the target device. +#warning Please update your pic14/pic16fam.h manually and/or inform the maintainer. +#endif + +/* + * Define SSP style per device family. + */ +#undef __SDCC_SSP_STYLE + +#if defined(__SDCC_PIC10F320) || \ + defined(__SDCC_PIC10F322) || \ + defined(__SDCC_PIC12F609) || \ + defined(__SDCC_PIC12F615) || \ + defined(__SDCC_PIC12F617) || \ + defined(__SDCC_PIC12F629) || \ + defined(__SDCC_PIC12F635) || \ + defined(__SDCC_PIC12F675) || \ + defined(__SDCC_PIC12F683) || \ + defined(__SDCC_PIC12F752) || \ + defined(__SDCC_PIC12F1501) || \ + defined(__SDCC_PIC12F1571) || \ + defined(__SDCC_PIC12F1572) || \ + defined(__SDCC_PIC12F1612) || \ + defined(__SDCC_PIC12LF1552) || \ + defined(__SDCC_PIC16C71) || \ + defined(__SDCC_PIC16C432) || \ + defined(__SDCC_PIC16C433) || \ + defined(__SDCC_PIC16C554) || \ + defined(__SDCC_PIC16C557) || \ + defined(__SDCC_PIC16C558) || \ + defined(__SDCC_PIC16C620) || \ + defined(__SDCC_PIC16C620A) || \ + defined(__SDCC_PIC16C621) || \ + defined(__SDCC_PIC16C621A) || \ + defined(__SDCC_PIC16C622) || \ + defined(__SDCC_PIC16C622A) || \ + defined(__SDCC_PIC16C710) || \ + defined(__SDCC_PIC16C711) || \ + defined(__SDCC_PIC16C715) || \ + defined(__SDCC_PIC16C745) || \ + defined(__SDCC_PIC16C765) || \ + defined(__SDCC_PIC16C781) || \ + defined(__SDCC_PIC16C782) || \ + defined(__SDCC_PIC16CR73) || \ + defined(__SDCC_PIC16CR74) || \ + defined(__SDCC_PIC16CR76) || \ + defined(__SDCC_PIC16CR77) || \ + defined(__SDCC_PIC16CR620A) || \ + defined(__SDCC_PIC16F84) || \ + defined(__SDCC_PIC16F84A) || \ + defined(__SDCC_PIC16F610) || \ + defined(__SDCC_PIC16F616) || \ + defined(__SDCC_PIC16F627) || \ + defined(__SDCC_PIC16F627A) || \ + defined(__SDCC_PIC16F628) || \ + defined(__SDCC_PIC16F628A) || \ + defined(__SDCC_PIC16F630) || \ + defined(__SDCC_PIC16F631) || \ + defined(__SDCC_PIC16F636) || \ + defined(__SDCC_PIC16F639) || \ + defined(__SDCC_PIC16F648) || \ + defined(__SDCC_PIC16F648A) || \ + defined(__SDCC_PIC16F676) || \ + defined(__SDCC_PIC16F684) || \ + defined(__SDCC_PIC16F685) || \ + defined(__SDCC_PIC16F688) || \ + defined(__SDCC_PIC16F716) || \ + defined(__SDCC_PIC16F753) || \ + defined(__SDCC_PIC16F785) || \ + defined(__SDCC_PIC16F870) || \ + defined(__SDCC_PIC16F871) || \ + defined(__SDCC_PIC16F1458) || \ + defined(__SDCC_PIC16F1507) || \ + defined(__SDCC_PIC16F1613) || \ + defined(__SDCC_PIC16HV610) || \ + defined(__SDCC_PIC16HV616) || \ + defined(__SDCC_PIC16HV753) || \ + defined(__SDCC_PIC16HV785) || \ + defined(__SDCC_PIC16LF1902) || \ + defined(__SDCC_PIC16LF1903) || \ + defined(__SDCC_PIC16LF1904) || \ + defined(__SDCC_PIC16LF1906) || \ + defined(__SDCC_PIC16LF1907) +#define __SDCC_SSP_STYLE 0 + +#elif defined(__SDCC_PIC12F1822) || \ + defined(__SDCC_PIC12F1840) +#define __SDCC_SSP_STYLE 1218223 + +#elif defined(__SDCC_PIC16C62) || \ + defined(__SDCC_PIC16C72) +#define __SDCC_SSP_STYLE 1600623 + +#elif defined(__SDCC_PIC16C63A) || \ + defined(__SDCC_PIC16C65B) +#define __SDCC_SSP_STYLE 1600633 + +#elif defined(__SDCC_PIC16F72) || \ + defined(__SDCC_PIC16F73) || \ + defined(__SDCC_PIC16F74) || \ + defined(__SDCC_PIC16F76) || \ + defined(__SDCC_PIC16F77) +#define __SDCC_SSP_STYLE 1600723 + +#elif defined(__SDCC_PIC16C73B) || \ + defined(__SDCC_PIC16C74B) +#define __SDCC_SSP_STYLE 1600733 + +#elif defined(__SDCC_PIC16F87) || \ + defined(__SDCC_PIC16F88) || \ + defined(__SDCC_PIC16F818) || \ + defined(__SDCC_PIC16F819) +#define __SDCC_SSP_STYLE 1600873 + +#elif defined(__SDCC_PIC16F677) || \ + defined(__SDCC_PIC16F687) || \ + defined(__SDCC_PIC16F689) || \ + defined(__SDCC_PIC16F690) +#define __SDCC_SSP_STYLE 1606773 + +#elif defined(__SDCC_PIC16F707) +#define __SDCC_SSP_STYLE 1607073 + +#elif defined(__SDCC_PIC16C717) || \ + defined(__SDCC_PIC16C770) || \ + defined(__SDCC_PIC16C771) +#define __SDCC_SSP_STYLE 1607173 + +#elif defined(__SDCC_PIC16F720) || \ + defined(__SDCC_PIC16F721) +#define __SDCC_SSP_STYLE 1607203 + +#elif defined(__SDCC_PIC16F722) || \ + defined(__SDCC_PIC16F722A) || \ + defined(__SDCC_PIC16F723) || \ + defined(__SDCC_PIC16F723A) || \ + defined(__SDCC_PIC16F724) || \ + defined(__SDCC_PIC16F726) || \ + defined(__SDCC_PIC16F727) +#define __SDCC_SSP_STYLE 1607223 + +#elif defined(__SDCC_PIC16F737) || \ + defined(__SDCC_PIC16F747) || \ + defined(__SDCC_PIC16F767) || \ + defined(__SDCC_PIC16F777) +#define __SDCC_SSP_STYLE 1607373 + +#elif defined(__SDCC_PIC16C773) || \ + defined(__SDCC_PIC16C774) +#define __SDCC_SSP_STYLE 1607733 + +#elif defined(__SDCC_PIC16F872) || \ + defined(__SDCC_PIC16F873) || \ + defined(__SDCC_PIC16F873A) || \ + defined(__SDCC_PIC16F874) || \ + defined(__SDCC_PIC16F874A) || \ + defined(__SDCC_PIC16F876) || \ + defined(__SDCC_PIC16F876A) || \ + defined(__SDCC_PIC16F877) || \ + defined(__SDCC_PIC16F877A) +#define __SDCC_SSP_STYLE 1608723 + +#elif defined(__SDCC_PIC16F882) || \ + defined(__SDCC_PIC16F883) || \ + defined(__SDCC_PIC16F884) || \ + defined(__SDCC_PIC16F886) || \ + defined(__SDCC_PIC16F887) +#define __SDCC_SSP_STYLE 1608823 + +#elif defined(__SDCC_PIC16F913) || \ + defined(__SDCC_PIC16F914) || \ + defined(__SDCC_PIC16F916) || \ + defined(__SDCC_PIC16F917) || \ + defined(__SDCC_PIC16F946) +#define __SDCC_SSP_STYLE 1609133 + +#elif defined(__SDCC_PIC16C925) || \ + defined(__SDCC_PIC16C926) +#define __SDCC_SSP_STYLE 1609253 + +#elif defined(__SDCC_PIC16F1454) || \ + defined(__SDCC_PIC16F1455) +#define __SDCC_SSP_STYLE 1614543 + +#elif defined(__SDCC_PIC16F1459) +#define __SDCC_SSP_STYLE 1614593 + +#elif defined(__SDCC_PIC16F1503) +#define __SDCC_SSP_STYLE 1615033 + +#elif defined(__SDCC_PIC16F1508) || \ + defined(__SDCC_PIC16F1509) +#define __SDCC_SSP_STYLE 1615083 + +#elif defined(__SDCC_PIC16F1512) || \ + defined(__SDCC_PIC16F1513) || \ + defined(__SDCC_PIC16F1516) || \ + defined(__SDCC_PIC16F1517) || \ + defined(__SDCC_PIC16F1518) || \ + defined(__SDCC_PIC16F1519) +#define __SDCC_SSP_STYLE 1615123 + +#elif defined(__SDCC_PIC16F1526) || \ + defined(__SDCC_PIC16F1527) +#define __SDCC_SSP_STYLE 1615263 + +#elif defined(__SDCC_PIC16F1703) +#define __SDCC_SSP_STYLE 1617033 + +#elif defined(__SDCC_PIC16F1704) || \ + defined(__SDCC_PIC16F1705) +#define __SDCC_SSP_STYLE 1617043 + +#elif defined(__SDCC_PIC16F1707) +#define __SDCC_SSP_STYLE 1617073 + +#elif defined(__SDCC_PIC16F1708) +#define __SDCC_SSP_STYLE 1617083 + +#elif defined(__SDCC_PIC16F1709) +#define __SDCC_SSP_STYLE 1617093 + +#elif defined(__SDCC_PIC16F1713) || \ + defined(__SDCC_PIC16F1716) || \ + defined(__SDCC_PIC16F1718) +#define __SDCC_SSP_STYLE 1617133 + +#elif defined(__SDCC_PIC16F1717) || \ + defined(__SDCC_PIC16F1719) +#define __SDCC_SSP_STYLE 1617173 + +#elif defined(__SDCC_PIC16F1782) || \ + defined(__SDCC_PIC16F1783) || \ + defined(__SDCC_PIC16F1784) || \ + defined(__SDCC_PIC16F1786) || \ + defined(__SDCC_PIC16F1787) +#define __SDCC_SSP_STYLE 1617823 + +#elif defined(__SDCC_PIC16F1788) +#define __SDCC_SSP_STYLE 1617883 + +#elif defined(__SDCC_PIC16F1789) +#define __SDCC_SSP_STYLE 1617893 + +#elif defined(__SDCC_PIC16F1823) || \ + defined(__SDCC_PIC16F1824) || \ + defined(__SDCC_PIC16F1825) +#define __SDCC_SSP_STYLE 1618233 + +#elif defined(__SDCC_PIC16F1826) +#define __SDCC_SSP_STYLE 1618263 + +#elif defined(__SDCC_PIC16F1827) || \ + defined(__SDCC_PIC16F1847) +#define __SDCC_SSP_STYLE 1618273 + +#elif defined(__SDCC_PIC16F1828) +#define __SDCC_SSP_STYLE 1618283 + +#elif defined(__SDCC_PIC16F1829) +#define __SDCC_SSP_STYLE 1618293 + +#elif defined(__SDCC_PIC16F1933) || \ + defined(__SDCC_PIC16F1934) || \ + defined(__SDCC_PIC16F1936) || \ + defined(__SDCC_PIC16F1937) || \ + defined(__SDCC_PIC16F1938) || \ + defined(__SDCC_PIC16F1939) +#define __SDCC_SSP_STYLE 1619333 + +#elif defined(__SDCC_PIC16F1946) || \ + defined(__SDCC_PIC16F1947) +#define __SDCC_SSP_STYLE 1619463 + +#else +#warning No SSP style associated with the target device. +#warning Please update your pic14/pic16fam.h manually and/or inform the maintainer. +#endif + +/* + * Define USART style per device family. + */ +#undef __SDCC_USART_STYLE + +#if defined(__SDCC_PIC10F320) || \ + defined(__SDCC_PIC10F322) || \ + defined(__SDCC_PIC12F609) || \ + defined(__SDCC_PIC12F615) || \ + defined(__SDCC_PIC12F617) || \ + defined(__SDCC_PIC12F629) || \ + defined(__SDCC_PIC12F635) || \ + defined(__SDCC_PIC12F675) || \ + defined(__SDCC_PIC12F683) || \ + defined(__SDCC_PIC12F752) || \ + defined(__SDCC_PIC12F1501) || \ + defined(__SDCC_PIC12F1571) || \ + defined(__SDCC_PIC12F1612) || \ + defined(__SDCC_PIC12LF1552) || \ + defined(__SDCC_PIC16C62) || \ + defined(__SDCC_PIC16C71) || \ + defined(__SDCC_PIC16C72) || \ + defined(__SDCC_PIC16C432) || \ + defined(__SDCC_PIC16C433) || \ + defined(__SDCC_PIC16C554) || \ + defined(__SDCC_PIC16C557) || \ + defined(__SDCC_PIC16C558) || \ + defined(__SDCC_PIC16C620) || \ + defined(__SDCC_PIC16C620A) || \ + defined(__SDCC_PIC16C621) || \ + defined(__SDCC_PIC16C621A) || \ + defined(__SDCC_PIC16C622) || \ + defined(__SDCC_PIC16C622A) || \ + defined(__SDCC_PIC16C710) || \ + defined(__SDCC_PIC16C711) || \ + defined(__SDCC_PIC16C715) || \ + defined(__SDCC_PIC16C717) || \ + defined(__SDCC_PIC16C770) || \ + defined(__SDCC_PIC16C771) || \ + defined(__SDCC_PIC16C781) || \ + defined(__SDCC_PIC16C782) || \ + defined(__SDCC_PIC16C925) || \ + defined(__SDCC_PIC16C926) || \ + defined(__SDCC_PIC16CR73) || \ + defined(__SDCC_PIC16CR74) || \ + defined(__SDCC_PIC16CR76) || \ + defined(__SDCC_PIC16CR77) || \ + defined(__SDCC_PIC16CR620A) || \ + defined(__SDCC_PIC16F72) || \ + defined(__SDCC_PIC16F84) || \ + defined(__SDCC_PIC16F84A) || \ + defined(__SDCC_PIC16F610) || \ + defined(__SDCC_PIC16F616) || \ + defined(__SDCC_PIC16F630) || \ + defined(__SDCC_PIC16F631) || \ + defined(__SDCC_PIC16F636) || \ + defined(__SDCC_PIC16F639) || \ + defined(__SDCC_PIC16F648) || \ + defined(__SDCC_PIC16F676) || \ + defined(__SDCC_PIC16F677) || \ + defined(__SDCC_PIC16F684) || \ + defined(__SDCC_PIC16F685) || \ + defined(__SDCC_PIC16F716) || \ + defined(__SDCC_PIC16F753) || \ + defined(__SDCC_PIC16F785) || \ + defined(__SDCC_PIC16F818) || \ + defined(__SDCC_PIC16F819) || \ + defined(__SDCC_PIC16F872) || \ + defined(__SDCC_PIC16F1458) || \ + defined(__SDCC_PIC16F1503) || \ + defined(__SDCC_PIC16F1507) || \ + defined(__SDCC_PIC16F1613) || \ + defined(__SDCC_PIC16F1703) || \ + defined(__SDCC_PIC16HV610) || \ + defined(__SDCC_PIC16HV616) || \ + defined(__SDCC_PIC16HV753) || \ + defined(__SDCC_PIC16HV785) || \ + defined(__SDCC_PIC16LF1902) || \ + defined(__SDCC_PIC16LF1903) +#define __SDCC_USART_STYLE 0 + +#elif defined(__SDCC_PIC12F1572) +#define __SDCC_USART_STYLE 1215724 + +#elif defined(__SDCC_PIC12F1822) || \ + defined(__SDCC_PIC12F1840) +#define __SDCC_USART_STYLE 1218224 + +#elif defined(__SDCC_PIC16C63A) || \ + defined(__SDCC_PIC16C65B) || \ + defined(__SDCC_PIC16C73B) || \ + defined(__SDCC_PIC16C74B) || \ + defined(__SDCC_PIC16C745) || \ + defined(__SDCC_PIC16C765) || \ + defined(__SDCC_PIC16F73) || \ + defined(__SDCC_PIC16F74) || \ + defined(__SDCC_PIC16F76) || \ + defined(__SDCC_PIC16F77) +#define __SDCC_USART_STYLE 1600634 + +#elif defined(__SDCC_PIC16F87) || \ + defined(__SDCC_PIC16F88) +#define __SDCC_USART_STYLE 1600874 + +#elif defined(__SDCC_PIC16F627) || \ + defined(__SDCC_PIC16F627A) || \ + defined(__SDCC_PIC16F628) || \ + defined(__SDCC_PIC16F628A) || \ + defined(__SDCC_PIC16F648A) +#define __SDCC_USART_STYLE 1606274 + +#elif defined(__SDCC_PIC16F687) || \ + defined(__SDCC_PIC16F689) || \ + defined(__SDCC_PIC16F690) +#define __SDCC_USART_STYLE 1606874 + +#elif defined(__SDCC_PIC16F688) +#define __SDCC_USART_STYLE 1606884 + +#elif defined(__SDCC_PIC16F707) +#define __SDCC_USART_STYLE 1607074 + +#elif defined(__SDCC_PIC16F720) || \ + defined(__SDCC_PIC16F721) +#define __SDCC_USART_STYLE 1607204 + +#elif defined(__SDCC_PIC16C773) || \ + defined(__SDCC_PIC16C774) || \ + defined(__SDCC_PIC16F722) || \ + defined(__SDCC_PIC16F722A) || \ + defined(__SDCC_PIC16F723) || \ + defined(__SDCC_PIC16F723A) || \ + defined(__SDCC_PIC16F724) || \ + defined(__SDCC_PIC16F726) || \ + defined(__SDCC_PIC16F727) || \ + defined(__SDCC_PIC16F737) || \ + defined(__SDCC_PIC16F747) || \ + defined(__SDCC_PIC16F767) || \ + defined(__SDCC_PIC16F777) || \ + defined(__SDCC_PIC16F870) || \ + defined(__SDCC_PIC16F871) || \ + defined(__SDCC_PIC16F873) || \ + defined(__SDCC_PIC16F873A) || \ + defined(__SDCC_PIC16F874) || \ + defined(__SDCC_PIC16F874A) || \ + defined(__SDCC_PIC16F876) || \ + defined(__SDCC_PIC16F876A) || \ + defined(__SDCC_PIC16F877) || \ + defined(__SDCC_PIC16F877A) || \ + defined(__SDCC_PIC16F913) || \ + defined(__SDCC_PIC16F914) || \ + defined(__SDCC_PIC16F916) || \ + defined(__SDCC_PIC16F917) || \ + defined(__SDCC_PIC16F946) +#define __SDCC_USART_STYLE 1607734 + +#elif defined(__SDCC_PIC16F882) || \ + defined(__SDCC_PIC16F883) || \ + defined(__SDCC_PIC16F884) || \ + defined(__SDCC_PIC16F886) || \ + defined(__SDCC_PIC16F887) +#define __SDCC_USART_STYLE 1608824 + +#elif defined(__SDCC_PIC16F1454) || \ + defined(__SDCC_PIC16F1455) +#define __SDCC_USART_STYLE 1614544 + +#elif defined(__SDCC_PIC16F1459) +#define __SDCC_USART_STYLE 1614594 + +#elif defined(__SDCC_PIC16F1508) || \ + defined(__SDCC_PIC16F1509) +#define __SDCC_USART_STYLE 1615084 + +#elif defined(__SDCC_PIC16F1512) || \ + defined(__SDCC_PIC16F1513) || \ + defined(__SDCC_PIC16F1516) || \ + defined(__SDCC_PIC16F1517) || \ + defined(__SDCC_PIC16F1518) || \ + defined(__SDCC_PIC16F1519) +#define __SDCC_USART_STYLE 1615124 + +#elif defined(__SDCC_PIC16F1526) || \ + defined(__SDCC_PIC16F1527) +#define __SDCC_USART_STYLE 1615264 + +#elif defined(__SDCC_PIC16F1704) || \ + defined(__SDCC_PIC16F1705) +#define __SDCC_USART_STYLE 1617044 + +#elif defined(__SDCC_PIC16F1707) +#define __SDCC_USART_STYLE 1617074 + +#elif defined(__SDCC_PIC16F1708) +#define __SDCC_USART_STYLE 1617084 + +#elif defined(__SDCC_PIC16F1709) +#define __SDCC_USART_STYLE 1617094 + +#elif defined(__SDCC_PIC16F1713) || \ + defined(__SDCC_PIC16F1716) || \ + defined(__SDCC_PIC16F1718) +#define __SDCC_USART_STYLE 1617134 + +#elif defined(__SDCC_PIC16F1717) || \ + defined(__SDCC_PIC16F1719) +#define __SDCC_USART_STYLE 1617174 + +#elif defined(__SDCC_PIC16F1782) || \ + defined(__SDCC_PIC16F1783) || \ + defined(__SDCC_PIC16F1784) || \ + defined(__SDCC_PIC16F1786) || \ + defined(__SDCC_PIC16F1787) +#define __SDCC_USART_STYLE 1617824 + +#elif defined(__SDCC_PIC16F1788) +#define __SDCC_USART_STYLE 1617884 + +#elif defined(__SDCC_PIC16F1789) +#define __SDCC_USART_STYLE 1617894 + +#elif defined(__SDCC_PIC16F1823) || \ + defined(__SDCC_PIC16F1824) || \ + defined(__SDCC_PIC16F1825) +#define __SDCC_USART_STYLE 1618234 + +#elif defined(__SDCC_PIC16F1826) || \ + defined(__SDCC_PIC16F1827) || \ + defined(__SDCC_PIC16F1847) +#define __SDCC_USART_STYLE 1618264 + +#elif defined(__SDCC_PIC16F1828) || \ + defined(__SDCC_PIC16F1829) +#define __SDCC_USART_STYLE 1618284 + +#elif defined(__SDCC_PIC16F1933) || \ + defined(__SDCC_PIC16F1934) || \ + defined(__SDCC_PIC16F1936) || \ + defined(__SDCC_PIC16F1937) || \ + defined(__SDCC_PIC16F1938) || \ + defined(__SDCC_PIC16F1939) || \ + defined(__SDCC_PIC16LF1904) || \ + defined(__SDCC_PIC16LF1906) || \ + defined(__SDCC_PIC16LF1907) +#define __SDCC_USART_STYLE 1619334 + +#elif defined(__SDCC_PIC16F1946) || \ + defined(__SDCC_PIC16F1947) +#define __SDCC_USART_STYLE 1619464 + +#else +#warning No USART style associated with the target device. +#warning Please update your pic14/pic16fam.h manually and/or inform the maintainer. +#endif + +#endif /* !__SDCC_PIC16FAM_H__ */ +/*------------------------------------------------------------------------- + errno.h - Error codes used in the math functions + + Copyright (C) 2001, Jesus Calvino-Fraga + Ported to PIC port by Vangelis Rokas, 2004 + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef _PIC14_ERRNO_H +#define _PIC14_ERRNO_H + +extern int errno; + +/* Error Codes: */ + +#define EDOM 33 /* Math argument out of domain of functions */ +#define ERANGE 34 /* Math result not representable */ + +#endif /* _PIC14_ERRNO_H */ +;-------------------------------------------------------------------------- +; p16f_common.inc - definitions common to all 14 bit PIC devices +; +; Copyright (C) 2005, Vangelis Rokas +; +; This library is free software; you can redistribute it and/or modify it +; under the terms of the GNU General Public License as published by the +; Free Software Foundation; either version 2, or (at your option) any +; later version. +; +; This library is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this library; see the file COPYING. If not, write to the +; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, +; MA 02110-1301, USA. +; +; As a special exception, if you link this library with other files, +; some of which are compiled with SDCC, to produce an executable, +; this library does not by itself cause the resulting executable to +; be covered by the GNU General Public License. This exception does +; not however invalidate any other reasons why the executable file +; might be covered by the GNU General Public License. +;-------------------------------------------------------------------------- + + extern STK00 + extern STK01 + extern STK02 + extern STK03 + extern STK04 + extern STK05 + +/*------------------------------------------------------------------------- + limits.h - ANSI defines constants for sizes of integral types + + Copyright (C) 1998, Sandeep Dutta + Adopted for pic16 port library by Vangelis Rokas (2004) + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __LIMITS_H +#define __LIMITS_H 1 + +#define CHAR_BIT 8 /* bits in a char */ +#define SCHAR_MAX 127 +#define SCHAR_MIN -128 +#define UCHAR_MAX 0xff +#define UCHAR_MIN 0 +#ifdef __SDCC_CHAR_UNSIGNED +#define CHAR_MAX UCHAR_MAX +#define CHAR_MIN UCHAR_MIN +#else +#define CHAR_MAX SCHAR_MAX +#define CHAR_MIN SCHAR_MIN +#endif +#define INT_MIN -32768 +#define INT_MAX 32767 +#define SHRT_MAX INT_MAX +#define SHRT_MIN INT_MIN +#define UINT_MAX 0xffff +#define UINT_MIN 0 +#define USHRT_MAX UINT_MAX +#define USHRT_MIN UINT_MIN +#define LONG_MIN -2147483648 +#define LONG_MAX 2147483647 +#define ULONG_MAX 0xffffffff +#define ULONG_MIN 0 + +#endif +/*------------------------------------------------------------------------- + float.h - ANSI functions forward declarations + + Copyright (C) 1998, Sandeep Dutta + Adopted for pic16 port library by Vangelis Rokas (2004) + Adopted for pic14 port library by Raphael Neider (2006) + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __PIC14_FLOAT_H +#define __PIC14_FLOAT_H 1 + +#include +#include + +#define FLT_RADIX 2 +#define FLT_MANT_DIG 24 +#define FLT_EPSILON 1.192092896E-07F +#define FLT_DIG 6 +#define FLT_MIN_EXP (-125) +#define FLT_MIN 1.175494351E-38F +#define FLT_MIN_10_EXP (-37) +#define FLT_MAX_EXP (+128) +#define FLT_MAX 3.402823466E+38F +#define FLT_MAX_10_EXP (+38) + +/* the following deal with IEEE single-precision numbers */ +#define EXCESS 126 +#define SIGNBIT ((unsigned long)0x80000000) +#define HIDDEN (unsigned long)(1ul << 23) +#define SIGN(fp) (((unsigned long)(fp) >> (8*sizeof(fp)-1)) & 1) +#define EXP(fp) (((unsigned long)(fp) >> 23) & (unsigned int) 0x00FF) +#define MANT(fp) (((fp) & (unsigned long)0x007FFFFF) | HIDDEN) +#define NORM 0xff000000 +#define PACK(s,e,m) ((s) | ((unsigned long)(e) << 23) | (m)) + +/* Workaround for unhandled local variables. */ +#define FS_STATIC /*static*/ + + +float __uchar2fs (unsigned char) _FS_REENTRANT; +float __schar2fs (signed char) _FS_REENTRANT; +float __uint2fs (unsigned int) _FS_REENTRANT; +float __sint2fs (signed int) _FS_REENTRANT; +float __ulong2fs (unsigned long) _FS_REENTRANT; +float __slong2fs (signed long) _FS_REENTRANT; +unsigned char __fs2uchar (float) _FS_REENTRANT; +signed char __fs2schar (float) _FS_REENTRANT; +unsigned int __fs2uint (float) _FS_REENTRANT; +signed int __fs2sint (float) _FS_REENTRANT; +unsigned long __fs2ulong (float) _FS_REENTRANT; +signed long __fs2slong (float) _FS_REENTRANT; + +float __fsadd (float, float) _FS_REENTRANT; +float __fssub (float, float) _FS_REENTRANT; +float __fsmul (float, float) _FS_REENTRANT; +float __fsdiv (float, float) _FS_REENTRANT; + +char __fslt (float, float) _FS_REENTRANT; +char __fseq (float, float) _FS_REENTRANT; +char __fsneq (float, float) _FS_REENTRANT; +char __fsgt (float, float) _FS_REENTRANT; + +#endif /* __PIC14_FLOAT_H */ +/* + * + * This file is generated automatically by the device-manager.pl program. + * + * Copyright (C) 2012-2016, Molnar Karoly + * + */ + +#ifndef __PIC16REGS_H__ +#define __PIC16REGS_H__ + +#if defined(__SDCC_PIC10F320) + #include + +#elif defined(__SDCC_PIC10F322) + #include + +#elif defined(__SDCC_PIC10LF320) + #include + +#elif defined(__SDCC_PIC10LF322) + #include + +#elif defined(__SDCC_PIC12F609) + #include + +#elif defined(__SDCC_PIC12F615) + #include + +#elif defined(__SDCC_PIC12F617) + #include + +#elif defined(__SDCC_PIC12F629) + #include + +#elif defined(__SDCC_PIC12F635) + #include + +#elif defined(__SDCC_PIC12F675) + #include + +#elif defined(__SDCC_PIC12F683) + #include + +#elif defined(__SDCC_PIC12F752) + #include + +#elif defined(__SDCC_PIC12F1501) + #include + +#elif defined(__SDCC_PIC12F1571) + #include + +#elif defined(__SDCC_PIC12F1572) + #include + +#elif defined(__SDCC_PIC12F1612) + #include + +#elif defined(__SDCC_PIC12F1822) + #include + +#elif defined(__SDCC_PIC12F1840) + #include + +#elif defined(__SDCC_PIC12HV752) + #include + +#elif defined(__SDCC_PIC12LF1501) + #include + +#elif defined(__SDCC_PIC12LF1552) + #include + +#elif defined(__SDCC_PIC12LF1571) + #include + +#elif defined(__SDCC_PIC12LF1572) + #include + +#elif defined(__SDCC_PIC12LF1612) + #include + +#elif defined(__SDCC_PIC12LF1822) + #include + +#elif defined(__SDCC_PIC12LF1840) + #include + +#elif defined(__SDCC_PIC12LF1840T39A) + #include + +#elif defined(__SDCC_PIC12LF1840T48A) + #include + +#elif defined(__SDCC_PIC16C62) + #include + +#elif defined(__SDCC_PIC16C63A) + #include + +#elif defined(__SDCC_PIC16C65B) + #include + +#elif defined(__SDCC_PIC16C71) + #include + +#elif defined(__SDCC_PIC16C72) + #include + +#elif defined(__SDCC_PIC16C73B) + #include + +#elif defined(__SDCC_PIC16C74B) + #include + +#elif defined(__SDCC_PIC16C432) + #include + +#elif defined(__SDCC_PIC16C433) + #include + +#elif defined(__SDCC_PIC16C554) + #include + +#elif defined(__SDCC_PIC16C557) + #include + +#elif defined(__SDCC_PIC16C558) + #include + +#elif defined(__SDCC_PIC16C620) + #include + +#elif defined(__SDCC_PIC16C620A) + #include + +#elif defined(__SDCC_PIC16C621) + #include + +#elif defined(__SDCC_PIC16C621A) + #include + +#elif defined(__SDCC_PIC16C622) + #include + +#elif defined(__SDCC_PIC16C622A) + #include + +#elif defined(__SDCC_PIC16C710) + #include + +#elif defined(__SDCC_PIC16C711) + #include + +#elif defined(__SDCC_PIC16C715) + #include + +#elif defined(__SDCC_PIC16C717) + #include + +#elif defined(__SDCC_PIC16C745) + #include + +#elif defined(__SDCC_PIC16C765) + #include + +#elif defined(__SDCC_PIC16C770) + #include + +#elif defined(__SDCC_PIC16C771) + #include + +#elif defined(__SDCC_PIC16C773) + #include + +#elif defined(__SDCC_PIC16C774) + #include + +#elif defined(__SDCC_PIC16C781) + #include + +#elif defined(__SDCC_PIC16C782) + #include + +#elif defined(__SDCC_PIC16C925) + #include + +#elif defined(__SDCC_PIC16C926) + #include + +#elif defined(__SDCC_PIC16F72) + #include + +#elif defined(__SDCC_PIC16F73) + #include + +#elif defined(__SDCC_PIC16F74) + #include + +#elif defined(__SDCC_PIC16F76) + #include + +#elif defined(__SDCC_PIC16F77) + #include + +#elif defined(__SDCC_PIC16F84) + #include + +#elif defined(__SDCC_PIC16F84A) + #include + +#elif defined(__SDCC_PIC16F87) + #include + +#elif defined(__SDCC_PIC16F88) + #include + +#elif defined(__SDCC_PIC16F610) + #include + +#elif defined(__SDCC_PIC16F616) + #include + +#elif defined(__SDCC_PIC16F627) + #include + +#elif defined(__SDCC_PIC16F627A) + #include + +#elif defined(__SDCC_PIC16F628) + #include + +#elif defined(__SDCC_PIC16F628A) + #include + +#elif defined(__SDCC_PIC16F630) + #include + +#elif defined(__SDCC_PIC16F631) + #include + +#elif defined(__SDCC_PIC16F636) + #include + +#elif defined(__SDCC_PIC16F639) + #include + +#elif defined(__SDCC_PIC16F648A) + #include + +#elif defined(__SDCC_PIC16F676) + #include + +#elif defined(__SDCC_PIC16F677) + #include + +#elif defined(__SDCC_PIC16F684) + #include + +#elif defined(__SDCC_PIC16F685) + #include + +#elif defined(__SDCC_PIC16F687) + #include + +#elif defined(__SDCC_PIC16F688) + #include + +#elif defined(__SDCC_PIC16F689) + #include + +#elif defined(__SDCC_PIC16F690) + #include + +#elif defined(__SDCC_PIC16F707) + #include + +#elif defined(__SDCC_PIC16F716) + #include + +#elif defined(__SDCC_PIC16F720) + #include + +#elif defined(__SDCC_PIC16F721) + #include + +#elif defined(__SDCC_PIC16F722) + #include + +#elif defined(__SDCC_PIC16F722A) + #include + +#elif defined(__SDCC_PIC16F723) + #include + +#elif defined(__SDCC_PIC16F723A) + #include + +#elif defined(__SDCC_PIC16F724) + #include + +#elif defined(__SDCC_PIC16F726) + #include + +#elif defined(__SDCC_PIC16F727) + #include + +#elif defined(__SDCC_PIC16F737) + #include + +#elif defined(__SDCC_PIC16F747) + #include + +#elif defined(__SDCC_PIC16F753) + #include + +#elif defined(__SDCC_PIC16F767) + #include + +#elif defined(__SDCC_PIC16F777) + #include + +#elif defined(__SDCC_PIC16F785) + #include + +#elif defined(__SDCC_PIC16F818) + #include + +#elif defined(__SDCC_PIC16F819) + #include + +#elif defined(__SDCC_PIC16F870) + #include + +#elif defined(__SDCC_PIC16F871) + #include + +#elif defined(__SDCC_PIC16F872) + #include + +#elif defined(__SDCC_PIC16F873) + #include + +#elif defined(__SDCC_PIC16F873A) + #include + +#elif defined(__SDCC_PIC16F874) + #include + +#elif defined(__SDCC_PIC16F874A) + #include + +#elif defined(__SDCC_PIC16F876) + #include + +#elif defined(__SDCC_PIC16F876A) + #include + +#elif defined(__SDCC_PIC16F877) + #include + +#elif defined(__SDCC_PIC16F877A) + #include + +#elif defined(__SDCC_PIC16F882) + #include + +#elif defined(__SDCC_PIC16F883) + #include + +#elif defined(__SDCC_PIC16F884) + #include + +#elif defined(__SDCC_PIC16F886) + #include + +#elif defined(__SDCC_PIC16F887) + #include + +#elif defined(__SDCC_PIC16F913) + #include + +#elif defined(__SDCC_PIC16F914) + #include + +#elif defined(__SDCC_PIC16F916) + #include + +#elif defined(__SDCC_PIC16F917) + #include + +#elif defined(__SDCC_PIC16F946) + #include + +#elif defined(__SDCC_PIC16F1454) + #include + +#elif defined(__SDCC_PIC16F1455) + #include + +#elif defined(__SDCC_PIC16F1458) + #include + +#elif defined(__SDCC_PIC16F1459) + #include + +#elif defined(__SDCC_PIC16F1503) + #include + +#elif defined(__SDCC_PIC16F1507) + #include + +#elif defined(__SDCC_PIC16F1508) + #include + +#elif defined(__SDCC_PIC16F1509) + #include + +#elif defined(__SDCC_PIC16F1512) + #include + +#elif defined(__SDCC_PIC16F1513) + #include + +#elif defined(__SDCC_PIC16F1516) + #include + +#elif defined(__SDCC_PIC16F1517) + #include + +#elif defined(__SDCC_PIC16F1518) + #include + +#elif defined(__SDCC_PIC16F1519) + #include + +#elif defined(__SDCC_PIC16F1526) + #include + +#elif defined(__SDCC_PIC16F1527) + #include + +#elif defined(__SDCC_PIC16F1574) + #include + +#elif defined(__SDCC_PIC16F1575) + #include + +#elif defined(__SDCC_PIC16F1578) + #include + +#elif defined(__SDCC_PIC16F1579) + #include + +#elif defined(__SDCC_PIC16F1613) + #include + +#elif defined(__SDCC_PIC16F1614) + #include + +#elif defined(__SDCC_PIC16F1615) + #include + +#elif defined(__SDCC_PIC16F1618) + #include + +#elif defined(__SDCC_PIC16F1619) + #include + +#elif defined(__SDCC_PIC16F1703) + #include + +#elif defined(__SDCC_PIC16F1704) + #include + +#elif defined(__SDCC_PIC16F1705) + #include + +#elif defined(__SDCC_PIC16F1707) + #include + +#elif defined(__SDCC_PIC16F1708) + #include + +#elif defined(__SDCC_PIC16F1709) + #include + +#elif defined(__SDCC_PIC16F1713) + #include + +#elif defined(__SDCC_PIC16F1716) + #include + +#elif defined(__SDCC_PIC16F1717) + #include + +#elif defined(__SDCC_PIC16F1718) + #include + +#elif defined(__SDCC_PIC16F1719) + #include + +#elif defined(__SDCC_PIC16F1764) + #include + +#elif defined(__SDCC_PIC16F1765) + #include + +#elif defined(__SDCC_PIC16F1768) + #include + +#elif defined(__SDCC_PIC16F1769) + #include + +#elif defined(__SDCC_PIC16F1773) + #include + +#elif defined(__SDCC_PIC16F1776) + #include + +#elif defined(__SDCC_PIC16F1777) + #include + +#elif defined(__SDCC_PIC16F1778) + #include + +#elif defined(__SDCC_PIC16F1779) + #include + +#elif defined(__SDCC_PIC16F1782) + #include + +#elif defined(__SDCC_PIC16F1783) + #include + +#elif defined(__SDCC_PIC16F1784) + #include + +#elif defined(__SDCC_PIC16F1786) + #include + +#elif defined(__SDCC_PIC16F1787) + #include + +#elif defined(__SDCC_PIC16F1788) + #include + +#elif defined(__SDCC_PIC16F1789) + #include + +#elif defined(__SDCC_PIC16F1823) + #include + +#elif defined(__SDCC_PIC16F1824) + #include + +#elif defined(__SDCC_PIC16F1825) + #include + +#elif defined(__SDCC_PIC16F1826) + #include + +#elif defined(__SDCC_PIC16F1827) + #include + +#elif defined(__SDCC_PIC16F1828) + #include + +#elif defined(__SDCC_PIC16F1829) + #include + +#elif defined(__SDCC_PIC16F1829LIN) + #include + +#elif defined(__SDCC_PIC16F1847) + #include + +#elif defined(__SDCC_PIC16F1933) + #include + +#elif defined(__SDCC_PIC16F1934) + #include + +#elif defined(__SDCC_PIC16F1936) + #include + +#elif defined(__SDCC_PIC16F1937) + #include + +#elif defined(__SDCC_PIC16F1938) + #include + +#elif defined(__SDCC_PIC16F1939) + #include + +#elif defined(__SDCC_PIC16F1946) + #include + +#elif defined(__SDCC_PIC16F1947) + #include + +#elif defined(__SDCC_PIC16F18313) + #include + +#elif defined(__SDCC_PIC16F18323) + #include + +#elif defined(__SDCC_PIC16F18324) + #include + +#elif defined(__SDCC_PIC16F18325) + #include + +#elif defined(__SDCC_PIC16F18344) + #include + +#elif defined(__SDCC_PIC16F18345) + #include + +#elif defined(__SDCC_PIC16F18855) + #include + +#elif defined(__SDCC_PIC16F18875) + #include + +#elif defined(__SDCC_PIC16HV616) + #include + +#elif defined(__SDCC_PIC16HV753) + #include + +#elif defined(__SDCC_PIC16LF74) + #include + +#elif defined(__SDCC_PIC16LF76) + #include + +#elif defined(__SDCC_PIC16LF77) + #include + +#elif defined(__SDCC_PIC16LF84) + #include + +#elif defined(__SDCC_PIC16LF84A) + #include + +#elif defined(__SDCC_PIC16LF87) + #include + +#elif defined(__SDCC_PIC16LF88) + #include + +#elif defined(__SDCC_PIC16LF627) + #include + +#elif defined(__SDCC_PIC16LF627A) + #include + +#elif defined(__SDCC_PIC16LF628) + #include + +#elif defined(__SDCC_PIC16LF628A) + #include + +#elif defined(__SDCC_PIC16LF648A) + #include + +#elif defined(__SDCC_PIC16LF707) + #include + +#elif defined(__SDCC_PIC16LF720) + #include + +#elif defined(__SDCC_PIC16LF721) + #include + +#elif defined(__SDCC_PIC16LF722) + #include + +#elif defined(__SDCC_PIC16LF722A) + #include + +#elif defined(__SDCC_PIC16LF723) + #include + +#elif defined(__SDCC_PIC16LF723A) + #include + +#elif defined(__SDCC_PIC16LF724) + #include + +#elif defined(__SDCC_PIC16LF726) + #include + +#elif defined(__SDCC_PIC16LF727) + #include + +#elif defined(__SDCC_PIC16LF747) + #include + +#elif defined(__SDCC_PIC16LF767) + #include + +#elif defined(__SDCC_PIC16LF777) + #include + +#elif defined(__SDCC_PIC16LF818) + #include + +#elif defined(__SDCC_PIC16LF819) + #include + +#elif defined(__SDCC_PIC16LF870) + #include + +#elif defined(__SDCC_PIC16LF871) + #include + +#elif defined(__SDCC_PIC16LF872) + #include + +#elif defined(__SDCC_PIC16LF873) + #include + +#elif defined(__SDCC_PIC16LF873A) + #include + +#elif defined(__SDCC_PIC16LF874) + #include + +#elif defined(__SDCC_PIC16LF874A) + #include + +#elif defined(__SDCC_PIC16LF876) + #include + +#elif defined(__SDCC_PIC16LF876A) + #include + +#elif defined(__SDCC_PIC16LF877) + #include + +#elif defined(__SDCC_PIC16LF877A) + #include + +#elif defined(__SDCC_PIC16LF1454) + #include + +#elif defined(__SDCC_PIC16LF1455) + #include + +#elif defined(__SDCC_PIC16LF1458) + #include + +#elif defined(__SDCC_PIC16LF1459) + #include + +#elif defined(__SDCC_PIC16LF1503) + #include + +#elif defined(__SDCC_PIC16LF1507) + #include + +#elif defined(__SDCC_PIC16LF1508) + #include + +#elif defined(__SDCC_PIC16LF1509) + #include + +#elif defined(__SDCC_PIC16LF1512) + #include + +#elif defined(__SDCC_PIC16LF1513) + #include + +#elif defined(__SDCC_PIC16LF1516) + #include + +#elif defined(__SDCC_PIC16LF1517) + #include + +#elif defined(__SDCC_PIC16LF1518) + #include + +#elif defined(__SDCC_PIC16LF1519) + #include + +#elif defined(__SDCC_PIC16LF1526) + #include + +#elif defined(__SDCC_PIC16LF1527) + #include + +#elif defined(__SDCC_PIC16LF1554) + #include + +#elif defined(__SDCC_PIC16LF1559) + #include + +#elif defined(__SDCC_PIC16LF1566) + #include + +#elif defined(__SDCC_PIC16LF1567) + #include + +#elif defined(__SDCC_PIC16LF1574) + #include + +#elif defined(__SDCC_PIC16LF1575) + #include + +#elif defined(__SDCC_PIC16LF1578) + #include + +#elif defined(__SDCC_PIC16LF1579) + #include + +#elif defined(__SDCC_PIC16LF1613) + #include + +#elif defined(__SDCC_PIC16LF1614) + #include + +#elif defined(__SDCC_PIC16LF1615) + #include + +#elif defined(__SDCC_PIC16LF1618) + #include + +#elif defined(__SDCC_PIC16LF1619) + #include + +#elif defined(__SDCC_PIC16LF1703) + #include + +#elif defined(__SDCC_PIC16LF1704) + #include + +#elif defined(__SDCC_PIC16LF1705) + #include + +#elif defined(__SDCC_PIC16LF1707) + #include + +#elif defined(__SDCC_PIC16LF1708) + #include + +#elif defined(__SDCC_PIC16LF1709) + #include + +#elif defined(__SDCC_PIC16LF1713) + #include + +#elif defined(__SDCC_PIC16LF1716) + #include + +#elif defined(__SDCC_PIC16LF1717) + #include + +#elif defined(__SDCC_PIC16LF1718) + #include + +#elif defined(__SDCC_PIC16LF1719) + #include + +#elif defined(__SDCC_PIC16LF1764) + #include + +#elif defined(__SDCC_PIC16LF1765) + #include + +#elif defined(__SDCC_PIC16LF1768) + #include + +#elif defined(__SDCC_PIC16LF1769) + #include + +#elif defined(__SDCC_PIC16LF1773) + #include + +#elif defined(__SDCC_PIC16LF1776) + #include + +#elif defined(__SDCC_PIC16LF1777) + #include + +#elif defined(__SDCC_PIC16LF1778) + #include + +#elif defined(__SDCC_PIC16LF1779) + #include + +#elif defined(__SDCC_PIC16LF1782) + #include + +#elif defined(__SDCC_PIC16LF1783) + #include + +#elif defined(__SDCC_PIC16LF1784) + #include + +#elif defined(__SDCC_PIC16LF1786) + #include + +#elif defined(__SDCC_PIC16LF1787) + #include + +#elif defined(__SDCC_PIC16LF1788) + #include + +#elif defined(__SDCC_PIC16LF1789) + #include + +#elif defined(__SDCC_PIC16LF1823) + #include + +#elif defined(__SDCC_PIC16LF1824) + #include + +#elif defined(__SDCC_PIC16LF1824T39A) + #include + +#elif defined(__SDCC_PIC16LF1825) + #include + +#elif defined(__SDCC_PIC16LF1826) + #include + +#elif defined(__SDCC_PIC16LF1827) + #include + +#elif defined(__SDCC_PIC16LF1828) + #include + +#elif defined(__SDCC_PIC16LF1829) + #include + +#elif defined(__SDCC_PIC16LF1847) + #include + +#elif defined(__SDCC_PIC16LF1902) + #include + +#elif defined(__SDCC_PIC16LF1903) + #include + +#elif defined(__SDCC_PIC16LF1904) + #include + +#elif defined(__SDCC_PIC16LF1906) + #include + +#elif defined(__SDCC_PIC16LF1907) + #include + +#elif defined(__SDCC_PIC16LF1933) + #include + +#elif defined(__SDCC_PIC16LF1934) + #include + +#elif defined(__SDCC_PIC16LF1936) + #include + +#elif defined(__SDCC_PIC16LF1937) + #include + +#elif defined(__SDCC_PIC16LF1938) + #include + +#elif defined(__SDCC_PIC16LF1939) + #include + +#elif defined(__SDCC_PIC16LF1946) + #include + +#elif defined(__SDCC_PIC16LF1947) + #include + +#elif defined(__SDCC_PIC16LF18313) + #include + +#elif defined(__SDCC_PIC16LF18323) + #include + +#elif defined(__SDCC_PIC16LF18324) + #include + +#elif defined(__SDCC_PIC16LF18325) + #include + +#elif defined(__SDCC_PIC16LF18344) + #include + +#elif defined(__SDCC_PIC16LF18345) + #include + +#elif defined(__SDCC_PIC16LF18855) + #include + +#elif defined(__SDCC_PIC16LF18875) + #include + +#else + #error The sdcc is not supported by this processor! +#endif + +#ifndef __CONCAT2 + #define __CONCAT2(a, b) a##b +#endif + +#ifndef __CONCAT + #define __CONCAT(a, b) __CONCAT2(a, b) +#endif + +#define __CONFIG(address, value) \ + static const __code unsigned char __at(address) __CONCAT(_conf, __LINE__) = (value) + +#define Nop() __asm nop __endasm +#define ClrWdt() __asm clrwdt __endasm +#define Sleep() __asm sleep __endasm +#define Reset() __asm reset __endasm + + // To pointer manipulations. (From the sdcc/src/pic14/pcode.h file.) +#define GPTR_TAG_MASK 0x80 // Generated by the device-manager.pl program. +#define GPTR_TAG_DATA 0x00 +#define GPTR_TAG_CODE 0x80 + +#endif // #ifndef __PIC16REGS_H__ +/*------------------------------------------------------------------------- + math.h - Floating point math function declarations + + Copyright (C) 2001, Jesus Calvino-Fraga + Ported to PIC16 port by Vangelis Rokas, 2004 + Adopted for the PIC14 port 2006 by Raphael Neider + + This library is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. + + As a special exception, if you link this library with other files, + some of which are compiled with SDCC, to produce an executable, + this library does not by itself cause the resulting executable to + be covered by the GNU General Public License. This exception does + not however invalidate any other reasons why the executable file + might be covered by the GNU General Public License. +-------------------------------------------------------------------------*/ + +#ifndef __PIC14_MATH_H +#define __PIC14_MATH_H 1 + +#include + +#define PI 3.1415926536 +#define TWO_PI 6.2831853071 +#define HALF_PI 1.5707963268 +#define QUART_PI 0.7853981634 +#define iPI 0.3183098862 +#define iTWO_PI 0.1591549431 +#define TWO_O_PI 0.6366197724 + +// EPS=B**(-t/2), where B is the radix of the floating-point representation +// and there are t base-B digits in the significand. Therefore, for floats +// EPS=2**(-12). Also define EPS2=EPS*EPS. +#define EPS 244.14062E-6 +#define EPS2 59.6046E-9 +#define XMAX 3.402823466E+38 + +union float_long +{ + float f; + long l; +}; + +/********************************************** + * Prototypes for float ANSI C math functions * + **********************************************/ + +/* Trigonometric functions */ +float sinf(float x) _MATH_REENTRANT; +float cosf(float x) _MATH_REENTRANT; +float tanf(float x) _MATH_REENTRANT; +float cotf(float x) _MATH_REENTRANT; +float asinf(float x) _MATH_REENTRANT; +float acosf(float x) _MATH_REENTRANT; +float atanf(float x) _MATH_REENTRANT; +float atan2f(float x, float y); + +/* Hyperbolic functions */ +float sinhf(float x) _MATH_REENTRANT; +float coshf(float x) _MATH_REENTRANT; +float tanhf(float x) _MATH_REENTRANT; + +/* Exponential, logarithmic and power functions */ +float expf(float x); +float logf(float x) _MATH_REENTRANT; +float log10f(float x) _MATH_REENTRANT; +float powf(float x, float y); +float sqrtf(float a) _MATH_REENTRANT; + +/* Nearest integer, absolute value, and remainder functions */ +float fabsf(float x) _MATH_REENTRANT; +float frexpf(float x, int *pw2); +float ldexpf(float x, int pw2); +float ceilf(float x) _MATH_REENTRANT; +float floorf(float x) _MATH_REENTRANT; +float modff(float x, float * y); + +int isnan(float f); +int isinf(float f); +#endif /* __PIC14_MATH_H */ +#-------------------------------------------------------------------------- +# pic14devices.txt - 14 bit 16Fxxx / 16Cxxx / 12Fxxx series device file +# for SDCC +# +# Copyright (C) 2006, Zik Saleeba +# +# This library is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the +# Free Software Foundation; either version 2, or (at your option) any +# later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this library; see the file COPYING. If not, write to the +# Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301, USA. +#-------------------------------------------------------------------------- + +# +# dev = device name +# program = program memory in 14 bit words +# data = data memory in bytes +# eeprom = eeprom storage +# enhanced = 0 | 1 +# 0: regular device (default) +# 1: indicate that this is an enhanced core (automatic context saving on IRQ) +# io = io lines +# maxram = maximum memmap address for unique general purpose registers +# bankmsk = mask for memmap bank selecting. 0x80 for two banks usable, +# 0x180 for four. +# config = white-space separated list of config word addresses +# regmap = registers duplicated in multiple banks. First value is a bank bitmask, +# following values are register addresses +# memmap +# - mirrored in all banks set in +# is a bitmask of bank bits (0x80, 0x100, 0x180) +# Make sure to always provide at least one non-full ( = ) +# record or SDCC will assume that all usable memory is shared across all +# banks! +# +# + +# +# 10F series devices with 14 bit core +# + +processor 10f320, 10lf320 + program 256 + data 64 + eeprom 0 + io 4 + maxram 0x7f + config 0x2007 + + +processor 10f322, 10lf322 + program 512 + data 64 + eeprom 0 + io 4 + maxram 0x7f + config 0x2007 + +# +# 16F series +# +processor 16f72 + program 2K + data 128 + eeprom 0 + io 22 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x06 0x0a 0x0b + regmap 0x100 0x01 0x81 + memmap 0x0020 0x003f 0x100 + memmap 0x0040 0x007f 0x180 + memmap 0x00a0 0x00bf 0x100 + +processor 16f73 + program 4K + data 192 + eeprom 0 + io 22 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x007f 0x100 + memmap 0x00a0 0x00ff 0x100 + +processor 16f74, 16lf74 + program 4K + data 192 + eeprom 0 + io 33 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x007f 0x100 + memmap 0x00a0 0x00ff 0x100 + +processor 16f76, 16lf76 + program 8K + data 368 + eeprom 0 + io 22 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + memmap 0x01a0 0x01ef 0x000 + +processor 16f77, 16lf77 + program 8K + data 368 + eeprom 0 + io 33 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + memmap 0x01a0 0x01ef 0x000 + +processor 16f84, 16lf84, 16f84a, 16lf84a + program 1K + data 68 + eeprom 64 + io 13 + maxram 0xcf + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x000C 0x004f 0x080 + +processor 16f87, 16lf87, 16f88, 16lf88 + program 4K + data 368 + eeprom 256 + io 16 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 0x2008 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f610, 16hv610 + program 1K + data 64 + eeprom 0 + io 11 + maxram 0xff + bankmsk 0x80 + config 0x2007 + regmap 0x080 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0040 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + +processor 16f616, 16hv616 + program 2K + data 128 + eeprom 0 + io 11 + maxram 0xff + bankmsk 0x80 + config 0x2007 + regmap 0x080 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + memmap 0x00a0 0x00bf 0x000 + +processor 16f627, 16lf627, 16f627a, 16lf627a + program 1K + data 224 + eeprom 128 + io 16 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x014f 0x000 + +processor 16f628, 16lf628, 16f628a, 16lf628a + program 2K + data 224 + eeprom 128 + io 16 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x014f 0x000 + +processor 16f648, 16f648a, 16lf648a + program 4K + data 256 + eeprom 256 + io 16 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16f630, 16f676 + program 1K + data 64 + eeprom 128 + io 12 + maxram 0xff + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x005f 0x080 + +processor 16f631 + program 1K + data 64 + eeprom 128 + io 18 + maxram 0xff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x05 0x85 0x07 0x87 + memmap 0x0040 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + +processor 16f636, 16f639 + program 2K + data 128 + eeprom 256 + io 12 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x05 0x85 0x07 0x87 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + +processor 16f677 + program 2K + data 128 + eeprom 256 + io 18 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x05 0x85 0x07 0x87 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + +processor 16f684 + program 2K + data 128 + eeprom 256 + io 12 + maxram 0xff + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + memmap 0x00a0 0x00bf 0x000 + +processor 16f685, 16f689, 16f690 + program 4K + data 256 + eeprom 256 + io 18 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x05 0x85 0x06 0x86 0x07 0x87 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16f687 + program 2K + data 128 + eeprom 256 + io 18 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x05 0x85 0x06 0x86 0x07 0x87 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + +processor 16f688 + program 4K + data 256 + eeprom 256 + io 12 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x05 0x85 0x07 0x87 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16f716 + program 2K + data 128 + eeprom 0 + io 13 + maxram 0xff + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + memmap 0x00a0 0x00bf 0x000 + +processor 16f707,16lf707 + program 8K + data 363 + eeprom 0 + io 36 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0115 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f720,16lf720 + program 2K + data 128 + eeprom 0 + io 18 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 0x2008 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + +processor 16f721,16lf721 + program 4K + data 256 + eeprom 0 + io 18 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 0x2008 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + +processor 16f722,16lf722,16f722a,16lf722a + program 2K + data 128 + eeprom 0 + io 25 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 0x2008 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + +processor 16f723,16lf723,16f723a,16lf723a + program 4K + data 192 + eeprom 0 + io 25 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 0x2008 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x012f 0x000 + +processor 16f724,16lf724 + program 4K + data 192 + eeprom 0 + io 36 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 0x2008 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x012f 0x000 + +processor 16f726,16lf726 + program 8K + data 368 + eeprom 0 + io 25 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 0x2008 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f727,16lf727 + program 8K + data 368 + eeprom 0 + io 36 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 0x2008 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f737 + program 4K + data 368 + eeprom 0 + io 25 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 0x2008 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f747, 16lf747 + program 4K + data 368 + eeprom 0 + io 36 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 0x2008 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f767, 16lf767 + program 8K + data 368 + eeprom 0 + io 25 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 0x2008 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f777, 16lf777 + program 8K + data 368 + eeprom 0 + io 36 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 0x2008 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f753, 16hv753 + program 2K + data 128 + eeprom 0 + io 12 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + +processor 16f785, 16hv785 + program 2K + data 128 + eeprom 256 + io 18 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x05 0x85 0x06 0x86 0x07 0x87 0x8c + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + +processor 16f870, 16lf870, 16f872, 16lf872 + program 2K + data 128 + eeprom 64 + io 22 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x100 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x100 + +processor 16f871, 16lf871 + program 2K + data 128 + eeprom 64 + io 33 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x100 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x100 + +processor 16f873, 16lf873, 16f873a, 16lf873a + program 4K + data 192 + eeprom 128 + io 22 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x007f 0x100 + memmap 0x00a0 0x00ff 0x100 + +processor 16f874, 16lf874, 16f874a, 16lf874a + program 4K + data 192 + eeprom 128 + io 33 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x007f 0x100 + memmap 0x00a0 0x00ff 0x100 + +processor 16f876, 16lf876, 16f876a, 16lf876a + program 8K + data 368 + eeprom 256 + io 22 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f877, 16lf877, 16f877a, 16lf877a + program 8K + data 368 + eeprom 256 + io 22 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f882 + program 2K + data 128 + eeprom 128 + io 24 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 0x2008 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + +processor 16f883 + program 4K + data 256 + eeprom 256 + io 24 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 0x2008 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16f884 + program 4K + data 256 + eeprom 256 + io 35 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 0x2008 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16f886 + program 8K + data 368 + eeprom 256 + io 24 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 0x2008 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f887 + program 8K + data 368 + eeprom 256 + io 35 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 0x2008 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f818, 16lf818 + program 1K + data 128 + eeprom 128 + io 16 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x003f 0x100 + memmap 0x0040 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + +processor 16f819, 16lf819 + program 2K + data 256 + eeprom 256 + io 16 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16f913 + program 4K + data 256 + eeprom 256 + io 24 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16f914 + program 4K + data 256 + eeprom 256 + io 35 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16f916 + program 8K + data 352 + eeprom 256 + io 24 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f917 + program 8K + data 352 + eeprom 256 + io 35 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f946 + program 8K + data 336 + eeprom 256 + io 53 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + memmap 0x01a0 0x01ef 0x000 + + +# +# 16c series +# +processor 16c62, 16c72 + program 2K + data 128 + eeprom 0 + io 22 + maxram 0xbf + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x007f 0x000 + memmap 0x00a0 0x00bf 0x000 + +processor 16c63a, 16c73b + program 4K + data 192 + eeprom 0 + io 22 + maxram 0xff + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x007f 0x000 + memmap 0x00a0 0x00ff 0x000 + +processor 16c65b, 16c74b + program 4K + data 192 + eeprom 0 + io 33 + maxram 0xff + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x007f 0x000 + memmap 0x00a0 0x00ff 0x000 + +processor 16cr73 + program 4K + data 192 + eeprom 0 + io 22 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 + memmap 0x0020 0x007f 0x000 + memmap 0x00a0 0x00ff 0x000 + +processor 16cr74 + program 4K + data 192 + eeprom 0 + io 33 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 + memmap 0x0020 0x007f 0x000 + memmap 0x00a0 0x00ff 0x000 + +processor 16cr76 + program 8K + data 368 + eeprom 0 + io 22 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x180 0x01 0x81 + memmap 0x0020 0x006f 0x000 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + memmap 0x0070 0x007f 0x180 + +processor 16cr77 + program 8K + data 368 + eeprom 0 + io 33 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x180 0x01 0x81 + memmap 0x0020 0x006f 0x000 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + memmap 0x0070 0x007f 0x180 + +processor 16c432 + program 2K + data 128 + eeprom 0 + io 12 + maxram 0xff + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + memmap 0x00a0 0x00bf 0x000 + +processor 16c433 + program 2K + data 128 + eeprom 0 + io 6 + maxram 0xff + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + memmap 0x00a0 0x00bf 0x000 + +processor 16c554 + program 512 + data 80 + eeprom 0 + io 21 + maxram 0x6f + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + +processor 16c557, 16c558 + program 2K + data 128 + eeprom 0 + io 21 + maxram 0xbf + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x007f 0x000 + memmap 0x00a0 0x00bf 0x000 + +processor 16c620 + program 512 + data 80 + eeprom 0 + io 13 + maxram 0x9f + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + +processor 16c620a, 16cr620a + program 512 + data 96 + eeprom 0 + io 13 + maxram 0xff + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + +processor 16c621 + program 1K + data 80 + eeprom 0 + io 13 + maxram 0x9f + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + +processor 16c621a + program 1K + data 96 + eeprom 0 + io 13 + maxram 0xff + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + +processor 16c622 + program 2K + data 128 + eeprom 0 + io 13 + maxram 0xbf + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x007f 0x000 + memmap 0x00a0 0x00bf 0x000 + +processor 16c622a + program 2K + data 128 + eeprom 0 + io 13 + maxram 0xff + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + memmap 0x00a0 0x00bf 0x000 + + +processor 16c710 + program 512 + data 36 + eeprom 0 + io 13 + maxram 0xaf + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x09 0x0a 0x0b + memmap 0x000c 0x002f 0x080 + +processor 16c71 + program 1K + data 36 + eeprom 0 + io 13 + maxram 0xaf + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x09 0x0a 0x0b + memmap 0x000c 0x002f 0x080 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0x0120 0x016f 0x000 + +processor 16c745 + program 8K + data 320 + eeprom 0 + io 22 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + memmap 0x01a0 0x01df 0x000 + +processor 16c765 + program 8K + data 320 + eeprom 0 + io 33 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + memmap 0x01a0 0x01df 0x000 + +processor 16c773 + program 4K + data 256 + eeprom 0 + io 21 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16c774 + program 4K + data 256 + eeprom 0 + io 32 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16c781 + program 1K + data 128 + eeprom 0 + io 16 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + +processor 16c782 + program 2K + data 128 + eeprom 0 + io 16 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + +processor 16c925 + program 4K + data 176 + eeprom 0 + io 52 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + +processor 16c926 + program 8K + data 336 + eeprom 0 + io 52 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + memmap 0x0120 0x016f 0x000 + memmap 0x01a0 0x01bf 0x000 + +# +# 12F series devices with 14 bit core +# +processor 12f609, 12f615, 12hv609, 12hv615 + program 1K + data 64 + eeprom 0 + io 5 + maxram 0xff + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0040 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + +processor 12f617 + program 2K + data 128 + eeprom 0 + io 5 + maxram 0xff + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + memmap 0x00a0 0x00bf 0x000 + +processor 12f629, 12f675 + program 1K + data 64 + eeprom 128 + io 6 + maxram 0xff + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x005f 0x080 + +processor 12f635 + program 1K + data 64 + eeprom 128 + io 6 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x05 0x85 + memmap 0x0040 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + +processor 12f683 + program 2K + data 128 + eeprom 256 + io 6 + maxram 0xff + bankmsk 0x80 + config 0x2007 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + memmap 0x00a0 0x00bf 0x000 + +processor 12f752 + program 1K + data 64 + eeprom 0 + io 6 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0040 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + +processor 12hv752 + program 1K + data 64 + eeprom 0 + io 6 + maxram 0x1ff + bankmsk 0x180 + config 0x2007 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0040 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + +# +# Enhanced instruction set 14-bit devices +# + +processor 16f1454, 16lf1454 + program 8K + data 1024 + eeprom 0 + io 11 + enhanced 1 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1455, 16lf1455 + program 8K + data 1024 + eeprom 0 + io 11 + enhanced 1 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1458, 16lf1458 + program 4K + data 512 + eeprom 0 + io 18 + enhanced 1 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1459, 16lf1459 + program 8K + data 1024 + eeprom 0 + io 17 + enhanced 1 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 12f1501, 12lf1501 + program 1K + data 64 + eeprom 0 + enhanced 1 + io 6 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x4f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 12f1571 12lf1571 + program 1K + data 128 + eeprom 0 + enhanced 1 + io 6 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 12f1572 12lf1572 + program 2K + data 256 + eeprom 0 + enhanced 1 + io 6 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 12f1612 12lf1612 + program 2K + data 256 + eeprom 0 + enhanced 1 + io 6 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 0x8009 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1503, 16lf1503 + program 2K + data 128 + eeprom 0 + enhanced 1 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1507, 16lf1507 + program 2K + data 128 + eeprom 0 + enhanced 1 + io 18 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1508, 16lf1508 + program 4K + data 256 + eeprom 0 + enhanced 1 + io 18 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1509, 16lf1509 + program 8K + data 512 + eeprom 0 + enhanced 1 + io 18 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1512, 16lf1512 + program 2K + data 128 + eeprom 0 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1513, 16lf1513 + program 4K + data 256 + eeprom 0 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1516, 16lf1516 + program 8K + data 512 + eeprom 0 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1517, 16lf1517 + program 8K + data 512 + eeprom 0 + enhanced 1 + io 36 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1518, 16lf1518 + program 16K + data 1024 + eeprom 0 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1519, 16lf1519 + program 16K + data 1024 + eeprom 0 + enhanced 1 + io 36 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1526, 16lf1526 + program 8K + data 768 + eeprom 0 + enhanced 1 + io 55 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1527, 16lf1527 + program 16K + data 1536 + eeprom 0 + enhanced 1 + io 55 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 12lf1552 + program 2K + data 1536 + eeprom 0 + enhanced 1 + io 6 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16lf1554 + program 4K + data 256 + eeprom 0 + enhanced 1 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16lf1559 + program 8K + data 512 + eeprom 0 + enhanced 1 + io 18 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16lf1566 + program 8K + data 1024 + eeprom 0 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16lf1567 + program 8K + data 1024 + eeprom 0 + enhanced 1 + io 36 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1574, 16lf1574 + program 4K + data 512 + eeprom 0 + enhanced 1 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1575, 16lf1575 + program 8K + data 1024 + eeprom 0 + enhanced 1 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1578, 16lf1578 + program 4K + data 512 + eeprom 0 + enhanced 1 + io 18 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1579, 16lf1579 + program 8K + data 1024 + eeprom 0 + enhanced 1 + io 18 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1613 16lf1613 + program 2K + data 256 + eeprom 0 + enhanced 1 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 0x8009 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1614, 16lf1614 + program 4K + data 512 + eeprom 0 + enhanced 1 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 0x8009 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1615, 16lf1615 + program 8K + data 1024 + eeprom 0 + enhanced 1 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 0x8009 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1618, 16lf1618 + program 4K + data 512 + eeprom 0 + enhanced 1 + io 18 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 0x8009 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1619, 16lf1619 + program 8K + data 1024 + eeprom 0 + enhanced 1 + io 18 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 0x8009 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1703 16lf1703 + program 2K + data 256 + eeprom 0 + enhanced 1 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1704, 16lf1704 + program 4K + data 512 + eeprom 0 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1705 16lf1705 + program 8K + data 1024 + eeprom 0 + enhanced 1 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1707 16lf1707 + program 2K + data 256 + eeprom 0 + enhanced 1 + io 18 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1708, 16lf1708 + program 4K + data 512 + eeprom 0 + io 18 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1709, 16lf1709 + program 8K + data 1024 + eeprom 0 + enhanced 1 + io 18 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1713, 16lf1713 + program 4K + data 512 + eeprom 0 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1716, 16lf1716 + program 8K + data 1024 + eeprom 0 + enhanced 1 + io 17 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1717, 16lf1717 + program 8K + data 1024 + eeprom 0 + enhanced 1 + io 36 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1718, 16lf1718 + program 16K + data 2048 + eeprom 0 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1719, 16lf1719 + program 16K + data 2048 + eeprom 0 + enhanced 1 + io 36 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1764, 16lf1764 + program 4K + data 512 + eeprom 0 + enhanced 1 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1765, 16lf1765 + program 8K + data 1024 + eeprom 0 + enhanced 1 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1768, 16lf1768 + program 4K + data 512 + eeprom 0 + enhanced 1 + io 18 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1769, 16lf1769 + program 8K + data 1024 + eeprom 0 + enhanced 1 + io 18 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1773, 16lf1773 + program 4K + data 512 + eeprom 0 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1776, 16lf1776 + program 8K + data 1024 + eeprom 0 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1777, 16lf1777 + program 8K + data 1024 + eeprom 0 + enhanced 1 + io 36 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1778, 16lf1778 + program 16K + data 2048 + eeprom 0 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1779, 16lf1779 + program 16K + data 2048 + eeprom 0 + enhanced 1 + io 36 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1782, 16lf1782 + program 2K + data 256 + eeprom 256 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1783, 16lf1783 + program 4K + data 512 + eeprom 256 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1784, 16lf1784 + program 4K + data 512 + eeprom 256 + enhanced 1 + io 36 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1786, 16lf1786 + program 8K + data 1024 + eeprom 256 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1787, 16lf1787 + program 8K + data 1024 + eeprom 256 + enhanced 1 + io 36 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1788, 16lf1788 + program 16K + data 2048 + eeprom 256 + enhanced 1 + io 25 + maxram 0xfff + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1789, 16lf1789 + program 16K + data 2048 + eeprom 256 + enhanced 1 + io 36 + maxram 0xfff + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +# PICxxF182x family +processor 12f1822, 12lf1822 + program 2K + data 128 + eeprom 256 + enhanced 1 + io 6 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1823, 16lf1823 + program 2K + data 128 + eeprom 256 + enhanced 1 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1824, 16lf1824 + program 4K + data 256 + eeprom 256 + enhanced 1 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16lf1824t39a + program 4K + data 256 + eeprom 256 + enhanced 1 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1825, 16lf1825 + program 8K + data 1024 + eeprom 256 + enhanced 1 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1826, 16lf1826 + program 2K + data 256 + eeprom 256 + enhanced 1 + io 16 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1827, 16lf1827 + program 4K + data 384 + eeprom 256 + enhanced 1 + io 16 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1828, 16lf1828 + program 4K + data 256 + eeprom 256 + enhanced 1 + io 18 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1829, 16lf1829 + program 8K + data 1024 + eeprom 256 + enhanced 1 + io 18 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1829lin + program 8K + data 1024 + eeprom 256 + enhanced 1 + io 13 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +# PICxxF184x family +processor 12f1840, 12lf1840 + program 4K + data 256 + eeprom 256 + enhanced 1 + io 6 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 12lf1840t39a + program 4K + data 256 + eeprom 256 + enhanced 1 + io 6 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 12lf1840t48a + program 4K + data 256 + eeprom 256 + enhanced 1 + io 6 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1847, 16lf1847 + program 8K + data 1024 + eeprom 256 + enhanced 1 + io 16 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +# PIC16LF190x family +processor 16lf1902 + program 2K + data 128 + eeprom 0 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16lf1903 + program 4K + data 256 + eeprom 0 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16lf1904 + program 4K + data 256 + eeprom 0 + enhanced 1 + io 36 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16lf1906 + program 8K + data 512 + eeprom 0 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16lf1907 + program 8K + data 512 + eeprom 0 + enhanced 1 + io 36 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +# PIC16F193x family +processor 16f1933, 16lf1933 + program 4K + data 256 + eeprom 256 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1934, 16lf1934 + program 4K + data 256 + eeprom 256 + enhanced 1 + io 36 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1936, 16lf1936 + program 8K + data 512 + eeprom 256 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1937, 16lf1937 + program 8K + data 512 + eeprom 256 + enhanced 1 + io 36 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1938, 16lf1938 + program 16K + data 1024 + eeprom 256 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1939, 16lf1939 + program 16K + data 1024 + eeprom 256 + enhanced 1 + io 36 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1946, 16lf1946 + program 8K + data 512 + eeprom 256 + enhanced 1 + io 53 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f1947, 16lf1947 + program 16K + data 1024 + eeprom 256 + enhanced 1 + io 53 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f18313, 16lf18313 + program 2K + data 256 + eeprom 256 + enhanced 1 + io 6 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 0x8009 0x800a + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f18323, 16lf18323 + program 2K + data 256 + eeprom 256 + enhanced 1 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 0x8009 0x800a + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f18324, 16lf18324 + program 4K + data 512 + eeprom 256 + enhanced 1 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 0x8009 0x800a + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f18325, 16lf18325 + program 8K + data 1024 + eeprom 256 + enhanced 1 + io 12 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 0x8009 0x800a + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f18344, 16lf18344 + program 4K + data 512 + eeprom 256 + enhanced 1 + io 18 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 0x8009 0x800a + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f18345, 16lf18345 + program 8K + data 1024 + eeprom 256 + enhanced 1 + io 18 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 0x8009 0x800a + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f18855, 16lf18855 + program 8K + data 1024 + eeprom 256 + enhanced 1 + io 25 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 0x8009 0x800a 0x800b + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 + +processor 16f18875, 16lf18875 + program 8K + data 1024 + eeprom 256 + enhanced 1 + io 36 + maxram 0x07f + bankmsk 0xf80 + config 0x8007 0x8008 0x8009 0x800a 0x800b + regmap 0xf80 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b + memmap 0x20 0x6f 0x000 + memmap 0x70 0x7f 0xf80 /*------------------------------------------------------------------------- ds400rom.h - Interface to DS80C400 ROM functions @@ -33455,9 +48138,9 @@ extern void task_settickreload(unsigned); #endif ! -/ 1458795436 0 0 0 3024 ` -à è è è è è>>>>>>>ÚÚÚ–––&&&ìììääääöööö ` ` `""""#º#º$Þ$Þ%ì%ì&Ø&Ø'®'®(†(†)x)x)x+¾+¾<|<|>æ>æATATDðDðGPGPI¦PœPœT®T®XÄXÄ]¢]¢`¢`¢c¤iÊ„š™¬°ð³Ð¸úÀŠÈÍDÐ:ÔÊÛ&Û&ôdôdútút‚‚˜˜ÊÊ(‚(‚+b+b6Æ6ÆP€P€SSXXqqv6v6{‚{‚ŽJŽJšÂšÂ­æ°j²ð²ðÀäÀäNJNJͮͮÑDÓ ÙÞ”ähèÖèÖòÌþ’þ’¨ââø v v#¶&Ü)t,Œ/h3869†9†= -AŠDfIäLVNÈU^Š^Š_vbdbdgšj–n‚qÂu&zP*‚…¶‰´Ž‘€—ÖŸ"£V§Ò«P® ® ±x±xºÎºÎÅlÅlÅlË â âüüüüüüüüüIÎIÎIÎRRZ<\6\6\6a a a .__.ABS.__divuint__divuchar__divu16__divu8.__.ABS.__div_signexte__divschar__get_remainder__div16__div8__divsint.__.ABS.__divuschar__divsuchar.__.ABS.__moduchar__moduint.__.ABS.__modschar__modsint.__.ABS.__moduschar__modsuchar.__.ABS.__mulint__mul16.__.ABS.__muluschar__mulsuchar__mulschar.__.ABS._putchar_putchar_rr_s_putchar_rr_dbs.__.ABS.__sdcc_heap_start__sdcc_heap_end.__.ABS._memmove.__.ABS._strcpy.__.ABS._strlen.__.ABS._abs.__.ABS.___sdcc_call_hl.__.ABS.___sdcc_call_iy.__.ABS.___sdcc_enter_ix.__.ABS._longjmp___setjmp.__.ABS._atof.__.ABS.___schar2fs.__.ABS.___sint2fs.__.ABS.___slong2fs.__.ABS.___uchar2fs.__.ABS.___uint2fs___ulong2fs.__.ABS.___fs2schar.__.ABS.___fs2sint.__.ABS.___fs2slong.__.ABS.___fs2uchar.__.ABS.___fs2uint___fs2ulong___fsadd___fsdiv___fsmul___fssub___fseq___fsgt___fslt___fsneq_fabsf_frexpf_ldexpf.__.ABS._expf.__.ABS._powf.__.ABS._sincosf.__.ABS._sinf.__.ABS._cosf.__.ABS._logf.__.ABS._log10f.__.ABS._sqrtf.__.ABS._tancotf.__.ABS._tanf.__.ABS._cotf.__.ABS._asincosf.__.ABS._asinf.__.ABS._acosf.__.ABS._atanf.__.ABS._atan2f.__.ABS._sincoshf_sinhf_coshf.__.ABS._tanhf.__.ABS._floorf.__.ABS._ceilf.__.ABS._modff_errno__divslong__modslong__modulong__divulong.__.ABS.__mullong__mullonglong.__.ABS.__divslonglong__divulonglong.__.ABS.__modslonglong__modulonglong.__.ABS._isalnum_isalpha_isblank_iscntrl_isdigit_isgraph_islower_isprint.__.ABS._ispunct_isspace_isupper_isxdigit_tolower_toupper_atoi_atol.__.ABS._abs_labs_rand_srand_strcat_strchr_strcmp_strcspn_strncat_strncmp_strxfrm_strncpy_strpbrk_strrchr_strspn_strstr_strtok_memchr_memcmp_memcpy_memset.__.ABS._calloc_malloc__sdcc_heap_init.__.ABS._realloc_free__sdcc_find_memheader__sdcc_prev_memheader__print_format.__.ABS._puts.__.ABS._gets__assert_RtcRead_asctime_time_localtime_gmtime_mktime_ctime___month___day.__.ABS.__uitoa__itoa__ultoa__ltoa__sdcc_external_startup.__.ABS._vsprintf_sprintf.__.ABS._vprintf_printf// 152 ` +/ 0 0 0 0 3242 ` +ô Ö Ö Ö Ö Ö,,,,,,,ÈÈÈ„„„ÚÚÚðððÌÌÌÌÞÞÞ!ž!ž#6#6$Z$Z%h%h&T&T'*'*(((ô(ô(ô+:+:=`=`?Ê?ÊB8B8EÔEÔH(H(JzQjQjU|U|Y’Y’^p^papapdrjX‚Æ‚Æœ°j³J¸tÀǔ̾ϴÔJÚ,Ú,ó¢ó¢ù²ù²ÀÀÖÖ'Â'Â*¢*¢66OÀOÀR@R@WHWHp8p8ululz¸z¸€€™ü™ü­ ¯¤²*²*ÀÀÆÄÆÄÌèÌèÐ~ÒZÕÒØ>Þã²éVí¾í¾÷ÖŠŠ ’ÀÀÈ%%(4+H-Ú0ì3¶7€:J=¶=¶A4E®HxMðPbRÔXÀbbc|fjfjløoôsÔw|F€¶ƒ ‡B‹:Ä“ +™2 j¤È©­”­”± ± ± ± º®º®ÎXÕ,ÚNäíròføòøòØ > >v ØŽ!d$p$p'â'â9î<‚¤¤‚Š‚Šˆ’Œ<Œ<Œ<Œ<Œ<Œ<Œ<Œ<Œ<»0»0»0Ã"Ã"ËNÍHÍHÍHÒ,Ò,Ò,ÖÙH.__.ABS.__divuint__divuchar__divu16__divu8.__.ABS.__div_signexte__divschar__get_remainder__div16__div8__divsint.__.ABS.__divuschar__divsuchar.__.ABS.__moduchar__moduint.__.ABS.__modschar__modsint.__.ABS.__moduschar__modsuchar.__.ABS.__mulint__mul16.__.ABS.__muluschar__mulsuchar__mulschar.__.ABS.___sdcc_heap___sdcc_heap_end.__.ABS._memmove.__.ABS._strcpy.__.ABS._strlen.__.ABS._abs.__.ABS.___sdcc_call_hl.__.ABS.___sdcc_call_iy.__.ABS.___sdcc_enter_ix.__.ABS._longjmp___setjmp.__.ABS._atof.__.ABS.___schar2fs.__.ABS.___sint2fs.__.ABS.___slong2fs.__.ABS.___uchar2fs.__.ABS.___uint2fs___ulong2fs.__.ABS.___fs2schar.__.ABS.___fs2sint.__.ABS.___fs2slong.__.ABS.___fs2uchar.__.ABS.___fs2uint___fs2ulong___fsadd.__.ABS.___fsdiv___fsmul___fssub___fseq___fsgt___fslt___fsneq_fabsf_frexpf_ldexpf.__.ABS._expf.__.ABS._powf.__.ABS._sincosf.__.ABS._sinf.__.ABS._cosf.__.ABS._logf.__.ABS._log10f.__.ABS._sqrtf.__.ABS._tancotf.__.ABS._tanf.__.ABS._cotf.__.ABS._asincosf.__.ABS._asinf.__.ABS._acosf.__.ABS._atanf.__.ABS._atan2f.__.ABS._sincoshf_sinhf_coshf.__.ABS._tanhf.__.ABS._floorf.__.ABS._ceilf.__.ABS._modff_errno_isinf_isnan__divslong__modslong__modulong__divulong.__.ABS.__mullong__mullonglong.__.ABS.__divslonglong__divulonglong.__.ABS.__modslonglong__modulonglong.__.ABS._isalnum_isalpha_isblank_iscntrl_isdigit_isgraph_islower_isprint.__.ABS._ispunct_isspace_isupper_isxdigit_tolower_toupper_atoi_atol.__.ABS._abs_labs_rand_srand_strcat_strchr_strcspn_strncat_strncmp_strxfrm_strncpy_strpbrk_strrchr_strspn_strstr_strtok_memchr_memcmp_memset.__.ABS._calloc.__.ABS.___sdcc_heap_init_malloc___sdcc_heap_free.__.ABS._realloc_free_mblen_mbtowc_wctomb_mbstowcs_wcstombs.__.ABS._mbrtoc16_c16rtomb.__.ABS._mbrtoc32_c32rtomb_wcscmp_wcslen_btowc_wctob_mbsinit.__.ABS._mbrlen.__.ABS._mbrtowc_wcrtomb__print_format.__.ABS._puts.__.ABS._gets__assert_RtcRead_asctime_time_localtime_gmtime_mktime_ctime___month___day.__.ABS.__uitoa__itoa__ultoa__ltoa__sdcc_external_startup.__.ABS._vsprintf_sprintf.__.ABS._vprintf_printf_strcmp_memcpy// 172 ` __sdcc_call_hl.rel/ __sdcc_call_iy.rel/ _mullonglong.rel/ @@ -33465,8 +48148,10 @@ _divslonglong.rel/ _divulonglong.rel/ _modslonglong.rel/ _modulonglong.rel/ +aligned_alloc.rel/ printf_large.rel/ -divunsigned.rel/1458795406 2001 2501 100664 794 ` + +divunsigned.rel/0 0 0 644 794 ` XL2 H 1 areas 5 global symbols S .__.ABS. Def0000 @@ -33515,7 +48200,7 @@ T 37 00 R 00 00 00 00 T 37 00 3F 17 10 F5 CB 10 50 5F EB C9 R 00 00 00 00 -divsigned.rel/ 1458795406 2001 2501 100664 863 ` +divsigned.rel/ 0 0 0 644 863 ` XL2 H 1 areas 8 global symbols S __divu16 Ref0000 @@ -33564,7 +48249,7 @@ R 00 00 00 00 T 3E 00 17 EB D0 97 95 6F 9F 94 67 C9 R 00 00 00 00 -divmixed.rel/ 1458795406 2001 2501 100664 383 ` +divmixed.rel/ 0 0 0 644 383 ` XL2 H 1 areas 5 global symbols S __div_signexte Ref0000 @@ -33584,7 +48269,7 @@ R 00 00 00 00 T 19 00 00 00 R 00 00 00 00 02 02 02 00 -modunsigned.rel/1458795406 2001 2501 100664 340 ` +modunsigned.rel/0 0 0 644 340 ` XL2 H 1 areas 5 global symbols S __divu16 Ref0000 @@ -33601,7 +48286,7 @@ T 0C 00 R 00 00 00 00 T 0C 00 F1 E1 D1 D5 E5 F5 CD 00 00 EB C9 R 00 00 00 00 02 09 00 00 -modsigned.rel/ 1458795406 2001 2501 100664 394 ` +modsigned.rel/ 0 0 0 644 394 ` XL2 H 1 areas 6 global symbols S __get_remainder Ref0000 @@ -33619,7 +48304,7 @@ T 0D 00 R 00 00 00 00 T 0D 00 F1 E1 D1 D5 E5 F5 CD 00 00 C3 00 00 R 00 00 00 00 02 09 02 00 02 0C 00 00 -modmixed.rel/ 1458795406 2001 2501 100664 473 ` +modmixed.rel/ 0 0 0 644 473 ` XL2 H 1 areas 6 global symbols S __div_signexte Ref0000 @@ -33642,34 +48327,34 @@ R 00 00 00 00 T 1C 00 00 00 C3 00 00 R 00 00 00 00 02 02 03 00 02 05 01 00 -mul.rel/ 1458795406 2001 2501 100664 422 ` +mul.rel/ 0 0 0 644 416 ` XL2 H 1 areas 3 global symbols S .__.ABS. Def0000 -A _CODE size 1C flags 0 addr 0 +A _CODE size 1A flags 0 addr 0 S __mulint Def0000 -S __mul16 Def0008 +S __mul16 Def0006 T 00 00 R 00 00 00 00 -T 00 00 F1 E1 D1 D5 E5 F5 44 4D +T 00 00 F1 C1 D1 D5 C5 F5 R 00 00 00 00 -T 08 00 +T 06 00 R 00 00 00 00 -T 08 00 AF 6F B0 06 10 20 04 06 08 79 +T 06 00 AF 6F B0 06 10 20 04 06 08 79 R 00 00 00 00 -T 12 00 +T 10 00 R 00 00 00 00 -T 12 00 29 +T 10 00 29 R 00 00 00 00 -T 13 00 +T 11 00 R 00 00 00 00 -T 13 00 CB 11 17 30 01 19 +T 11 00 CB 11 17 30 01 19 R 00 00 00 00 -T 19 00 +T 17 00 R 00 00 00 00 -T 19 00 10 F7 C9 +T 17 00 10 F7 C9 R 00 00 00 00 -mulchar.rel/ 1458795406 2001 2501 100664 469 ` +mulchar.rel/ 0 0 0 644 469 ` XL2 H 1 areas 5 global symbols S .__.ABS. Def0000 @@ -33695,38 +48380,19 @@ R 00 00 00 00 T 20 00 7B 17 9F 57 C3 00 00 R 00 00 00 00 02 07 01 00 -putchar.rel/ 1458795406 2001 2501 100664 301 ` -XL2 -H 1 areas 4 global symbols -S .__.ABS. Def0000 -A _CODE size E flags 0 addr 0 -S _putchar Def0000 -S _putchar_rr_s Def0000 -S _putchar_rr_dbs Def0009 -T 00 00 -R 00 00 00 00 -T 00 00 -R 00 00 00 00 -T 00 00 21 02 00 39 6E 3E 01 CF C9 -R 00 00 00 00 -T 09 00 -R 00 00 00 00 -T 09 00 6B 3E 01 CF C9 -R 00 00 00 00 - -heap.rel/ 1458795406 2001 2501 100664 390 ` +heap.rel/ 0 0 0 644 387 ` XL2 H 4 areas 4 global symbols +S ___sdcc_heap_init Ref0000 S .__.ABS. Def0000 -S __sdcc_heap_init Ref0000 A _CODE size 0 flags 0 addr 0 A _GSINIT size 3 flags 0 addr 0 A _HEAP size 3FF flags 0 addr 0 -S __sdcc_heap_start Def0000 +S ___sdcc_heap Def0000 A _HEAP_END size 1 flags 0 addr 0 -S __sdcc_heap_end Def0000 +S ___sdcc_heap_end Def0000 T 00 00 CD 00 00 -R 00 00 01 00 02 03 01 00 +R 00 00 01 00 02 03 00 00 T 00 00 R 00 00 02 00 T 00 00 @@ -33735,7 +48401,8 @@ T 00 00 R 00 00 03 00 T 00 00 R 00 00 03 00 -memmove.rel/ 1458795406 2001 2501 100664 347 ` + +memmove.rel/ 0 0 0 644 347 ` XL2 H 1 areas 2 global symbols S .__.ABS. Def0000 @@ -33756,7 +48423,7 @@ R 00 00 00 00 T 1A 00 EB ED B0 E1 C9 R 00 00 00 00 -strcpy.rel/ 1458795406 2001 2501 100664 231 ` +strcpy.rel/ 0 0 0 644 231 ` XL2 H 1 areas 2 global symbols S .__.ABS. Def0000 @@ -33771,7 +48438,7 @@ R 00 00 00 00 T 08 00 BE ED A0 20 FB E1 C9 R 00 00 00 00 -strlen.rel/ 1458795406 2001 2501 100664 209 ` +strlen.rel/ 0 0 0 644 209 ` XL2 H 1 areas 2 global symbols S .__.ABS. Def0000 @@ -33784,7 +48451,7 @@ R 00 00 00 00 T 0E 00 C9 R 00 00 00 00 -abs.rel/ 1458795406 2001 2501 100664 175 ` +abs.rel/ 0 0 0 644 175 ` XL2 H 1 areas 2 global symbols S .__.ABS. Def0000 @@ -33795,7 +48462,7 @@ R 00 00 00 00 T 00 00 E1 D1 D5 E5 AF 6F 67 ED 52 F0 EB C9 R 00 00 00 00 -/0 1458795406 2001 2501 100664 153 ` +/0 0 0 0 644 153 ` XL2 H 1 areas 2 global symbols S .__.ABS. Def0000 @@ -33806,7 +48473,7 @@ R 00 00 00 00 T 00 00 E9 R 00 00 00 00 -/20 1458795406 2001 2501 100664 156 ` +/20 0 0 0 644 156 ` XL2 H 1 areas 2 global symbols S .__.ABS. Def0000 @@ -33816,7 +48483,7 @@ T 00 00 R 00 00 00 00 T 00 00 FD E9 R 00 00 00 00 -crtenter.rel/ 1458795406 2001 2501 100664 181 ` +crtenter.rel/ 0 0 0 644 181 ` XL2 H 1 areas 2 global symbols S .__.ABS. Def0000 @@ -33827,7 +48494,7 @@ R 00 00 00 00 T 00 00 E1 DD E5 DD 21 00 00 DD 39 E9 R 00 00 00 00 -setjmp.rel/ 1458795406 2001 2501 100664 522 ` +setjmp.rel/ 0 0 0 644 522 ` XL2 H 1 areas 3 global symbols S .__.ABS. Def0000 @@ -33852,20 +48519,19 @@ T 2A 00 FD 6E 04 FD 66 05 E5 DD E1 FD 6E 02 FD 66 R 00 00 00 00 T 38 00 03 F9 E1 EB FD 4E 00 FD 46 01 C5 C9 R 00 00 00 00 -_atof.rel/ 1458795407 2001 2501 100664 4226 ` +_atof.rel/ 0 0 0 644 4586 ` XL2 -H 9 areas 9 global symbols +H 9 areas 8 global symbols M _atof O -mz80 S ___fsmul Ref0000 S _isspace Ref0000 -S _isdigit Ref0000 S _atoi Ref0000 S .__.ABS. Def0000 S ___fsadd Ref0000 S ___sint2fs Ref0000 S _toupper Ref0000 -A _CODE size 299 flags 0 addr 0 +A _CODE size 2E8 flags 0 addr 0 S _atof Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -33877,139 +48543,153 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 DD E5 DD 21 00 00 DD 39 21 F0 FF 39 F9 DD +T 00 00 DD E5 DD 21 00 00 DD 39 21 ED FF 39 F9 DD R 00 00 00 00 T 0E 00 4E 04 DD 46 05 R 00 00 00 00 T 13 00 R 00 00 00 00 -T 13 00 0A 6F 17 9F 67 C5 E5 CD 00 00 F1 C1 59 50 -R 00 00 00 00 02 0A 01 00 -T 21 00 13 7C B5 28 04 4B 42 18 E9 +T 13 00 0A 5F 16 00 C5 D5 CD 00 00 F1 C1 59 50 13 +R 00 00 00 00 02 09 01 00 +T 21 00 7C B5 28 04 4B 42 18 EA R 00 00 00 00 -T 2A 00 +T 29 00 R 00 00 00 00 -T 2A 00 DD 71 04 DD 70 05 0A 67 D6 2D 20 0C DD 36 +T 29 00 DD 71 04 DD 70 05 0A 47 D6 2D 20 0A 0E 01 R 00 00 00 00 -T 38 00 F0 01 DD 73 04 DD 72 05 18 0F +T 37 00 DD 73 04 DD 72 05 18 0D R 00 00 00 00 -T 42 00 +T 3F 00 R 00 00 00 00 -T 42 00 DD 36 F0 00 7C D6 2B 20 06 DD 73 04 DD 72 +T 3F 00 0E 00 78 D6 2B 20 06 DD 73 04 DD 72 05 R 00 00 00 00 -T 50 00 05 +T 4C 00 R 00 00 00 00 -T 51 00 +T 4C 00 DD 36 F2 00 DD 36 F3 00 DD 36 F4 00 DD 36 R 00 00 00 00 -T 51 00 DD 36 F5 00 DD 36 F6 00 DD 36 F7 00 DD 36 +T 5A 00 F5 00 DD 5E 04 DD 56 05 R 00 00 00 00 -T 5F 00 F8 00 DD 4E 04 DD 46 05 +T 62 00 R 00 00 00 00 -T 67 00 +T 62 00 1A 47 DD 70 F8 DD 36 F9 00 DD 6E F8 DD 75 R 00 00 00 00 -T 67 00 0A 6F 17 9F 67 C5 E5 CD 00 00 F1 EB C1 0A -R 00 00 00 00 02 0A 02 00 -T 75 00 DD 77 FF 21 01 00 09 DD 75 FD DD 74 FE 7A +T 70 00 FF 21 01 00 19 DD 75 F6 DD 74 F7 DD 7E FF R 00 00 00 00 -T 83 00 B3 28 6C DD 6E F7 DD 66 F8 E5 DD 6E F5 DD +T 7E 00 D6 30 38 72 3E 39 DD 96 FF 38 6B C5 DD 6E R 00 00 00 00 -T 91 00 66 F6 E5 21 20 41 E5 21 00 00 E5 CD 00 00 -R 00 00 00 00 02 0E 00 00 -T 9F 00 F1 F1 F1 F1 DD 72 FC DD 73 FB DD 74 FA DD +T 8C 00 F4 DD 66 F5 E5 DD 6E F2 DD 66 F3 E5 21 R 00 00 00 00 -T AD 00 75 F9 DD 66 FF DD 7E FF 17 9F 57 7C C6 D0 -R 00 00 00 00 -T BB 00 6F 7A CE FF 67 E5 CD 00 00 F1 EB E5 D5 DD -R 00 00 00 00 02 09 06 00 -T C9 00 6E FB DD 66 FC E5 DD 6E F9 DD 66 FA E5 CD -R 00 00 00 00 -T D7 00 00 00 F1 F1 F1 F1 DD 75 F5 DD 74 F6 DD 73 -R 00 00 00 00 02 02 05 00 -T E5 00 F7 DD 72 F8 DD 4E FD DD 46 FE C3 67 00 -R 00 00 00 00 00 0D 00 00 -T F2 00 -R 00 00 00 00 -T F2 00 DD 71 04 DD 70 05 DD 7E FF D6 2E C2 D4 01 -R 00 00 00 00 00 0E 00 00 -T 00 01 DD 36 F1 CD DD 36 F2 CC DD 36 F3 CC DD 36 -R 00 00 00 00 -T 0E 01 F4 3D DD 7E FD DD 77 F9 DD 7E FE DD 77 FA -R 00 00 00 00 -T 1C 01 -R 00 00 00 00 -T 1C 01 DD 6E F9 DD 66 FA 7E DD 77 FD DD 77 FD 17 -R 00 00 00 00 -T 2A 01 9F DD 77 FE DD 6E FD DD 66 FE E5 CD 00 00 -R 00 00 00 00 02 0E 02 00 -T 38 01 F1 7C B5 CA C8 01 DD 6E F9 DD 66 FA 7E 67 -R 00 00 00 00 00 06 00 00 -T 46 01 17 9F 6F 7C C6 D0 5F 7D CE FF 57 D5 CD -R 00 00 00 00 -T 53 01 00 00 F1 4D 44 DD 6E F3 DD 66 F4 E5 DD 6E -R 00 00 00 00 02 02 06 00 -T 61 01 F1 DD 66 F2 E5 D5 C5 CD 00 00 F1 F1 F1 F1 +T 99 00 20 41 E5 21 00 00 E5 CD 00 00 F1 F1 F1 F1 R 00 00 00 00 02 0A 00 00 -T 6F 01 EB E5 D5 DD 6E F7 DD 66 F8 E5 DD 6E F5 DD +T A7 00 DD 72 FE DD 73 FD DD 74 FC DD 75 FB C1 DD R 00 00 00 00 -T 7D 01 66 F6 E5 CD 00 00 F1 F1 F1 F1 DD 75 F5 DD -R 00 00 00 00 02 06 05 00 -T 8B 01 74 F6 DD 73 F7 DD 72 F8 DD 6E F3 DD 66 F4 +T B5 00 7E F8 C6 D0 5F DD 7E F9 CE FF 57 C5 D5 CD R 00 00 00 00 -T 99 01 E5 DD 6E F1 DD 66 F2 E5 21 CC 3D E5 21 +T C3 00 00 00 F1 EB E5 D5 DD 6E FD DD 66 FE E5 DD +R 00 00 00 00 02 02 05 00 +T D1 00 6E FB DD 66 FC E5 CD 00 00 F1 F1 F1 F1 C1 +R 00 00 00 00 02 09 04 00 +T DF 00 DD 75 F2 DD 74 F3 DD 73 F4 DD 72 F5 DD 5E R 00 00 00 00 -T A6 01 CD CC E5 CD 00 00 F1 F1 F1 F1 DD 75 F1 DD -R 00 00 00 00 02 06 00 00 -T B4 01 74 F2 DD 73 F3 DD 72 F4 DD 34 F9 C2 1C 01 -R 00 00 00 00 00 0E 00 00 -T C2 01 DD 34 FA C3 1C 01 -R 00 00 00 00 00 06 00 00 -T C8 01 +T ED 00 F6 DD 56 F7 C3 62 00 +R 00 00 00 00 00 07 00 00 +T F4 00 R 00 00 00 00 -T C8 01 DD 7E F9 DD 77 04 DD 7E FA DD 77 05 +T F4 00 DD 73 04 DD 72 05 78 D6 2E C2 19 02 DD 36 +R 00 00 00 00 00 0C 00 00 +T 02 01 EE CD DD 36 EF CC DD 36 F0 CC DD 36 F1 3D R 00 00 00 00 -T D4 01 +T 10 01 DD 46 F6 DD 5E F7 R 00 00 00 00 -T D4 01 DD 7E 04 DD 77 F9 DD 7E 05 DD 77 FA DD 6E +T 16 01 R 00 00 00 00 -T E2 01 F9 DD 66 FA 7E 6F 17 9F 67 E5 CD 00 00 F1 -R 00 00 00 00 02 0D 07 00 -T F0 01 7D D6 45 C2 7A 02 B4 C2 7A 02 DD 7E F9 C6 +T 16 01 68 63 56 DD 72 FB DD 36 FC 00 DD 56 FB 7A +R 00 00 00 00 +T 24 01 D6 30 DA 13 02 3E 39 92 DA 13 02 DD 7E FB +R 00 00 00 00 00 05 00 00 00 0B 00 00 +T 32 01 C6 D0 6F DD 7E FC CE FF 67 C5 D5 E5 CD +R 00 00 00 00 +T 3F 01 00 00 F1 DD 72 FE DD 73 FD DD 74 FC DD 75 +R 00 00 00 00 02 02 05 00 +T 4D 01 FB DD 6E F0 DD 66 F1 E5 DD 6E EE DD 66 EF +R 00 00 00 00 +T 5B 01 E5 DD 6E FD DD 66 FE E5 DD 6E FB DD 66 FC +R 00 00 00 00 +T 69 01 E5 CD 00 00 F1 F1 F1 F1 DD 72 FE DD 73 FD +R 00 00 00 00 02 04 00 00 +T 77 01 DD 74 FC DD 75 FB DD 6E FD DD 66 FE E5 DD +R 00 00 00 00 +T 85 01 6E FB DD 66 FC E5 DD 6E F4 DD 66 F5 E5 DD +R 00 00 00 00 +T 93 01 6E F2 DD 66 F3 E5 CD 00 00 F1 F1 F1 F1 DD +R 00 00 00 00 02 09 04 00 +T A1 01 72 FE DD 73 FD DD 74 FC DD 75 FB D1 C1 DD +R 00 00 00 00 +T AF 01 7E FB DD 77 F2 DD 7E FC DD 77 F3 DD 7E FD +R 00 00 00 00 +T BD 01 DD 77 F4 DD 7E FE DD 77 F5 C5 D5 DD 6E F0 +R 00 00 00 00 +T CB 01 DD 66 F1 E5 DD 6E EE DD 66 EF E5 21 CC 3D +R 00 00 00 00 +T D9 01 E5 21 CD CC E5 CD 00 00 F1 F1 F1 F1 DD 72 +R 00 00 00 00 02 08 00 00 +T E7 01 FE DD 73 FD DD 74 FC DD 75 FB D1 C1 DD 7E +R 00 00 00 00 +T F5 01 FB DD 77 EE DD 7E FC DD 77 EF DD 7E FD DD +R 00 00 00 00 +T 03 02 77 F0 DD 7E FE DD 77 F1 04 C2 16 01 1C C3 +R 00 00 00 00 00 0C 00 00 +T 11 02 16 01 +R 00 00 00 00 00 02 00 00 +T 13 02 +R 00 00 00 00 +T 13 02 DD 70 04 DD 73 05 +R 00 00 00 00 +T 19 02 +R 00 00 00 00 +T 19 02 DD 7E 04 DD 77 FB DD 7E 05 DD 77 FC DD 6E +R 00 00 00 00 +T 27 02 FB DD 66 FC 5E 16 00 C5 D5 CD 00 00 F1 C1 +R 00 00 00 00 02 0C 06 00 +T 35 02 7D D6 45 C2 CB 02 B4 C2 CB 02 DD 7E FB C6 R 00 00 00 00 00 06 00 00 00 0A 00 00 -T FE 01 01 DD 77 04 DD 7E FA CE 00 DD 77 05 DD 6E +T 43 02 01 DD 77 04 DD 7E FC CE 00 DD 77 05 C5 DD R 00 00 00 00 -T 0C 02 04 DD 66 05 E5 CD 00 00 F1 45 -R 00 00 00 00 02 08 03 00 -T 16 02 +T 51 02 6E 04 DD 66 05 E5 CD 00 00 F1 C1 DD 75 ED +R 00 00 00 00 02 09 02 00 +T 5F 02 R 00 00 00 00 -T 16 02 78 B7 28 60 CB 78 28 2E C5 DD 6E F7 DD 66 +T 5F 02 DD 7E ED B7 28 66 DD CB ED 7E 28 30 C5 DD R 00 00 00 00 -T 24 02 F8 E5 DD 6E F5 DD 66 F6 E5 21 CC 3D E5 21 +T 6D 02 6E F4 DD 66 F5 E5 DD 6E F2 DD 66 F3 E5 21 R 00 00 00 00 -T 32 02 CD CC E5 CD 00 00 F1 F1 F1 F1 C1 DD 75 F5 -R 00 00 00 00 02 06 00 00 -T 40 02 DD 74 F6 DD 73 F7 DD 72 F8 04 18 CA +T 7B 02 CC 3D E5 21 CD CC E5 CD 00 00 F1 F1 F1 F1 +R 00 00 00 00 02 0A 00 00 +T 89 02 C1 DD 75 F2 DD 74 F3 DD 73 F4 DD 72 F5 DD R 00 00 00 00 -T 4C 02 +T 97 02 34 ED 18 C4 R 00 00 00 00 -T 4C 02 C5 DD 6E F7 DD 66 F8 E5 DD 6E F5 DD 66 F6 +T 9B 02 R 00 00 00 00 -T 5A 02 E5 21 20 41 E5 21 00 00 E5 CD 00 00 F1 F1 +T 9B 02 C5 DD 6E F4 DD 66 F5 E5 DD 6E F2 DD 66 F3 +R 00 00 00 00 +T A9 02 E5 21 20 41 E5 21 00 00 E5 CD 00 00 F1 F1 R 00 00 00 00 02 0C 00 00 -T 68 02 F1 F1 C1 DD 75 F5 DD 74 F6 DD 73 F7 DD 72 +T B7 02 F1 F1 C1 DD 75 F2 DD 74 F3 DD 73 F4 DD 72 R 00 00 00 00 -T 76 02 F8 05 18 9C +T C5 02 F5 DD 35 ED 18 94 R 00 00 00 00 -T 7A 02 +T CB 02 R 00 00 00 00 -T 7A 02 DD CB F0 46 28 08 DD 7E F8 EE 80 DD 77 F8 +T CB 02 CB 41 28 08 DD 7E F5 EE 80 DD 77 F5 R 00 00 00 00 -T 88 02 +T D7 02 R 00 00 00 00 -T 88 02 DD 6E F5 DD 66 F6 DD 5E F7 DD 56 F8 DD F9 +T D7 02 DD 6E F2 DD 66 F3 DD 5E F4 DD 56 F5 DD F9 R 00 00 00 00 -T 96 02 DD E1 C9 +T E5 02 DD E1 C9 R 00 00 00 00 -_schar2fs.rel/ 1458795407 2001 2501 100664 557 ` +_schar2fs.rel/ 0 0 0 644 557 ` XL2 H 9 areas 3 global symbols M _schar2fs @@ -34028,12 +48708,12 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 04 00 -T 00 00 FD 21 02 00 FD 39 FD 6E 00 FD 7E 00 17 9F +T 00 00 FD 21 02 00 FD 39 FD 4E 00 FD 7E 00 17 9F R 00 00 04 00 -T 0E 00 67 5F 57 D5 E5 CD 00 00 F1 F1 C9 +T 0E 00 47 5F 57 D5 C5 CD 00 00 F1 F1 C9 R 00 00 04 00 02 08 00 00 -_sint2fs.rel/ 1458795407 2001 2501 100664 561 ` +_sint2fs.rel/ 0 0 0 644 561 ` XL2 H 9 areas 3 global symbols M _sint2fs @@ -34052,12 +48732,12 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 04 00 -T 00 00 FD 21 02 00 FD 39 FD 6E 00 FD 66 01 FD 7E +T 00 00 FD 21 02 00 FD 39 FD 4E 00 FD 46 01 FD 7E R 00 00 04 00 -T 0E 00 01 17 9F 5F 57 D5 E5 CD 00 00 F1 F1 C9 +T 0E 00 01 17 9F 5F 57 D5 C5 CD 00 00 F1 F1 C9 R 00 00 04 00 02 0A 00 00 -_slong2fs.rel/ 1458795407 2001 2501 100664 864 ` +_slong2fs.rel/ 0 0 0 644 864 ` XL2 H 9 areas 3 global symbols M _slong2fs @@ -34078,9 +48758,9 @@ T 00 00 R 00 00 04 00 T 00 00 DD E5 DD 21 00 00 DD 39 DD CB 07 7E 28 24 R 00 00 04 00 -T 0E 00 AF DD 96 04 6F 3E 00 DD 9E 05 67 3E 00 DD +T 0E 00 AF DD 96 04 4F 3E 00 DD 9E 05 47 3E 00 DD R 00 00 04 00 -T 1C 00 9E 06 5F 3E 00 DD 9E 07 57 D5 E5 CD 00 00 +T 1C 00 9E 06 5F 3E 00 DD 9E 07 57 D5 C5 CD 00 00 R 00 00 04 00 02 0E 00 00 T 2A 00 F1 F1 7A EE 80 57 18 13 R 00 00 04 00 @@ -34094,7 +48774,7 @@ T 45 00 R 00 00 04 00 T 45 00 DD E1 C9 R 00 00 04 00 -_uchar2fs.rel/ 1458795407 2001 2501 100664 548 ` +_uchar2fs.rel/ 0 0 0 644 536 ` XL2 H 9 areas 3 global symbols M _uchar2fs @@ -34105,7 +48785,7 @@ A _CODE size 0 flags 0 addr 0 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 A _DABS size 0 flags 8 addr 0 -A _HOME size 16 flags 0 addr 0 +A _HOME size 12 flags 0 addr 0 S ___uchar2fs Def0000 A _GSINIT size 0 flags 0 addr 0 A _GSFINAL size 0 flags 0 addr 0 @@ -34113,11 +48793,11 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 04 00 -T 00 00 FD 21 02 00 FD 39 FD 6E 00 26 00 11 00 00 +T 00 00 21 02 00 39 4E 06 00 11 00 00 D5 C5 CD R 00 00 04 00 -T 0E 00 D5 E5 CD 00 00 F1 F1 C9 -R 00 00 04 00 02 05 00 00 -_uint2fs.rel/ 1458795407 2001 2501 100664 537 ` +T 0D 00 00 00 F1 F1 C9 +R 00 00 04 00 02 02 00 00 +_uint2fs.rel/ 0 0 0 644 534 ` XL2 H 9 areas 3 global symbols M _uint2fs @@ -34128,7 +48808,7 @@ A _CODE size 0 flags 0 addr 0 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 A _DABS size 0 flags 8 addr 0 -A _HOME size 13 flags 0 addr 0 +A _HOME size 12 flags 0 addr 0 S ___uint2fs Def0000 A _GSINIT size 0 flags 0 addr 0 A _GSFINAL size 0 flags 0 addr 0 @@ -34136,12 +48816,11 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 04 00 -T 00 00 21 02 00 39 7E 23 66 6F 11 00 00 D5 E5 CD +T 00 00 21 02 00 39 4E 23 46 11 00 00 D5 C5 CD R 00 00 04 00 -T 0E 00 00 00 F1 F1 C9 +T 0D 00 00 00 F1 F1 C9 R 00 00 04 00 02 02 00 00 - -_ulong2fs.rel/ 1458795408 2001 2501 100664 1722 ` +_ulong2fs.rel/ 0 0 0 644 1716 ` XL2 H 9 areas 2 global symbols M _ulong2fs @@ -34151,7 +48830,7 @@ A _CODE size 0 flags 0 addr 0 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 A _DABS size 0 flags 8 addr 0 -A _HOME size E6 flags 0 addr 0 +A _HOME size E4 flags 0 addr 0 S ___ulong2fs Def0000 A _GSINIT size 0 flags 0 addr 0 A _GSFINAL size 0 flags 0 addr 0 @@ -34163,59 +48842,59 @@ T 00 00 DD E5 DD 21 00 00 DD 39 21 FA FF 39 F9 DD R 00 00 04 00 T 0E 00 7E 07 DD B6 06 DD B6 05 DD B6 04 20 08 21 R 00 00 04 00 -T 1C 00 00 00 5D 54 C3 E1 00 +T 1C 00 00 00 5D 54 C3 DF 00 R 00 00 04 00 00 07 04 00 T 23 00 R 00 00 04 00 -T 23 00 21 96 00 +T 23 00 01 96 00 R 00 00 04 00 T 26 00 R 00 00 04 00 -T 26 00 DD 7E 07 B7 28 15 F5 F1 DD CB 07 3E DD CB +T 26 00 DD 7E 07 B7 28 13 DD CB 07 3E DD CB 06 1E R 00 00 04 00 -T 34 00 06 1E DD CB 05 1E DD CB 04 1E 23 18 E5 +T 34 00 DD CB 05 1E DD CB 04 1E 03 18 E7 R 00 00 04 00 -T 41 00 +T 3F 00 R 00 00 04 00 -T 41 00 +T 3F 00 R 00 00 04 00 -T 41 00 DD 7E 06 D6 80 DD 7E 07 DE 00 30 15 F5 F1 +T 3F 00 DD 7E 06 D6 80 DD 7E 07 DE 00 30 13 DD CB R 00 00 04 00 -T 4F 00 DD CB 04 26 DD CB 05 16 DD CB 06 16 DD CB +T 4D 00 04 26 DD CB 05 16 DD CB 06 16 DD CB 07 16 R 00 00 04 00 -T 5D 00 07 16 2B 18 DF +T 5B 00 0B 18 E1 R 00 00 04 00 -T 62 00 +T 5E 00 R 00 00 04 00 -T 62 00 DD 75 FE DD 74 FF DD 56 04 DD 5E 05 DD 4E +T 5E 00 DD 71 FE DD 70 FF DD 5E 04 DD 56 05 DD 6E R 00 00 04 00 -T 70 00 06 CB B9 06 00 14 20 1F 1C 20 1C 79 D6 7F +T 6C 00 06 CB BD 26 00 1C 20 1F 14 20 1C 7D D6 7F R 00 00 04 00 -T 7E 00 20 17 B0 20 14 AF DD 77 04 DD 77 05 DD 77 +T 7A 00 20 17 B4 20 14 AF DD 77 04 DD 77 05 DD 77 R 00 00 04 00 -T 8C 00 06 DD 77 07 23 DD 75 FE DD 74 FF +T 88 00 06 DD 77 07 03 DD 71 FE DD 70 FF R 00 00 04 00 -T 97 00 +T 93 00 R 00 00 04 00 -T 97 00 DD CB 06 BE 21 00 00 39 DD 5E FE DD 56 FF +T 93 00 DD CB 06 BE 21 00 00 39 DD 4E FE DD 46 FF R 00 00 04 00 -T A5 00 DD 7E FF 17 9F 4F 47 3E 17 +T A1 00 DD 7E FF 17 9F 5F 57 F5 F1 3E 17 R 00 00 04 00 -T AE 00 +T AC 00 R 00 00 04 00 -T AE 00 CB 23 CB 12 CB 11 CB 10 3D 20 F5 7B DD B6 +T AC 00 CB 21 CB 10 CB 13 CB 12 3D 20 F5 79 DD B6 R 00 00 04 00 -T BC 00 04 5F 7A DD B6 05 57 79 DD B6 06 4F 78 DD +T BA 00 04 4F 78 DD B6 05 47 7B DD B6 06 5F 7A DD R 00 00 04 00 -T CA 00 B6 07 47 73 23 72 23 71 23 70 21 00 00 39 +T C8 00 B6 07 57 71 23 70 23 73 23 72 21 00 00 39 R 00 00 04 00 -T D8 00 46 23 4E 23 5E 23 56 68 61 +T D6 00 4E 23 46 23 5E 23 56 69 60 R 00 00 04 00 -T E1 00 +T DF 00 R 00 00 04 00 -T E1 00 DD F9 DD E1 C9 +T DF 00 DD F9 DD E1 C9 R 00 00 04 00 -_fs2schar.rel/ 1458795408 2001 2501 100664 982 ` +_fs2schar.rel/ 0 0 0 644 982 ` XL2 H 9 areas 3 global symbols M _fs2schar @@ -34260,7 +48939,7 @@ T 4B 00 R 00 00 04 00 T 4B 00 DD E1 C9 R 00 00 04 00 -_fs2sint.rel/ 1458795408 2001 2501 100664 986 ` +_fs2sint.rel/ 0 0 0 644 986 ` XL2 H 9 areas 3 global symbols M _fs2sint @@ -34305,7 +48984,7 @@ T 4D 00 R 00 00 04 00 T 4D 00 DD E1 C9 R 00 00 04 00 -_fs2slong.rel/ 1458795408 2001 2501 100664 1185 ` +_fs2slong.rel/ 0 0 0 644 1185 ` XL2 H 9 areas 4 global symbols M _fs2slong @@ -34337,9 +49016,9 @@ T 1F 00 21 00 00 E5 21 00 00 E5 DD 6E 06 DD 66 07 R 00 00 04 00 T 2D 00 E5 DD 6E 04 DD 66 05 E5 CD 00 00 F1 F1 F1 R 00 00 04 00 02 0B 01 00 -T 3B 00 F1 7D B7 28 27 DD 7E 07 EE 80 57 DD 6E 04 +T 3B 00 F1 7D B7 28 27 DD 7E 07 EE 80 57 DD 4E 04 R 00 00 04 00 -T 49 00 DD 66 05 DD 5E 06 D5 E5 CD 00 00 F1 F1 AF +T 49 00 DD 46 05 DD 5E 06 D5 C5 CD 00 00 F1 F1 AF R 00 00 04 00 02 0B 00 00 T 57 00 95 6F 3E 00 9C 67 3E 00 9B 5F 3E 00 9A 57 R 00 00 04 00 @@ -34356,7 +49035,7 @@ R 00 00 04 00 T 7A 00 DD E1 C9 R 00 00 04 00 -_fs2uchar.rel/ 1458795408 2001 2501 100664 708 ` +_fs2uchar.rel/ 0 0 0 644 708 ` XL2 H 9 areas 3 global symbols M _fs2uchar @@ -34387,7 +49066,7 @@ T 2B 00 R 00 00 04 00 T 2B 00 DD E1 C9 R 00 00 04 00 -_fs2uint.rel/ 1458795408 2001 2501 100664 709 ` +_fs2uint.rel/ 0 0 0 644 709 ` XL2 H 9 areas 3 global symbols M _fs2uint @@ -34419,7 +49098,7 @@ R 00 00 04 00 T 2C 00 DD E1 C9 R 00 00 04 00 -_fs2ulong.rel/ 1458795408 2001 2501 100664 1513 ` +_fs2ulong.rel/ 0 0 0 644 1450 ` XL2 H 9 areas 2 global symbols M _fs2ulong @@ -34429,7 +49108,7 @@ A _CODE size 0 flags 0 addr 0 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 A _DABS size 0 flags 8 addr 0 -A _HOME size C5 flags 0 addr 0 +A _HOME size B4 flags 0 addr 0 S ___fs2ulong Def0000 A _GSINIT size 0 flags 0 addr 0 A _GSFINAL size 0 flags 0 addr 0 @@ -34441,50 +49120,49 @@ T 00 00 DD E5 DD 21 00 00 DD 39 21 F6 FF 39 F9 21 R 00 00 04 00 T 0E 00 06 00 39 EB 21 0E 00 39 01 04 00 ED B0 21 R 00 00 04 00 -T 1C 00 06 00 39 5E 23 56 23 4E 23 7E B1 B2 B3 28 +T 1C 00 06 00 39 4E 23 46 23 5E 23 7E B3 B0 B1 28 R 00 00 04 00 -T 2A 00 11 21 06 00 39 5E 23 56 23 4E 23 7E CB 07 +T 2A 00 11 21 06 00 39 4E 23 46 23 5E 23 7E CB 07 R 00 00 04 00 -T 38 00 E6 01 28 08 +T 38 00 E6 01 28 07 R 00 00 04 00 T 3C 00 R 00 00 04 00 -T 3C 00 21 00 00 5D 54 C3 C0 00 -R 00 00 04 00 00 08 04 00 -T 44 00 +T 3C 00 21 00 00 5D 54 18 6C R 00 00 04 00 -T 44 00 21 06 00 39 5E 23 56 23 4E 23 46 3E 17 +T 43 00 R 00 00 04 00 -T 51 00 +T 43 00 21 06 00 39 4E 23 46 23 5E 23 56 F5 F1 06 R 00 00 04 00 -T 51 00 CB 38 CB 19 CB 1A CB 1B 3D 20 F5 16 00 01 +T 51 00 07 R 00 00 04 00 -T 5F 00 00 00 7B C6 6A 6F 7A CE FF 67 79 CE FF 78 +T 52 00 R 00 00 04 00 -T 6D 00 CE FF DD 75 FA DD 74 FB 21 06 00 39 5E 23 +T 52 00 CB 3A CB 1B 10 FA 0E 00 7B C6 6A DD 77 FA R 00 00 04 00 -T 7B 00 56 23 4E 23 46 CB B9 06 00 DD 73 F6 DD 72 +T 60 00 79 CE FF DD 77 FB 21 06 00 39 4E 23 46 23 R 00 00 04 00 -T 89 00 F7 79 CB FF DD 77 F8 DD 70 F9 AF DD 96 FA +T 6E 00 5E 23 56 CB BB 16 00 DD 71 F6 DD 70 F7 7B R 00 00 04 00 -T 97 00 47 3E 00 DD 9E FB F5 F1 04 18 10 +T 7C 00 CB FF DD 77 F8 DD 72 F9 AF DD 96 FA 47 3E R 00 00 04 00 -T A2 00 +T 8A 00 00 DD 9E FB 04 18 10 R 00 00 04 00 -T A2 00 DD CB F9 2E DD CB F8 1E DD CB F7 1E DD CB +T 91 00 R 00 00 04 00 -T B0 00 F6 1E +T 91 00 DD CB F9 2E DD CB F8 1E DD CB F7 1E DD CB R 00 00 04 00 -T B2 00 +T 9F 00 F6 1E R 00 00 04 00 -T B2 00 10 EE DD 6E F6 DD 66 F7 DD 5E F8 DD 56 F9 +T A1 00 R 00 00 04 00 -T C0 00 +T A1 00 10 EE DD 6E F6 DD 66 F7 DD 5E F8 DD 56 F9 R 00 00 04 00 -T C0 00 DD F9 DD E1 C9 +T AF 00 R 00 00 04 00 - -_fsadd.rel/ 1458795409 2001 2501 100664 6804 ` +T AF 00 DD F9 DD E1 C9 +R 00 00 04 00 +_fsadd.rel/ 0 0 0 644 6194 ` XL2 H 9 areas 2 global symbols M _fsadd @@ -34494,7 +49172,7 @@ A _CODE size 0 flags 0 addr 0 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 A _DABS size 0 flags 8 addr 0 -A _HOME size 455 flags 0 addr 0 +A _HOME size 3D3 flags 0 addr 0 S ___fsadd Def0000 A _GSINIT size 0 flags 0 addr 0 A _GSFINAL size 0 flags 0 addr 0 @@ -34502,287 +49180,269 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 04 00 -T 00 00 DD E5 DD 21 00 00 DD 39 21 E1 FF 39 F9 21 +T 00 00 DD E5 DD 21 00 00 DD 39 21 E5 FF 39 F9 21 R 00 00 04 00 -T 0E 00 27 00 39 EB 21 11 00 39 EB 01 04 00 ED B0 +T 0E 00 23 00 39 EB 21 11 00 39 EB 01 04 00 ED B0 R 00 00 04 00 -T 1C 00 21 17 00 39 EB 21 11 00 39 01 04 00 ED B0 +T 1C 00 21 15 00 39 EB 21 11 00 39 01 04 00 ED B0 R 00 00 04 00 -T 2A 00 F5 DD 6E F8 DD 66 F9 DD 56 FA DD 4E FB F1 +T 2A 00 DD 5E FC DD 56 FD 06 07 R 00 00 04 00 -T 38 00 06 17 +T 32 00 R 00 00 04 00 -T 3A 00 +T 32 00 CB 3A CB 1B 10 FA DD 73 E8 DD 36 E9 00 DD R 00 00 04 00 -T 3A 00 CB 39 CB 1A CB 1C CB 1D 10 F6 DD 75 E4 DD +T 40 00 4E F6 DD 46 F7 DD 5E F8 CB BB 16 00 CB FB R 00 00 04 00 -T 48 00 36 E5 00 DD 6E F8 DD 66 F9 DD 4E FA CB B9 +T 4E 00 DD 71 EE DD 70 EF DD 73 F0 DD 72 F1 06 04 R 00 00 04 00 -T 56 00 06 00 79 CB FF 57 F5 DD 75 EA DD 74 EB DD +T 5C 00 R 00 00 04 00 -T 64 00 72 EC DD 70 ED F1 3E 04 +T 5C 00 DD CB EE 26 DD CB EF 16 DD CB F0 16 DD CB R 00 00 04 00 -T 6C 00 +T 6A 00 F1 16 10 EE DD 7E FD 07 30 1F AF DD 96 EE R 00 00 04 00 -T 6C 00 DD CB EA 26 DD CB EB 16 DD CB EC 16 DD CB +T 78 00 DD 77 EE 3E 00 DD 9E EF DD 77 EF 3E 00 DD R 00 00 04 00 -T 7A 00 ED 16 3D 20 ED DD 7E FB CB 07 E6 01 28 1F +T 86 00 9E F0 DD 77 F0 3E 00 DD 9E F1 DD 77 F1 R 00 00 04 00 -T 88 00 AF DD 96 EA DD 77 EA 3E 00 DD 9E EB DD 77 +T 93 00 R 00 00 04 00 -T 96 00 EB 3E 00 DD 9E EC DD 77 EC 3E 00 DD 9E ED +T 93 00 DD 7E F9 DD B6 F8 DD B6 F7 DD B6 F6 20 0F R 00 00 04 00 -T A4 00 DD 77 ED +T A1 00 DD 6E 04 DD 66 05 DD 5E 06 DD 56 07 C3 R 00 00 04 00 -T A7 00 -R 00 00 04 00 -T A7 00 DD 7E F5 DD B6 F4 DD B6 F3 DD B6 F2 20 0F -R 00 00 04 00 -T B5 00 DD 6E 04 DD 66 05 DD 5E 06 DD 56 07 C3 -R 00 00 04 00 -T C2 00 50 04 +T AE 00 CE 03 R 00 00 04 00 00 02 04 00 -T C4 00 +T B0 00 R 00 00 04 00 -T C4 00 21 23 00 39 DD 75 F8 DD 74 F9 DD 7E F8 DD +T B0 00 21 1F 00 39 DD 75 EC DD 74 ED DD 6E EC DD R 00 00 04 00 -T D2 00 77 E8 DD 7E F9 DD 77 E9 DD 5E E8 DD 56 E9 +T BE 00 66 ED 4E 23 46 23 5E 23 56 DD 71 FA DD 70 R 00 00 04 00 -T E0 00 21 17 00 39 EB 01 04 00 ED B0 21 11 00 39 +T CC 00 FB DD 73 FC DD 72 FD DD 7E FC DD 77 F6 DD R 00 00 04 00 -T EE 00 EB 21 17 00 39 01 04 00 ED B0 F5 DD 6E F2 +T DA 00 7E FD DD 77 F7 DD 36 F8 00 DD 36 F9 00 3E R 00 00 04 00 -T FC 00 DD 66 F3 DD 5E F4 DD 56 F5 F1 06 17 +T E8 00 07 R 00 00 04 00 -T 08 01 +T E9 00 R 00 00 04 00 -T 08 01 CB 3A CB 1B CB 1C CB 1D 10 F6 26 00 1E 00 +T E9 00 DD CB F7 3E DD CB F6 1E 3D 20 F5 DD 6E F6 R 00 00 04 00 -T 16 01 DD 75 F6 DD 74 F7 DD 6E F2 DD 66 F3 DD 4E +T F7 00 DD 75 F6 DD 36 F7 00 DD 71 F2 DD 70 F3 7B R 00 00 04 00 -T 24 01 F4 CB B9 06 00 79 CB FF 57 F5 DD 75 FC DD +T 05 01 E6 7F DD 77 F4 DD 36 F5 00 DD CB F4 FE 3E R 00 00 04 00 -T 32 01 74 FD DD 72 FE DD 70 FF F1 3E 04 +T 13 01 04 R 00 00 04 00 -T 3D 01 +T 14 01 R 00 00 04 00 -T 3D 01 DD CB FC 26 DD CB FD 16 DD CB FE 16 DD CB +T 14 01 DD CB F2 26 DD CB F3 16 DD CB F4 16 DD CB R 00 00 04 00 -T 4B 01 FF 16 3D 20 ED DD 7E F5 CB 07 E6 01 28 25 +T 22 01 F5 16 3D 20 ED DD 7E FD 07 30 23 CB 7A 28 R 00 00 04 00 -T 59 01 DD CB F5 7E 28 1F AF DD 96 FC DD 77 FC 3E +T 30 01 1F AF DD 96 F2 DD 77 F2 3E 00 DD 9E F3 DD R 00 00 04 00 -T 67 01 00 DD 9E FD DD 77 FD 3E 00 DD 9E FE DD 77 +T 3E 01 77 F3 3E 00 DD 9E F4 DD 77 F4 3E 00 DD 9E R 00 00 04 00 -T 75 01 FE 3E 00 DD 9E FF DD 77 FF +T 4C 01 F5 DD 77 F5 R 00 00 04 00 -T 7E 01 +T 50 01 R 00 00 04 00 -T 7E 01 DD 7E FB DD B6 FA DD B6 F9 DD B6 F8 20 0F +T 50 01 7A B3 B0 B1 20 0F DD 6E 08 DD 66 09 DD 5E R 00 00 04 00 -T 8C 01 DD 6E 08 DD 66 09 DD 5E 0A DD 56 0B C3 +T 5E 01 0A DD 56 0B C3 CE 03 +R 00 00 04 00 00 07 04 00 +T 65 01 R 00 00 04 00 -T 99 01 50 04 -R 00 00 04 00 00 02 04 00 -T 9B 01 +T 65 01 DD 7E F6 DD 96 E8 DD 77 FA DD 7E F7 DD 9E R 00 00 04 00 -T 9B 01 DD 7E F6 DD 96 E4 DD 77 F8 DD 7E F7 DD 9E +T 73 01 E9 DD 77 FB 3E 19 DD BE FA 3E 00 DD 9E FB R 00 00 04 00 -T A9 01 E5 DD 77 F9 3E 19 DD BE F8 3E 00 DD 9E F9 -R 00 00 04 00 -T B7 01 E2 BC 01 EE 80 +T 81 01 E2 86 01 EE 80 R 00 00 04 00 00 03 04 00 -T BC 01 +T 86 01 R 00 00 04 00 -T BC 01 F2 CE 01 DD 6E 04 DD 66 05 DD 5E 06 DD 56 +T 86 01 F2 98 01 DD 6E 04 DD 66 05 DD 5E 06 DD 56 R 00 00 04 00 00 03 04 00 -T CA 01 07 C3 50 04 +T 94 01 07 C3 CE 03 R 00 00 04 00 00 04 04 00 -T CE 01 +T 98 01 R 00 00 04 00 -T CE 01 DD 7E F8 D6 E7 DD 7E F9 17 3F 1F DE 7F 30 +T 98 01 DD 7E FA D6 E7 DD 7E FB 17 3F 1F DE 7F 30 R 00 00 04 00 -T DC 01 0F DD 6E 08 DD 66 09 DD 5E 0A DD 56 0B C3 +T A6 01 0F DD 6E 08 DD 66 09 DD 5E 0A DD 56 0B C3 R 00 00 04 00 -T EA 01 50 04 +T B4 01 CE 03 R 00 00 04 00 00 02 04 00 -T EC 01 +T B6 01 R 00 00 04 00 -T EC 01 DD CB F9 7E 28 49 AF DD 96 F8 DD 77 F2 3E +T B6 01 DD CB FB 7E 28 49 AF DD 96 FA DD 77 FE 3E R 00 00 04 00 -T FA 01 00 DD 9E F9 DD 77 F3 DD 7E F2 DD 77 E2 DD +T C4 01 00 DD 9E FB DD 77 FF DD 7E FE DD 77 E6 DD R 00 00 04 00 -T 08 02 7E F3 DD 77 E3 DD 7E F6 DD 86 E2 DD 77 F6 +T D2 01 7E FF DD 77 E7 DD 7E F6 DD 86 E6 DD 77 F6 R 00 00 04 00 -T 16 02 DD 7E F7 DD 8E E3 DD 77 F7 DD 46 E2 F5 F1 +T E0 01 DD 7E F7 DD 8E E7 DD 77 F7 DD 46 E6 F5 F1 R 00 00 04 00 -T 24 02 04 18 10 +T EE 01 04 18 10 R 00 00 04 00 -T 27 02 +T F1 01 R 00 00 04 00 -T 27 02 DD CB FF 2E DD CB FE 1E DD CB FD 1E DD CB +T F1 01 DD CB F5 2E DD CB F4 1E DD CB F3 1E DD CB R 00 00 04 00 -T 35 02 FC 1E +T FF 01 F2 1E R 00 00 04 00 -T 37 02 +T 01 02 R 00 00 04 00 -T 37 02 10 EE 18 1A +T 01 02 10 EE 18 1A R 00 00 04 00 -T 3B 02 +T 05 02 R 00 00 04 00 -T 3B 02 DD 46 F8 F5 F1 04 18 10 +T 05 02 DD 46 FA F5 F1 04 18 10 R 00 00 04 00 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00 00 00 -T 6D 02 39 01 04 00 ED B0 DD 6E E9 DD 66 EA E5 DD +T 71 02 39 01 04 00 ED B0 DD 6E E9 DD 66 EA E5 DD R 00 00 00 00 -T 7B 02 6E E7 DD 66 E8 E5 21 88 3B E5 21 08 53 E5 +T 7F 02 6E E7 DD 66 E8 E5 21 88 3B E5 21 08 53 E5 R 00 00 00 00 -T 89 02 CD 00 00 F1 F1 F1 F1 DD 72 FB DD 73 FA DD +T 8D 02 CD 00 00 F1 F1 F1 F1 DD 72 FD DD 73 FC DD R 00 00 00 00 02 03 01 00 -T 97 02 74 F9 DD 75 F8 21 80 3E E5 21 00 00 E5 DD +T 9B 02 74 FB DD 75 FA 21 80 3E E5 21 00 00 E5 DD R 00 00 00 00 -T A5 02 6E FA DD 66 FB E5 DD 6E F8 DD 66 F9 E5 CD +T A9 02 6E FC DD 66 FD E5 DD 6E FA DD 66 FB E5 CD R 00 00 00 00 -T B3 02 00 00 F1 F1 F1 F1 DD 72 FB DD 73 FA DD 74 +T B7 02 00 00 F1 F1 F1 F1 DD 72 FD DD 73 FC DD 74 R 00 00 00 00 02 02 06 00 -T C1 02 F9 DD 75 F8 DD 6E F1 DD 66 F2 E5 DD 6E EF +T C5 02 FB DD 75 FA DD 6E F1 DD 66 F2 E5 DD 6E EF R 00 00 00 00 -T CF 02 DD 66 F0 E5 DD 6E FA DD 66 FB E5 DD 6E F8 +T D3 02 DD 66 F0 E5 DD 6E FC DD 66 FD E5 DD 6E FA R 00 00 00 00 -T DD 02 DD 66 F9 E5 CD 00 00 F1 F1 F1 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F5 DD 6E FC DD 66 FD R 00 00 00 00 -T 5A 03 E5 DD 6E F8 DD 66 F9 E5 DD 6E FE DD 66 FF +T 5E 03 E5 DD 6E FA DD 66 FB E5 DD 6E F7 DD 66 F8 R 00 00 00 00 -T 68 03 E5 DD 6E FC DD 66 FD E5 CD 00 00 F1 F1 F1 +T 6C 03 E5 DD 6E F5 DD 66 F6 E5 CD 00 00 F1 F1 F1 R 00 00 00 00 02 0B 00 00 -T 76 03 F1 DD 72 FF DD 73 FE DD 74 FD DD 75 FC DD +T 7A 03 F1 DD 72 F8 DD 73 F7 DD 74 F6 DD 75 F5 DD R 00 00 00 00 -T 84 03 6E FE DD 66 FF E5 DD 6E FC DD 66 FD E5 DD +T 88 03 6E F7 DD 66 F8 E5 DD 6E F5 DD 66 F6 E5 DD R 00 00 00 00 -T 92 03 6E FA DD 66 FB E5 DD 6E F8 DD 66 F9 E5 CD +T 96 03 6E FC DD 66 FD E5 DD 6E FA DD 66 FB E5 CD R 00 00 00 00 -T A0 03 00 00 F1 F1 F1 F1 DD 72 FB DD 73 FA DD 74 +T A4 03 00 00 F1 F1 F1 F1 DD 72 FD DD 73 FC DD 74 R 00 00 00 00 02 02 0A 00 -T AE 03 F9 DD 75 F8 21 00 3F E5 21 00 00 E5 DD 6E +T B2 03 FB DD 75 FA 21 00 3F E5 21 00 00 E5 DD 6E R 00 00 00 00 -T BC 03 FA DD 66 FB E5 DD 6E F8 DD 66 F9 E5 CD +T C0 03 FC DD 66 FD E5 DD 6E FA DD 66 FB E5 CD R 00 00 00 00 -T C9 03 00 00 F1 F1 F1 F1 DD 72 FB DD 73 FA DD 74 +T CD 03 00 00 F1 F1 F1 F1 DD 72 FD DD 73 FC DD 74 R 00 00 00 00 02 02 06 00 -T D7 03 F9 DD 75 F8 21 09 00 39 EB 21 16 00 39 01 +T DB 03 FB DD 75 FA 21 09 00 39 EB 21 18 00 39 01 R 00 00 00 00 -T E5 03 04 00 ED B0 DD 7E F6 C6 01 DD 77 F3 DD 7E +T E9 03 04 00 ED B0 DD 7E FE C6 01 DD 77 F3 DD 7E R 00 00 00 00 -T F3 03 F7 CE 00 DD 77 F4 DD 6E F3 DD 66 F4 E5 DD +T F7 03 FF CE 00 DD 77 F4 DD 6E F3 DD 66 F4 E5 DD R 00 00 00 00 -T 01 04 6E ED DD 66 EE E5 DD 6E EB DD 66 EC E5 CD +T 05 04 6E ED DD 66 EE E5 DD 6E EB DD 66 EC E5 CD R 00 00 00 00 -T 0F 04 00 00 F1 F1 F1 DD 72 FB DD 73 FA DD 74 F9 +T 13 04 00 00 F1 F1 F1 DD 72 FD DD 73 FC DD 74 FB R 00 00 00 00 02 02 07 00 -T 1D 04 DD 75 F8 DD CB E2 46 28 34 DD 6E FA DD 66 +T 21 04 DD 75 FA DD CB E2 46 28 34 DD 6E FC DD 66 R 00 00 00 00 -T 2B 04 FB E5 DD 6E F8 DD 66 F9 E5 21 80 3F E5 21 +T 2F 04 FD E5 DD 6E FA DD 66 FB E5 21 80 3F E5 21 R 00 00 00 00 -T 39 04 00 00 E5 CD 00 00 F1 F1 F1 F1 DD 72 FF DD +T 3D 04 00 00 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5C 55 21 1B 00 39 EB 01 04 00 ED B0 DD +T 07 03 C5 EB 21 17 00 39 EB 01 04 00 ED B0 DD 6E R 00 00 00 00 -T 15 03 6E FE DD 66 FF E5 DD 6E FC DD 66 FD E5 CD +T 15 03 FA DD 66 FB E5 DD 6E F8 DD 66 F9 E5 CD R 00 00 00 00 -T 23 03 00 00 F1 F1 F1 F1 4D 44 DD 6E FE DD 66 FF +T 22 03 00 00 F1 F1 F1 F1 4D 44 DD 6E FA DD 66 FB R 00 00 00 00 02 02 07 00 -T 31 03 E5 DD 6E FC DD 66 FD E5 D5 C5 CD 00 00 F1 +T 30 03 E5 DD 6E F8 DD 66 F9 E5 D5 C5 CD 00 00 F1 R 00 00 00 00 02 0D 07 00 -T 3F 03 F1 F1 F1 DD 75 E7 DD 74 E8 DD 73 E9 DD 72 +T 3E 03 F1 F1 F1 DD 75 E7 DD 74 E8 DD 73 E9 DD 72 R 00 00 00 00 -T 4D 03 EA C3 09 04 +T 4C 03 EA C3 06 04 R 00 00 00 00 00 04 00 00 -T 51 03 +T 50 03 R 00 00 00 00 -T 51 03 DD 7E F7 C6 1A 04 67 DD 7E F8 CE 1A 04 6F +T 50 03 DD 7E F4 C6 17 04 6F DD 7E F5 CE 17 04 67 R 00 00 00 00 09 06 00 00 89 0D 00 00 -T 5D 03 D5 C5 5C 55 21 1B 00 39 EB 01 04 00 ED B0 +T 5C 03 D5 C5 EB 21 17 00 39 EB 01 04 00 ED B0 DD R 00 00 00 00 -T 6B 03 DD 6E FE DD 66 FF E5 DD 6E FC DD 66 FD E5 +T 6A 03 6E FA DD 66 FB E5 DD 6E F8 DD 66 F9 E5 CD R 00 00 00 00 -T 79 03 CD 00 00 F1 F1 F1 F1 4D 44 DD 6E FE DD 66 -R 00 00 00 00 02 03 00 00 -T 87 03 FF E5 DD 6E FC DD 66 FD E5 D5 C5 CD 00 00 -R 00 00 00 00 02 0E 07 00 -T 95 03 F1 F1 F1 F1 DD 75 E7 DD 74 E8 DD 73 E9 DD +T 78 03 00 00 F1 F1 F1 F1 4D 44 DD 6E FA DD 66 FB +R 00 00 00 00 02 02 00 00 +T 86 03 E5 DD 6E F8 DD 66 F9 E5 D5 C5 CD 00 00 F1 +R 00 00 00 00 02 0D 07 00 +T 94 03 F1 F1 F1 DD 75 E7 DD 74 E8 DD 73 E9 DD 72 R 00 00 00 00 -T A3 03 72 EA 18 62 +T A2 03 EA 18 61 R 00 00 00 00 -T A7 03 +T A5 03 R 00 00 00 00 -T A7 03 3E 1A 04 DD 86 F7 67 3E 1A 04 DD 8E F8 6F +T A5 03 3E 17 04 DD 86 F4 6F 3E 17 04 DD 8E F5 67 R 00 00 00 00 09 03 00 00 89 0A 00 00 -T B3 03 D5 C5 5C 55 21 1B 00 39 EB 01 04 00 ED B0 +T B1 03 D5 C5 EB 21 17 00 39 EB 01 04 00 ED B0 DD R 00 00 00 00 -T C1 03 DD 6E FE DD 66 FF E5 DD 6E FC DD 66 FD E5 +T BF 03 6E FA DD 66 FB E5 DD 6E F8 DD 66 F9 E5 CD R 00 00 00 00 -T CF 03 CD 00 00 F1 F1 F1 F1 4D 44 DD 6E FE DD 66 -R 00 00 00 00 02 03 07 00 -T DD 03 FF E5 DD 6E FC DD 66 FD E5 D5 C5 CD 00 00 -R 00 00 00 00 02 0E 07 00 -T EB 03 F1 F1 F1 F1 DD 75 E7 DD 74 E8 DD 73 E9 DD +T CD 03 00 00 F1 F1 F1 F1 4D 44 DD 6E FA DD 66 FB +R 00 00 00 00 02 02 07 00 +T DB 03 E5 DD 6E F8 DD 66 F9 E5 D5 C5 CD 00 00 F1 +R 00 00 00 00 02 0D 07 00 +T E9 03 F1 F1 F1 DD 75 E7 DD 74 E8 DD 73 E9 DD 72 R 00 00 00 00 -T F9 03 72 EA DD 7E F3 B7 28 08 DD 7E EA EE 80 DD +T F7 03 EA DD 7E FC B7 28 08 DD 7E EA EE 80 DD 77 R 00 00 00 00 -T 07 04 77 EA +T 05 04 EA R 00 00 00 00 -T 09 04 +T 06 04 R 00 00 00 00 -T 09 04 DD 6E E7 DD 66 E8 DD 5E E9 DD 56 EA +T 06 04 DD 6E E7 DD 66 E8 DD 5E E9 DD 56 EA R 00 00 00 00 -T 15 04 +T 12 04 R 00 00 00 00 -T 15 04 DD F9 DD E1 C9 +T 12 04 DD F9 DD E1 C9 R 00 00 00 00 -T 1A 04 +T 17 04 R 00 00 00 00 -T 1A 04 00 00 00 00 DB 0F 49 3F +T 17 04 00 00 00 00 DB 0F 49 3F R 00 00 00 00 -T 22 04 +T 1F 04 R 00 00 00 00 -T 22 04 DB 0F C9 3F DB 0F 49 3F +T 1F 04 DB 0F C9 3F DB 0F 49 3F R 00 00 00 00 - -asinf.rel/ 1458795419 2001 2501 100664 1271 ` +asinf.rel/ 0 0 0 644 1271 ` XL2 H 9 areas 4 global symbols M asinf @@ -37027,7 +51689,7 @@ R 00 00 00 00 02 0C 02 00 T 94 00 33 C9 R 00 00 00 00 -acosf.rel/ 1458795419 2001 2501 100664 1296 ` +acosf.rel/ 0 0 0 644 1296 ` XL2 H 9 areas 4 global symbols M acosf @@ -37081,7 +51743,7 @@ T 86 00 66 03 E5 FD 6E 00 FD 66 01 E5 CD 00 00 F1 R 00 00 00 00 02 0D 02 00 T 94 00 F1 33 C9 R 00 00 00 00 -atanf.rel/ 1458795419 2001 2501 100664 4747 ` +atanf.rel/ 0 0 0 644 4747 ` XL2 H 9 areas 9 global symbols M atanf @@ -37220,25 +51882,25 @@ T 8F 02 F2 9A 02 DD 7E FF EE 80 DD 77 FF R 00 00 00 00 00 03 00 00 T 9A 02 R 00 00 00 00 -T 9A 02 11 06 03 E1 E5 29 29 19 5E 23 56 23 4E 23 +T 9A 02 01 06 03 E1 E5 29 29 09 4E 23 46 23 5E 23 R 00 00 00 00 00 03 00 00 -T A8 02 46 C5 D5 DD 6E FE DD 66 FF E5 DD 6E FC DD +T A8 02 56 D5 C5 DD 6E FE DD 66 FF E5 DD 6E FC DD R 00 00 00 00 T B6 02 66 FD E5 CD 00 00 F1 F1 F1 F1 DD 72 FB DD R 00 00 00 00 02 06 05 00 -T C4 02 73 FA DD 74 F9 DD 75 F8 45 DD 4E F9 DD 5E +T C4 02 73 FA DD 74 F9 DD 75 F8 4D DD 46 F9 DD 5E R 00 00 00 00 T D2 02 FA DD 56 FB C5 D5 21 00 00 E5 21 00 00 E5 R 00 00 00 00 T E0 02 DD 6E 06 DD 66 07 E5 DD 6E 04 DD 66 05 E5 R 00 00 00 00 -T EE 02 CD 00 00 F1 F1 F1 F1 7D D1 C1 B7 28 04 7A +T EE 02 CD 00 00 F1 F1 F1 F1 D1 C1 7D B7 28 04 7A R 00 00 00 00 02 03 03 00 T FC 02 EE 80 57 R 00 00 00 00 T FF 02 R 00 00 00 00 -T FF 02 68 61 DD F9 DD E1 C9 +T FF 02 69 60 DD F9 DD E1 C9 R 00 00 00 00 T 06 03 R 00 00 00 00 @@ -37247,7 +51909,7 @@ R 00 00 00 00 T 14 03 86 3F R 00 00 00 00 -atan2f.rel/ 1458795420 2001 2501 100664 3132 ` +atan2f.rel/ 0 0 0 644 3135 ` XL2 H 9 areas 8 global symbols M atan2f @@ -37259,7 +51921,7 @@ S ___fsadd Ref0000 S _fabsf Ref0000 S _atanf Ref0000 S ___fsdiv Ref0000 -A _CODE size 1D7 flags 0 addr 0 +A _CODE size 1D8 flags 0 addr 0 S _atan2f Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -37279,7 +51941,7 @@ T 1C 00 1E DD 7E 0B CB BF DD B6 0A DD B6 09 DD B6 R 00 00 00 00 T 2A 00 08 20 0E 21 21 00 22 00 00 21 00 00 5D 54 R 00 00 00 00 02 09 00 00 -T 38 00 C3 D2 01 +T 38 00 C3 D3 01 R 00 00 00 00 00 03 00 00 T 3B 00 R 00 00 00 00 @@ -37301,71 +51963,72 @@ T 9D 00 FF E5 DD 6E FC DD 66 FD E5 DD 6E FA DD 66 R 00 00 00 00 T AB 00 FB E5 DD 6E F8 DD 66 F9 E5 CD 00 00 F1 F1 R 00 00 00 00 02 0C 01 00 -T B9 00 F1 F1 7D C1 47 B7 C2 55 01 C5 DD 6E 0A DD -R 00 00 00 00 00 09 00 00 -T C7 00 66 0B E5 DD 6E 08 DD 66 09 E5 DD 6E 06 DD +T B9 00 F1 F1 7D C1 47 CB 40 C2 56 01 C5 DD 6E 0A +R 00 00 00 00 00 0A 00 00 +T C7 00 DD 66 0B E5 DD 6E 08 DD 66 09 E5 DD 6E 06 R 00 00 00 00 -T D5 00 66 07 E5 DD 6E 04 DD 66 05 E5 CD 00 00 F1 -R 00 00 00 00 02 0D 06 00 -T E3 00 F1 F1 F1 D5 E5 CD 00 00 F1 F1 C1 DD 75 FC -R 00 00 00 00 02 08 05 00 -T F1 00 DD 74 FD DD 73 FE DD 72 FF C5 21 00 00 E5 +T D5 00 DD 66 07 E5 DD 6E 04 DD 66 05 E5 CD 00 00 +R 00 00 00 00 02 0E 06 00 +T E3 00 F1 F1 F1 F1 D5 E5 CD 00 00 F1 F1 C1 DD 75 +R 00 00 00 00 02 09 05 00 +T F1 00 FC DD 74 FD DD 73 FE DD 72 FF C5 21 00 00 R 00 00 00 00 -T FF 00 21 00 00 E5 DD 6E 0A DD 66 0B E5 DD 6E 08 +T FF 00 E5 21 00 00 E5 DD 6E 0A DD 66 0B E5 DD 6E R 00 00 00 00 -T 0D 01 DD 66 09 E5 CD 00 00 F1 F1 F1 F1 7D C1 B7 -R 00 00 00 00 02 07 01 00 -T 1B 01 CA C6 01 79 B7 20 08 11 DB 0F 21 49 40 18 -R 00 00 00 00 00 03 00 00 -T 29 01 06 +T 0D 01 08 DD 66 09 E5 CD 00 00 F1 F1 F1 F1 C1 7D +R 00 00 00 00 02 08 01 00 +T 1B 01 B7 CA C7 01 CB 41 20 08 01 DB 0F 11 49 40 +R 00 00 00 00 00 04 00 00 +T 29 01 18 06 R 00 00 00 00 -T 2A 01 +T 2B 01 R 00 00 00 00 -T 2A 01 11 DB 0F 21 49 C0 +T 2B 01 01 DB 0F 11 49 C0 R 00 00 00 00 -T 30 01 +T 31 01 R 00 00 00 00 -T 30 01 E5 D5 DD 6E FE DD 66 FF E5 DD 6E FC DD 66 +T 31 01 D5 C5 DD 6E FE DD 66 FF E5 DD 6E FC DD 66 R 00 00 00 00 -T 3E 01 FD E5 CD 00 00 F1 F1 F1 F1 DD 75 FC DD 74 +T 3F 01 FD E5 CD 00 00 F1 F1 F1 F1 DD 75 FC DD 74 R 00 00 00 00 02 05 03 00 -T 4C 01 FD DD 73 FE DD 72 FF 18 71 +T 4D 01 FD DD 73 FE DD 72 FF 18 71 R 00 00 00 00 -T 55 01 +T 56 01 R 00 00 00 00 -T 55 01 C5 DD 6E 06 DD 66 07 E5 DD 6E 04 DD 66 05 +T 56 01 C5 DD 6E 06 DD 66 07 E5 DD 6E 04 DD 66 05 R 00 00 00 00 -T 63 01 E5 DD 6E 0A DD 66 0B E5 DD 6E 08 DD 66 09 +T 64 01 E5 DD 6E 0A DD 66 0B E5 DD 6E 08 DD 66 09 R 00 00 00 00 -T 71 01 E5 CD 00 00 F1 F1 F1 F1 D5 E5 CD 00 00 F1 +T 72 01 E5 CD 00 00 F1 F1 F1 F1 D5 E5 CD 00 00 F1 R 00 00 00 00 02 04 06 00 02 0D 05 00 -T 7F 01 F1 C1 7A EE 80 57 DD 75 F4 DD 74 F5 DD 73 +T 80 01 F1 C1 7A EE 80 47 DD 75 F4 DD 74 F5 DD 73 R 00 00 00 00 -T 8D 01 F6 DD 72 F7 79 B7 28 08 11 DB 0F 21 C9 BF +T 8E 01 F6 DD 70 F7 CB 41 28 08 01 DB 0F 11 C9 BF R 00 00 00 00 -T 9B 01 18 06 +T 9C 01 18 06 R 00 00 00 00 -T 9D 01 +T 9E 01 R 00 00 00 00 -T 9D 01 11 DB 0F 21 C9 3F +T 9E 01 01 DB 0F 11 C9 3F R 00 00 00 00 -T A3 01 +T A4 01 R 00 00 00 00 -T A3 01 E5 D5 DD 6E F6 DD 66 F7 E5 DD 6E F4 DD 66 +T A4 01 D5 C5 DD 6E F6 DD 66 F7 E5 DD 6E F4 DD 66 R 00 00 00 00 -T B1 01 F5 E5 CD 00 00 F1 F1 F1 F1 DD 75 FC DD 74 +T B2 01 F5 E5 CD 00 00 F1 F1 F1 F1 DD 75 FC DD 74 R 00 00 00 00 02 05 03 00 -T BF 01 FD DD 73 FE DD 72 FF +T C0 01 FD DD 73 FE DD 72 FF R 00 00 00 00 -T C6 01 +T C7 01 R 00 00 00 00 -T C6 01 DD 6E FC DD 66 FD DD 5E FE DD 56 FF +T C7 01 DD 6E FC DD 66 FD DD 5E FE DD 56 FF R 00 00 00 00 -T D2 01 +T D3 01 R 00 00 00 00 -T D2 01 DD F9 DD E1 C9 +T D3 01 DD F9 DD E1 C9 R 00 00 00 00 -sincoshf.rel/ 1458795420 2001 2501 100664 4840 ` + +sincoshf.rel/ 0 0 0 644 4840 ` XL2 H 9 areas A global symbols M sincoshf @@ -37393,7 +52056,7 @@ T 00 00 R 00 00 00 00 T 00 00 DD E5 DD 21 00 00 DD 39 21 EE FF 39 F9 21 R 00 00 00 00 -T 0E 00 09 00 39 EB 21 16 00 39 01 04 00 ED B0 21 +T 0E 00 05 00 39 EB 21 16 00 39 01 04 00 ED B0 21 R 00 00 00 00 T 1C 00 00 00 E5 21 00 00 E5 DD 6E 06 DD 66 07 E5 R 00 00 00 00 @@ -37405,7 +52068,7 @@ T 46 00 46 05 DD 5E 06 DD 36 EE 01 18 10 R 00 00 00 00 T 51 00 R 00 00 00 00 -T 51 00 DD 4E F7 DD 46 F8 DD 5E F9 DD 56 FA DD 36 +T 51 00 DD 4E F3 DD 46 F4 DD 5E F5 DD 56 F6 DD 36 R 00 00 00 00 T 5F 00 EE 00 R 00 00 00 00 @@ -37413,7 +52076,7 @@ T 61 00 R 00 00 00 00 T 61 00 C5 D5 21 80 3F E5 21 00 00 E5 D5 C5 CD R 00 00 00 00 -T 6E 00 00 00 F1 F1 F1 F1 DD 75 FF D1 C1 DD 7E FF +T 6E 00 00 00 F1 F1 F1 F1 DD 75 F7 D1 C1 DD 7E F7 R 00 00 00 00 02 02 03 00 T 7C 00 B7 20 07 DD CB 08 46 CA D1 01 R 00 00 00 00 00 0A 00 00 @@ -37421,7 +52084,7 @@ T 86 00 R 00 00 00 00 T 86 00 C5 D5 21 10 41 E5 21 00 00 E5 D5 C5 CD R 00 00 00 00 -T 93 00 00 00 F1 F1 F1 F1 DD 75 FF D1 C1 DD 7E FF +T 93 00 00 00 F1 F1 F1 F1 DD 75 F7 D1 C1 DD 7E F7 R 00 00 00 00 02 02 03 00 T A1 00 B7 CA 3A 01 21 31 3F E5 21 00 73 E5 D5 C5 R 00 00 00 00 00 04 00 00 @@ -37429,9 +52092,9 @@ T AF 00 CD 00 00 F1 F1 F1 F1 4D 44 C5 D5 21 33 42 R 00 00 00 00 02 03 00 00 T BD 00 E5 21 CF BD E5 D5 C5 CD 00 00 F1 F1 F1 F1 R 00 00 00 00 02 0A 03 00 -T CB 00 7D D1 C1 B7 28 19 21 22 00 22 00 00 DD 36 +T CB 00 D1 C1 7D B7 28 19 21 22 00 22 00 00 DD 36 R 00 00 00 00 02 0C 02 00 -T D9 00 FB FF DD 36 FC FF DD 36 FD 7F DD 36 FE 7F +T D9 00 F8 FF DD 36 F9 FF DD 36 FA 7F DD 36 FB 7F R 00 00 00 00 T E7 00 C3 BF 01 R 00 00 00 00 00 03 00 00 @@ -37441,13 +52104,13 @@ T EA 00 D5 C5 CD 00 00 F1 F1 4D 44 C5 D5 D5 C5 21 R 00 00 00 00 02 05 04 00 T F8 00 68 37 E5 21 97 08 E5 CD 00 00 F1 F1 F1 F1 R 00 00 00 00 02 0A 01 00 -T 06 01 DD 72 F6 DD 73 F5 DD 74 F4 DD 75 F3 D1 C1 +T 06 01 DD 72 FF DD 73 FE DD 74 FD DD 75 FC D1 C1 R 00 00 00 00 -T 14 01 DD 6E F5 DD 66 F6 E5 DD 6E F3 DD 66 F4 E5 +T 14 01 DD 6E FE DD 66 FF E5 DD 6E FC DD 66 FD E5 R 00 00 00 00 -T 22 01 D5 C5 CD 00 00 F1 F1 F1 F1 DD 75 FB DD 74 +T 22 01 D5 C5 CD 00 00 F1 F1 F1 F1 DD 75 F8 DD 74 R 00 00 00 00 02 05 07 00 -T 30 01 FC DD 73 FD DD 72 FE C3 BF 01 +T 30 01 F9 DD 73 FA DD 72 FB C3 BF 01 R 00 00 00 00 00 0A 00 00 T 3A 01 R 00 00 00 00 @@ -37455,11 +52118,11 @@ T 3A 01 D5 C5 CD 00 00 F1 F1 4D 44 C5 D5 D5 C5 21 R 00 00 00 00 02 05 04 00 T 48 01 80 3F E5 21 00 00 E5 CD 00 00 F1 F1 F1 F1 R 00 00 00 00 02 0A 08 00 -T 56 01 DD 72 F6 DD 73 F5 DD 74 F4 DD 75 F3 D1 C1 +T 56 01 DD 72 FF DD 73 FE DD 74 FD DD 75 FC D1 C1 R 00 00 00 00 -T 64 01 DD 7E F3 DD 77 EF DD 7E F4 DD 77 F0 DD 7E +T 64 01 DD 7E FC DD 77 EF DD 7E FD DD 77 F0 DD 7E R 00 00 00 00 -T 72 01 F5 DD 77 F1 DD 7E F6 DD 77 F2 DD CB 08 46 +T 72 01 FE DD 77 F1 DD 7E FF DD 77 F2 DD CB 08 46 R 00 00 00 00 T 80 01 20 08 DD 7E F2 EE 80 DD 77 F2 R 00 00 00 00 @@ -37471,21 +52134,21 @@ T 98 01 D5 C5 CD 00 00 F1 F1 F1 F1 EB E5 D5 21 R 00 00 00 00 02 05 07 00 T A5 01 00 3F E5 21 00 00 E5 CD 00 00 F1 F1 F1 F1 R 00 00 00 00 02 0A 01 00 -T B3 01 DD 75 FB DD 74 FC DD 73 FD DD 72 FE +T B3 01 DD 75 F8 DD 74 F9 DD 73 FA DD 72 FB R 00 00 00 00 T BF 01 R 00 00 00 00 -T BF 01 DD CB EE 46 CA 02 03 DD 7E FE EE 80 DD 77 +T BF 01 DD CB EE 46 CA 02 03 DD 7E FB EE 80 DD 77 R 00 00 00 00 00 07 00 00 -T CD 01 FE C3 02 03 +T CD 01 FB C3 02 03 R 00 00 00 00 00 04 00 00 T D1 01 R 00 00 00 00 T D1 01 21 80 39 E5 21 00 00 E5 D5 C5 CD 00 00 F1 R 00 00 00 00 02 0D 05 00 -T DF 01 F1 F1 F1 7D B7 28 11 21 0D 00 39 EB 21 +T DF 01 F1 F1 F1 7D B7 28 11 21 0A 00 39 EB 21 R 00 00 00 00 -T EC 01 09 00 39 01 04 00 ED B0 C3 02 03 +T EC 01 05 00 39 01 04 00 ED B0 C3 02 03 R 00 00 00 00 00 0B 00 00 T F7 01 R 00 00 00 00 @@ -37493,49 +52156,49 @@ T F7 01 DD 6E 06 DD 66 07 E5 DD 6E 04 DD 66 05 E5 R 00 00 00 00 T 05 02 DD 6E 06 DD 66 07 E5 DD 6E 04 DD 66 05 E5 R 00 00 00 00 -T 13 02 CD 00 00 F1 F1 F1 F1 DD 75 F3 DD 74 F4 DD +T 13 02 CD 00 00 F1 F1 F1 F1 DD 75 FC DD 74 FD DD R 00 00 00 00 02 03 01 00 -T 21 02 73 F5 DD 72 F6 DD 6E F5 DD 66 F6 E5 DD 6E +T 21 02 73 FE DD 72 FF DD 6E FE DD 66 FF E5 DD 6E R 00 00 00 00 -T 2F 02 F3 DD 66 F4 E5 DD 6E 06 DD 66 07 E5 DD 6E +T 2F 02 FC DD 66 FD E5 DD 6E 06 DD 66 07 E5 DD 6E R 00 00 00 00 T 3D 02 04 DD 66 05 E5 CD 00 00 F1 F1 F1 F1 DD 72 R 00 00 00 00 02 08 01 00 -T 4B 02 FA DD 73 F9 DD 74 F8 DD 75 F7 DD 6E F5 DD +T 4B 02 F6 DD 73 F5 DD 74 F4 DD 75 F3 DD 6E FE DD R 00 00 00 00 -T 59 02 66 F6 E5 DD 6E F3 DD 66 F4 E5 21 42 BE E5 +T 59 02 66 FF E5 DD 6E FC DD 66 FD E5 21 42 BE E5 R 00 00 00 00 T 67 02 21 EA E6 E5 CD 00 00 F1 F1 F1 F1 4D 44 21 R 00 00 00 00 02 07 01 00 T 75 02 E4 C0 E5 21 F0 69 E5 D5 C5 CD 00 00 F1 F1 R 00 00 00 00 02 0C 07 00 -T 83 02 F1 F1 EB E5 D5 DD 6E F9 DD 66 FA E5 DD 6E +T 83 02 F1 F1 EB E5 D5 DD 6E F5 DD 66 F6 E5 DD 6E R 00 00 00 00 -T 91 02 F7 DD 66 F8 E5 CD 00 00 F1 F1 F1 F1 DD 72 +T 91 02 F3 DD 66 F4 E5 CD 00 00 F1 F1 F1 F1 DD 72 R 00 00 00 00 02 08 01 00 -T 9F 02 FA DD 73 F9 DD 74 F8 DD 75 F7 21 2B C2 E5 +T 9F 02 F6 DD 73 F5 DD 74 F4 DD 75 F3 21 2B C2 E5 R 00 00 00 00 -T AD 02 21 93 4F E5 DD 6E F5 DD 66 F6 E5 DD 6E F3 +T AD 02 21 93 4F E5 DD 6E FE DD 66 FF E5 DD 6E FC R 00 00 00 00 -T BB 02 DD 66 F4 E5 CD 00 00 F1 F1 F1 F1 EB E5 D5 +T BB 02 DD 66 FD E5 CD 00 00 F1 F1 F1 F1 EB E5 D5 R 00 00 00 00 02 07 07 00 -T C9 02 DD 6E F9 DD 66 FA E5 DD 6E F7 DD 66 F8 E5 +T C9 02 DD 6E F5 DD 66 F6 E5 DD 6E F3 DD 66 F4 E5 R 00 00 00 00 T D7 02 CD 00 00 F1 F1 F1 F1 EB E5 D5 DD 6E 06 DD R 00 00 00 00 02 03 08 00 T E5 02 66 07 E5 DD 6E 04 DD 66 05 E5 CD 00 00 F1 R 00 00 00 00 02 0D 07 00 -T F3 02 F1 F1 F1 DD 75 FB DD 74 FC DD 73 FD DD 72 +T F3 02 F1 F1 F1 DD 75 F8 DD 74 F9 DD 73 FA DD 72 R 00 00 00 00 -T 01 03 FE +T 01 03 FB R 00 00 00 00 T 02 03 R 00 00 00 00 -T 02 03 DD 6E FB DD 66 FC DD 5E FD DD 56 FE DD F9 +T 02 03 DD 6E F8 DD 66 F9 DD 5E FA DD 56 FB DD F9 R 00 00 00 00 T 10 03 DD E1 C9 R 00 00 00 00 -sinhf.rel/ 1458795420 2001 2501 100664 583 ` +sinhf.rel/ 0 0 0 644 583 ` XL2 H 9 areas 3 global symbols M sinhf @@ -37561,7 +52224,7 @@ R 00 00 00 00 02 0C 01 00 T 1C 00 33 C9 R 00 00 00 00 -coshf.rel/ 1458795420 2001 2501 100664 586 ` +coshf.rel/ 0 0 0 644 586 ` XL2 H 9 areas 3 global symbols M coshf @@ -37586,7 +52249,7 @@ T 0E 00 66 03 E5 FD 6E 00 FD 66 01 E5 CD 00 00 F1 R 00 00 00 00 02 0D 01 00 T 1C 00 F1 33 C9 R 00 00 00 00 -tanhf.rel/ 1458795421 2001 2501 100664 3512 ` +tanhf.rel/ 0 0 0 644 3512 ` XL2 H 9 areas A global symbols M tanhf @@ -37618,15 +52281,15 @@ T 0E 00 6E 06 DD 66 07 E5 DD 6E 04 DD 66 05 E5 CD R 00 00 00 00 T 1C 00 00 00 F1 F1 4D 44 C5 D5 21 10 41 E5 21 R 00 00 00 00 02 02 07 00 -T 29 00 B0 2C E5 D5 C5 CD 00 00 F1 F1 F1 F1 7D D1 +T 29 00 B0 2C E5 D5 C5 CD 00 00 F1 F1 F1 F1 D1 C1 R 00 00 00 00 02 08 02 00 -T 37 00 C1 B7 28 09 01 00 00 11 80 3F C3 05 02 +T 37 00 7D B7 28 09 01 00 00 11 80 3F C3 05 02 R 00 00 00 00 00 0D 00 00 T 44 00 R 00 00 00 00 T 44 00 C5 D5 21 0C 3F E5 21 54 9F E5 D5 C5 CD R 00 00 00 00 -T 51 00 00 00 F1 F1 F1 F1 7D D1 C1 B7 28 5A D5 C5 +T 51 00 00 00 F1 F1 F1 F1 D1 C1 7D B7 28 5A D5 C5 R 00 00 00 00 02 02 02 00 T 5F 00 D5 C5 CD 00 00 F1 F1 F1 F1 D5 E5 CD 00 00 R 00 00 00 00 02 05 06 00 02 0E 03 00 @@ -37646,7 +52309,7 @@ T B7 00 R 00 00 00 00 T B7 00 C5 D5 21 80 39 E5 21 00 00 E5 D5 C5 CD R 00 00 00 00 -T C4 00 00 00 F1 F1 F1 F1 7D D1 C1 B7 C2 05 02 C5 +T C4 00 00 00 F1 F1 F1 F1 D1 C1 7D B7 C2 05 02 C5 R 00 00 00 00 02 02 04 00 00 0D 00 00 T D2 00 D5 D5 C5 D5 C5 CD 00 00 F1 F1 F1 F1 DD 72 R 00 00 00 00 02 08 01 00 @@ -37698,13 +52361,13 @@ T 05 02 C5 D5 21 00 00 E5 21 00 00 E5 DD 6E 06 DD R 00 00 00 00 T 13 02 66 07 E5 DD 6E 04 DD 66 05 E5 CD 00 00 F1 R 00 00 00 00 02 0D 04 00 -T 21 02 F1 F1 F1 7D D1 C1 B7 28 04 7A EE 80 57 +T 21 02 F1 F1 F1 D1 C1 7D B7 28 04 7A EE 80 57 R 00 00 00 00 T 2E 02 R 00 00 00 00 T 2E 02 69 60 DD F9 DD E1 C9 R 00 00 00 00 -floorf.rel/ 1458795421 2001 2501 100664 1642 ` +floorf.rel/ 0 0 0 644 1642 ` XL2 H 9 areas 5 global symbols M floorf @@ -37755,11 +52418,11 @@ T 94 00 DD 36 FF 00 R 00 00 00 00 T 98 00 R 00 00 00 00 -T 98 00 DD 6E FF DD 7E FF 17 9F 67 5F 57 DD 7E F7 +T 98 00 DD 4E FF DD 7E FF 17 9F 47 5F 57 DD 7E F7 R 00 00 00 00 -T A6 00 85 6F DD 7E F8 8C 67 DD 7E F9 8B 5F DD 7E +T A6 00 81 4F DD 7E F8 88 47 DD 7E F9 8B 5F DD 7E R 00 00 00 00 -T B4 00 FA 8A 57 D5 E5 CD 00 00 F1 F1 18 0C +T B4 00 FA 8A 57 D5 C5 CD 00 00 F1 F1 18 0C R 00 00 00 00 02 08 00 00 T C0 00 R 00 00 00 00 @@ -37769,7 +52432,7 @@ T CC 00 R 00 00 00 00 T CC 00 DD F9 DD E1 C9 R 00 00 00 00 -ceilf.rel/ 1458795421 2001 2501 100664 1512 ` +ceilf.rel/ 0 0 0 644 1512 ` XL2 H 9 areas 5 global symbols M ceilf @@ -37820,17 +52483,17 @@ T 8F 00 DD 36 FC 00 R 00 00 00 00 T 93 00 R 00 00 00 00 -T 93 00 DD 6E FC 26 00 7C 17 9F 5F 57 DD 7E F8 85 +T 93 00 DD 4E FC 06 00 78 17 9F 5F 57 DD 7E F8 81 R 00 00 00 00 -T A1 00 6F DD 7E F9 8C 67 DD 7E FA 8B 5F DD 7E FB +T A1 00 4F DD 7E F9 88 47 DD 7E FA 8B 5F DD 7E FB R 00 00 00 00 -T AF 00 8A 57 D5 E5 CD 00 00 F1 F1 +T AF 00 8A 57 D5 C5 CD 00 00 F1 F1 R 00 00 00 00 02 07 00 00 T B8 00 R 00 00 00 00 T B8 00 DD F9 DD E1 C9 R 00 00 00 00 -modff.rel/ 1458795421 2001 2501 100664 857 ` +modff.rel/ 0 0 0 644 857 ` XL2 H 9 areas 5 global symbols M modff @@ -37864,7 +52527,7 @@ R 00 00 00 00 02 0E 00 00 T 46 00 F1 F1 F1 F1 DD E1 C9 R 00 00 00 00 -errno.rel/ 1458795421 2001 2501 100664 416 ` +errno.rel/ 0 0 0 644 416 ` XL2 H 9 areas 2 global symbols M errno @@ -37884,7 +52547,74 @@ T 00 00 R 00 00 01 00 T 00 00 R 00 00 01 00 -_divslong.rel/ 1458795421 2001 2501 100664 1444 ` +isinf.rel/ 0 0 0 644 827 ` +XL2 +H 9 areas 2 global symbols +M isinf +O -mz80 +S .__.ABS. Def0000 +A _CODE size 38 flags 0 addr 0 +S _isinf Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 DD E5 21 04 00 39 4E 23 46 23 5E 23 56 79 +R 00 00 00 00 +T 0E 00 B7 20 0D B0 20 0A 7B D6 80 20 05 7A D6 7F +R 00 00 00 00 +T 1C 00 28 13 +R 00 00 00 00 +T 1E 00 +R 00 00 00 00 +T 1E 00 79 B7 20 0B B0 20 08 7B D6 80 20 03 14 28 +R 00 00 00 00 +T 2C 00 04 +R 00 00 00 00 +T 2D 00 +R 00 00 00 00 +T 2D 00 2E 00 18 02 +R 00 00 00 00 +T 31 00 +R 00 00 00 00 +T 31 00 2E 01 +R 00 00 00 00 +T 33 00 +R 00 00 00 00 +T 33 00 26 00 DD E1 C9 +R 00 00 00 00 + +isnan.rel/ 0 0 0 644 560 ` +XL2 +H 9 areas 2 global symbols +M isnan +O -mz80 +S .__.ABS. Def0000 +A _CODE size 21 flags 0 addr 0 +S _isnan Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 DD E5 21 04 00 39 4E 23 46 23 5E 23 56 CB +R 00 00 00 00 +T 0E 00 BA AF B9 98 3E 80 9B 3E 7F 9A 3E 00 17 6F +R 00 00 00 00 +T 1C 00 26 00 DD E1 C9 +R 00 00 00 00 +_divslong.rel/ 0 0 0 644 1444 ` XL2 H 9 areas 3 global symbols M _divslong @@ -37905,7 +52635,7 @@ T 00 00 R 00 00 04 00 T 00 00 DD E5 DD 21 00 00 DD 39 21 FA FF 39 F9 DD R 00 00 04 00 -T 0E 00 7E 07 07 E6 01 DD 77 FE B7 28 19 AF DD 96 +T 0E 00 7E 07 07 E6 01 DD 77 FB B7 28 19 AF DD 96 R 00 00 04 00 T 1C 00 04 4F 3E 00 DD 9E 05 47 3E 00 DD 9E 06 5F R 00 00 04 00 @@ -37917,27 +52647,27 @@ T 32 00 DD 4E 04 DD 46 05 DD 5E 06 DD 56 07 R 00 00 04 00 T 3E 00 R 00 00 04 00 -T 3E 00 DD 7E 0B 07 E6 01 DD 77 FF B7 28 21 AF DD +T 3E 00 DD 7E 0B 07 E6 01 DD 77 FA B7 28 21 AF DD R 00 00 04 00 -T 4C 00 96 08 DD 77 FA 3E 00 DD 9E 09 DD 77 FB 3E +T 4C 00 96 08 DD 77 FC 3E 00 DD 9E 09 DD 77 FD 3E R 00 00 04 00 -T 5A 00 00 DD 9E 0A DD 77 FC 3E 00 DD 9E 0B DD 77 +T 5A 00 00 DD 9E 0A DD 77 FE 3E 00 DD 9E 0B DD 77 R 00 00 04 00 -T 68 00 FD 18 18 +T 68 00 FF 18 18 R 00 00 04 00 T 6B 00 R 00 00 04 00 -T 6B 00 DD 7E 08 DD 77 FA DD 7E 09 DD 77 FB DD 7E +T 6B 00 DD 7E 08 DD 77 FC DD 7E 09 DD 77 FD DD 7E R 00 00 04 00 -T 79 00 0A DD 77 FC DD 7E 0B DD 77 FD +T 79 00 0A DD 77 FE DD 7E 0B DD 77 FF R 00 00 04 00 T 83 00 R 00 00 04 00 -T 83 00 DD 6E FC DD 66 FD E5 DD 6E FA DD 66 FB E5 +T 83 00 DD 6E FE DD 66 FF E5 DD 6E FC DD 66 FD E5 R 00 00 04 00 -T 91 00 D5 C5 CD 00 00 F1 F1 F1 F1 DD 7E FE DD AE +T 91 00 D5 C5 CD 00 00 F1 F1 F1 F1 DD 7E FB DD AE R 00 00 04 00 02 05 01 00 -T 9F 00 FF 28 0F AF 95 6F 3E 00 9C 67 3E 00 9B 5F +T 9F 00 FA 28 0F AF 95 6F 3E 00 9C 67 3E 00 9B 5F R 00 00 04 00 T AD 00 3E 00 9A 57 R 00 00 04 00 @@ -37945,7 +52675,7 @@ T B1 00 R 00 00 04 00 T B1 00 DD F9 DD E1 C9 R 00 00 04 00 -_modslong.rel/ 1458795421 2001 2501 100664 1368 ` +_modslong.rel/ 0 0 0 644 1368 ` XL2 H 9 areas 3 global symbols M _modslong @@ -37966,33 +52696,33 @@ T 00 00 R 00 00 04 00 T 00 00 DD E5 DD 21 00 00 DD 39 F5 F5 3B DD 7E 07 R 00 00 04 00 -T 0E 00 07 E6 01 DD 77 FB B7 28 19 AF DD 96 04 6F +T 0E 00 07 E6 01 DD 77 FB B7 28 19 AF DD 96 04 4F R 00 00 04 00 -T 1C 00 3E 00 DD 9E 05 67 3E 00 DD 9E 06 5F 3E 00 +T 1C 00 3E 00 DD 9E 05 47 3E 00 DD 9E 06 5F 3E 00 R 00 00 04 00 T 2A 00 DD 9E 07 57 18 0C R 00 00 04 00 T 30 00 R 00 00 04 00 -T 30 00 DD 6E 04 DD 66 05 DD 5E 06 DD 56 07 +T 30 00 DD 4E 04 DD 46 05 DD 5E 06 DD 56 07 R 00 00 04 00 T 3C 00 R 00 00 04 00 -T 3C 00 DD 75 FC DD 74 FD DD 73 FE DD 72 FF DD CB +T 3C 00 DD 71 FC DD 70 FD DD 73 FE DD 72 FF DD CB R 00 00 04 00 T 4A 00 0B 7E 28 19 AF DD 96 08 4F 3E 00 DD 9E 09 R 00 00 04 00 -T 58 00 47 3E 00 DD 9E 0A 6F 3E 00 DD 9E 0B 67 18 +T 58 00 47 3E 00 DD 9E 0A 5F 3E 00 DD 9E 0B 57 18 R 00 00 04 00 T 66 00 0C R 00 00 04 00 T 67 00 R 00 00 04 00 -T 67 00 DD 4E 08 DD 46 09 DD 6E 0A DD 66 0B +T 67 00 DD 4E 08 DD 46 09 DD 5E 0A DD 56 0B R 00 00 04 00 T 73 00 R 00 00 04 00 -T 73 00 E5 C5 DD 6E FE DD 66 FF E5 DD 6E FC DD 66 +T 73 00 D5 C5 DD 6E FE DD 66 FF E5 DD 6E FC DD 66 R 00 00 04 00 T 81 00 FD E5 CD 00 00 F1 F1 F1 F1 DD 7E FB B7 28 R 00 00 04 00 02 05 01 00 @@ -38004,7 +52734,7 @@ T 9F 00 R 00 00 04 00 T 9F 00 DD F9 DD E1 C9 R 00 00 04 00 -_modulong.rel/ 1458795421 2001 2501 100664 1432 ` +_modulong.rel/ 0 0 0 644 1383 ` XL2 H 9 areas 2 global symbols M _modulong @@ -38014,7 +52744,7 @@ A _CODE size 0 flags 0 addr 0 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 A _DABS size 0 flags 8 addr 0 -A _HOME size BD flags 0 addr 0 +A _HOME size B4 flags 0 addr 0 S __modulong Def0000 A _GSINIT size 0 flags 0 addr 0 A _GSFINAL size 0 flags 0 addr 0 @@ -38022,49 +52752,48 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 04 00 -T 00 00 DD E5 DD 21 00 00 DD 39 11 00 00 +T 00 00 DD E5 DD 21 00 00 DD 39 01 00 00 R 00 00 04 00 T 0B 00 R 00 00 04 00 -T 0B 00 DD 7E 0B CB 07 E6 01 20 44 F5 F1 DD CB 08 +T 0B 00 DD 7E 0B 07 38 40 DD CB 08 26 DD CB 09 16 R 00 00 04 00 -T 19 00 26 DD CB 09 16 DD CB 0A 16 DD CB 0B 16 DD +T 19 00 DD CB 0A 16 DD CB 0B 16 DD 7E 04 DD 96 08 R 00 00 04 00 -T 27 00 7E 04 DD 96 08 DD 7E 05 DD 9E 09 DD 7E 06 +T 27 00 DD 7E 05 DD 9E 09 DD 7E 06 DD 9E 0A DD 7E R 00 00 04 00 -T 35 00 DD 9E 0A DD 7E 07 DD 9E 0B 30 14 F5 F1 DD +T 35 00 07 DD 9E 0B 30 12 DD CB 0B 3E DD CB 0A 1E R 00 00 04 00 -T 43 00 CB 0B 3E DD CB 0A 1E DD CB 09 1E DD CB 08 +T 43 00 DD CB 09 1E DD CB 08 1E 18 04 R 00 00 04 00 -T 51 00 1E 18 04 +T 4D 00 R 00 00 04 00 -T 54 00 +T 4D 00 04 48 18 BA R 00 00 04 00 -T 54 00 1C 53 18 B3 +T 51 00 R 00 00 04 00 -T 58 00 +T 51 00 R 00 00 04 00 -T 58 00 +T 51 00 DD 7E 04 DD 96 08 DD 7E 05 DD 9E 09 DD 7E R 00 00 04 00 -T 58 00 DD 7E 04 DD 96 08 DD 7E 05 DD 9E 09 DD 7E +T 5F 00 06 DD 9E 0A DD 7E 07 DD 9E 0B 38 24 DD 7E R 00 00 04 00 -T 66 00 06 DD 9E 0A DD 7E 07 DD 9E 0B 38 24 DD 7E +T 6D 00 04 DD 96 08 DD 77 04 DD 7E 05 DD 9E 09 DD R 00 00 04 00 -T 74 00 04 DD 96 08 DD 77 04 DD 7E 05 DD 9E 09 DD +T 7B 00 77 05 DD 7E 06 DD 9E 0A DD 77 06 DD 7E 07 R 00 00 04 00 -T 82 00 77 05 DD 7E 06 DD 9E 0A DD 77 06 DD 7E 07 +T 89 00 DD 9E 0B DD 77 07 R 00 00 04 00 -T 90 00 DD 9E 0B DD 77 07 +T 8F 00 R 00 00 04 00 -T 96 00 +T 8F 00 DD CB 0B 3E DD CB 0A 1E DD CB 09 1E DD CB R 00 00 04 00 -T 96 00 F5 F1 DD CB 0B 3E DD CB 0A 1E DD CB 09 1E +T 9D 00 08 1E 41 0D 78 B7 20 AC DD 6E 04 DD 66 05 R 00 00 04 00 -T A4 00 DD CB 08 1E 62 15 7C B7 20 AA DD 6E 04 DD +T AB 00 DD 5E 06 DD 56 07 DD E1 C9 R 00 00 04 00 -T B2 00 66 05 DD 5E 06 DD 56 07 DD E1 C9 -R 00 00 04 00 -_divulong.rel/ 1458795421 2001 2501 100664 1073 ` + +_divulong.rel/ 0 0 0 644 1067 ` XL2 H 9 areas 2 global symbols M _divulong @@ -38074,7 +52803,7 @@ A _CODE size 0 flags 0 addr 0 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 A _DABS size 0 flags 8 addr 0 -A _HOME size 80 flags 0 addr 0 +A _HOME size 7E flags 0 addr 0 S __divulong Def0000 A _GSINIT size 0 flags 0 addr 0 A _GSFINAL size 0 flags 0 addr 0 @@ -38088,28 +52817,28 @@ T 0D 00 00 00 DD 36 FF 20 R 00 00 04 00 T 13 00 R 00 00 04 00 -T 13 00 DD 7E 07 CB 07 E6 01 67 F5 F1 DD CB 04 26 +T 13 00 DD 7E 07 CB 07 E6 01 6F DD CB 04 26 DD CB R 00 00 04 00 -T 21 00 DD CB 05 16 DD CB 06 16 DD CB 07 16 CB 20 +T 21 00 05 16 DD CB 06 16 DD CB 07 16 F5 F1 CB 21 R 00 00 04 00 -T 2F 00 CB 11 CB 13 CB 12 CB 44 28 02 CB C0 +T 2F 00 CB 10 CB 13 CB 12 CB 45 28 02 CB C1 R 00 00 04 00 T 3B 00 R 00 00 04 00 -T 3B 00 78 DD 96 08 79 DD 9E 09 7B DD 9E 0A 7A DD +T 3B 00 79 DD 96 08 78 DD 9E 09 7B DD 9E 0A 7A DD R 00 00 04 00 -T 49 00 9E 0B 38 18 78 DD 96 08 47 79 DD 9E 09 4F +T 49 00 9E 0B 38 18 79 DD 96 08 4F 78 DD 9E 09 47 R 00 00 04 00 T 57 00 7B DD 9E 0A 5F 7A DD 9E 0B 57 DD CB 04 C6 R 00 00 04 00 T 65 00 R 00 00 04 00 -T 65 00 DD 7E FF C6 FF DD 77 FF B7 20 A3 DD 6E 04 +T 65 00 DD 35 FF DD 7E FF B7 20 A5 DD 6E 04 DD 66 R 00 00 04 00 -T 73 00 DD 66 05 DD 5E 06 DD 56 07 33 DD E1 C9 +T 73 00 05 DD 5E 06 DD 56 07 33 DD E1 C9 R 00 00 04 00 -_mullong.rel/ 1458795422 2001 2501 100664 2489 ` +_mullong.rel/ 0 0 0 644 2523 ` XL2 H 9 areas 3 global symbols M _mullong @@ -38120,7 +52849,7 @@ A _CODE size 0 flags 0 addr 0 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 A _DABS size 0 flags 8 addr 0 -A _HOME size 184 flags 0 addr 0 +A _HOME size 188 flags 0 addr 0 S __mullong Def0000 A _GSINIT size 0 flags 0 addr 0 A _GSFINAL size 0 flags 0 addr 0 @@ -38130,86 +52859,88 @@ T 00 00 R 00 00 04 00 T 00 00 DD E5 DD 21 00 00 DD 39 21 FA FF 39 F9 21 R 00 00 04 00 -T 0E 00 0A 00 39 4D 44 23 23 E3 69 60 23 23 5E 23 +T 0E 00 0A 00 39 EB 4B 42 03 03 DD 71 FC DD 70 FD R 00 00 04 00 -T 1C 00 56 21 0E 00 39 DD 75 FE DD 74 FF DD 6E FE +T 1C 00 6B 62 23 23 4E 23 46 21 0E 00 39 DD 75 FE R 00 00 04 00 -T 2A 00 DD 66 FF 7E 23 66 6F C5 E5 D5 CD 00 00 F1 -R 00 00 04 00 02 0D 00 00 -T 38 00 F1 55 5C C1 E1 E5 72 23 73 69 60 23 23 E3 +T 2A 00 DD 74 FF DD 6E FE DD 66 FF 7E 23 66 6F D5 R 00 00 04 00 -T 46 00 69 60 23 23 7E DD 77 FC 23 7E DD 77 FD DD +T 38 00 E5 C5 CD 00 00 F1 F1 4D 44 D1 DD 6E FC DD +R 00 00 04 00 02 05 00 00 +T 46 00 66 FD 71 23 70 4B 42 03 03 DD 71 FC DD 70 R 00 00 04 00 -T 54 00 6E FE DD 66 FF 23 23 5E 23 56 69 60 7E 23 +T 54 00 FD 6B 62 23 23 7E DD 77 FA 23 7E DD 77 FB R 00 00 04 00 -T 62 00 66 6F C5 E5 D5 CD 00 00 F1 F1 C1 DD 7E FC -R 00 00 04 00 02 08 00 00 -T 70 00 85 57 DD 7E FD 8C 5F E1 E5 72 23 73 69 60 +T 62 00 DD 6E FE DD 66 FF 23 23 4E 23 46 6B 62 7E R 00 00 04 00 -T 7E 00 23 23 DD 75 FC DD 74 FD 69 60 23 23 5E 23 +T 70 00 23 66 6F D5 E5 C5 CD 00 00 F1 F1 D1 DD 7E +R 00 00 04 00 02 09 00 00 +T 7E 00 FA 85 4F DD 7E FB 8C 47 DD 6E FC DD 66 FD R 00 00 04 00 -T 8C 00 56 69 60 23 7E DD 77 FA DD 6E FE DD 66 FF +T 8C 00 71 23 70 4B 42 03 03 33 33 C5 6B 62 23 23 R 00 00 04 00 -T 9A 00 23 66 D5 C5 DD 5E FA 2E 00 55 06 08 +T 9A 00 4E 23 46 6B 62 23 7E DD 77 FC DD 6E FE DD R 00 00 04 00 -T A6 00 +T A8 00 66 FF 23 66 D5 C5 DD 5E FC 2E 00 55 06 08 R 00 00 04 00 -T A6 00 29 30 01 19 +T B6 00 R 00 00 04 00 -T AA 00 +T B6 00 29 30 01 19 R 00 00 04 00 -T AA 00 10 FA C1 D1 19 EB DD 6E FC DD 66 FD 73 23 +T BA 00 R 00 00 04 00 -T B8 00 72 DD 6E FE DD 66 FF 5E 69 60 23 66 C5 2E +T BA 00 10 FA C1 D1 09 4D 44 E1 E5 71 23 70 DD 6E R 00 00 04 00 -T C6 00 00 55 06 08 +T C8 00 FE DD 66 FF 4E 6B 62 23 66 D5 59 2E 00 55 R 00 00 04 00 -T CA 00 +T D6 00 06 08 R 00 00 04 00 -T CA 00 29 30 01 19 +T D8 00 R 00 00 04 00 -T CE 00 +T D8 00 29 30 01 19 R 00 00 04 00 -T CE 00 10 FA C1 EB DD 6E FE DD 66 FF 23 E5 FD E1 +T DC 00 R 00 00 04 00 -T DC 00 69 60 7E DD 77 FC DD 6E FE DD 66 FF 23 7E +T DC 00 10 FA D1 4D 44 DD 6E FE DD 66 FF 23 E5 FD R 00 00 04 00 -T EA 00 D5 C5 5F DD 66 FC 2E 00 55 06 08 +T EA 00 E1 6B 62 7E DD 77 FA DD 6E FE DD 66 FF 23 R 00 00 04 00 -T F5 00 +T F8 00 6E D5 C5 5D DD 66 FA 2E 00 55 06 08 R 00 00 04 00 -T F5 00 29 30 01 19 +T 04 01 R 00 00 04 00 -T F9 00 +T 04 01 29 30 01 19 R 00 00 04 00 -T F9 00 10 FA C1 D1 FD 75 00 FD 74 01 DD 6E FE DD +T 08 01 R 00 00 04 00 -T 07 01 66 FF 23 23 23 DD 75 FC DD 74 FD DD 6E FE +T 08 01 10 FA C1 D1 FD 75 00 FD 74 01 DD 6E FE DD R 00 00 04 00 -T 15 01 DD 66 FF 23 E5 FD E1 DD 6E FE DD 66 FF 23 +T 16 01 66 FF 23 23 23 E3 DD 6E FE DD 66 FF 23 E5 R 00 00 04 00 -T 23 01 7E 23 66 6F 19 FD 75 00 FD 74 01 BF ED 52 +T 24 01 FD E1 DD 6E FE DD 66 FF 23 7E 23 66 6F 09 R 00 00 04 00 -T 31 01 3E 00 17 DD 6E FC DD 66 FD 77 59 50 0A 4F +T 32 01 FD 75 00 FD 74 01 BF ED 42 3E 00 17 E1 E5 R 00 00 04 00 -T 3F 01 DD 6E FE DD 66 FF 66 D5 59 2E 00 55 06 08 +T 40 01 77 4B 42 1A 5F DD 6E FE DD 66 FF 66 C5 2E R 00 00 04 00 -T 4D 01 +T 4E 01 00 55 06 08 R 00 00 04 00 -T 4D 01 29 30 01 19 +T 52 01 R 00 00 04 00 -T 51 01 +T 52 01 29 30 01 19 R 00 00 04 00 -T 51 01 10 FA D1 4D 44 79 12 13 78 12 DD 6E FE DD +T 56 01 R 00 00 04 00 -T 5F 01 66 FF 36 00 DD 7E 04 DD 86 08 6F DD 7E 05 +T 56 01 10 FA C1 EB 7B 02 03 7A 02 DD 4E FE DD 46 R 00 00 04 00 -T 6D 01 DD 8E 09 67 DD 7E 06 DD 8E 0A 5F DD 7E 07 +T 64 01 FF AF 02 DD 7E 04 DD 86 08 6F DD 7E 05 DD R 00 00 04 00 -T 7B 01 DD 8E 0B 57 DD F9 DD E1 C9 +T 72 01 8E 09 67 DD 7E 06 DD 8E 0A 5F DD 7E 07 DD +R 00 00 04 00 +T 80 01 8E 0B 57 DD F9 DD E1 C9 R 00 00 04 00 -/40 1458795423 2001 2501 100664 2953 ` +/40 0 0 0 644 2935 ` XL2 H 9 areas 2 global symbols M _mullonglong @@ -38219,7 +52950,7 @@ A _CODE size 0 flags 0 addr 0 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 A _DABS size 0 flags 8 addr 0 -A _HOME size 1D5 flags 0 addr 0 +A _HOME size 1CF flags 0 addr 0 S __mullonglong Def0000 A _GSINIT size 0 flags 0 addr 0 A _GSFINAL size 0 flags 0 addr 0 @@ -38235,100 +52966,100 @@ T 1C 00 F2 DD 77 F3 DD 77 F4 DD 77 F5 0E 00 R 00 00 04 00 T 28 00 R 00 00 04 00 -T 28 00 59 16 00 6B 62 29 29 29 F5 DD 7E 06 DD 77 +T 28 00 59 16 00 6B 62 29 29 29 DD 7E 06 DD 77 F8 R 00 00 04 00 -T 36 00 F8 DD 7E 07 DD 77 F9 DD 7E 08 DD 77 FA DD +T 36 00 DD 7E 07 DD 77 F9 DD 7E 08 DD 77 FA DD 7E R 00 00 04 00 -T 44 00 7E 09 DD 77 FB DD 7E 0A DD 77 FC DD 7E 0B +T 44 00 09 DD 77 FB DD 7E 0A DD 77 FC DD 7E 0B DD R 00 00 04 00 -T 52 00 DD 77 FD DD 7E 0C DD 77 FE DD 7E 0D DD 77 +T 52 00 77 FD DD 7E 0C DD 77 FE DD 7E 0D DD 77 FF R 00 00 04 00 -T 60 00 FF F1 2C 18 20 +T 60 00 2C 18 20 R 00 00 04 00 -T 65 00 +T 63 00 R 00 00 04 00 -T 65 00 DD CB FF 2E DD CB FE 1E DD CB FD 1E DD CB +T 63 00 DD CB FF 2E DD CB FE 1E DD CB FD 1E DD CB R 00 00 04 00 -T 73 00 FC 1E DD CB FB 1E DD CB FA 1E DD CB F9 1E +T 71 00 FC 1E DD CB FB 1E DD CB FA 1E DD CB F9 1E R 00 00 04 00 -T 81 00 DD CB F8 1E +T 7F 00 DD CB F8 1E R 00 00 04 00 -T 85 00 +T 83 00 R 00 00 04 00 -T 85 00 2D 20 DD DD 46 F8 DD 36 ED 00 +T 83 00 2D 20 DD DD 46 F8 DD 36 ED 00 R 00 00 04 00 -T 8F 00 +T 8D 00 R 00 00 04 00 -T 8F 00 DD 6E ED 26 00 7D 83 DD 77 F6 7C 8A DD 77 +T 8D 00 DD 6E ED 26 00 7D 83 DD 77 F6 7C 8A DD 77 R 00 00 04 00 -T 9D 00 F7 DD 7E F6 D6 08 DD 7E F7 17 3F 1F DE 80 +T 9B 00 F7 DD 7E F6 D6 08 DD 7E F7 17 3F 1F DE 80 R 00 00 04 00 -T AB 00 D2 B9 01 29 29 29 F5 DD 7E 0E DD 77 F8 DD +T A9 00 D2 B3 01 29 29 29 DD 7E 0E DD 77 F8 DD 7E R 00 00 04 00 00 03 04 00 -T B9 00 7E 0F DD 77 F9 DD 7E 10 DD 77 FA DD 7E 11 +T B7 00 0F DD 77 F9 DD 7E 10 DD 77 FA DD 7E 11 DD R 00 00 04 00 -T C7 00 DD 77 FB DD 7E 12 DD 77 FC DD 7E 13 DD 77 +T C5 00 77 FB DD 7E 12 DD 77 FC DD 7E 13 DD 77 FD R 00 00 04 00 -T D5 00 FD DD 7E 14 DD 77 FE DD 7E 15 DD 77 FF F1 +T D3 00 DD 7E 14 DD 77 FE DD 7E 15 DD 77 FF 2C 18 R 00 00 04 00 -T E3 00 2C 18 20 +T E1 00 20 R 00 00 04 00 -T E6 00 +T E2 00 R 00 00 04 00 -T E6 00 DD CB FF 2E DD CB FE 1E DD CB FD 1E DD CB +T E2 00 DD CB FF 2E DD CB FE 1E DD CB FD 1E DD CB R 00 00 04 00 -T F4 00 FC 1E DD CB FB 1E DD CB FA 1E DD CB F9 1E +T F0 00 FC 1E DD CB FB 1E DD CB FA 1E DD CB F9 1E R 00 00 04 00 -T 02 01 DD CB F8 1E +T FE 00 DD CB F8 1E R 00 00 04 00 -T 06 01 +T 02 01 R 00 00 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00 -T 10 01 DD 96 E8 DD 77 F0 3E 00 DD 9E E9 DD 77 F1 +T 11 01 3E 00 DD 9E E9 DD 77 F1 3E 00 DD 9E EA DD R 00 00 04 00 -T 1E 01 3E 00 DD 9E EA DD 77 F2 3E 00 DD 9E EB DD +T 1F 01 77 F2 3E 00 DD 9E EB DD 77 F3 3E 00 DD 9E R 00 00 04 00 -T 2C 01 77 F3 3E 00 DD 9E EC DD 77 F4 3E 00 DD 9E +T 2D 01 EC DD 77 F4 3E 00 DD 9E ED DD 77 F5 3E 00 R 00 00 04 00 -T 3A 01 ED DD 77 F5 3E 00 DD 9E EE DD 77 F6 3E 00 +T 3B 01 DD 9E EE DD 77 F6 3E 00 DD 9E EF DD 77 F7 R 00 00 04 00 -T 48 01 DD 9E EF DD 77 F7 18 0E +T 49 01 18 0E R 00 00 04 00 -T 50 01 +T 4B 01 R 00 00 04 00 -T 50 01 21 08 00 39 EB 21 00 00 39 01 08 00 ED B0 +T 4B 01 21 08 00 39 EB 21 00 00 39 01 08 00 ED B0 R 00 00 04 00 -T 5E 01 +T 59 01 R 00 00 04 00 -T 5E 01 21 1C 00 39 5E 23 56 21 08 00 39 01 08 00 +T 59 01 21 1C 00 39 5E 23 56 21 08 00 39 01 08 00 R 00 00 04 00 -T 6C 01 ED B0 DD F9 DD E1 C9 +T 67 01 ED B0 DD F9 DD E1 C9 R 00 00 04 00 -/115 1458795423 2001 2501 100664 2114 ` + +/115 0 0 0 644 2050 ` XL2 H 9 areas 2 global symbols M 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Def0000 -A _CODE size 2A flags 0 addr 0 +A _CODE size 24 flags 0 addr 0 S _isalpha Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -38696,34 +53427,34 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 3B FD 21 03 00 FD 39 FD 6E 00 7D D6 41 38 +T 00 00 3B 21 03 00 39 4E 79 D6 41 38 05 3E 5A 91 R 00 00 00 00 -T 0E 00 05 3E 5A 95 30 0E +T 0E 00 30 0E R 00 00 00 00 -T 14 00 +T 10 00 R 00 00 00 00 -T 14 00 7D D6 61 38 05 3E 7A 95 30 04 +T 10 00 79 D6 61 38 05 3E 7A 91 30 04 +R 00 00 00 00 +T 1A 00 +R 00 00 00 00 +T 1A 00 2E 00 18 02 R 00 00 00 00 T 1E 00 R 00 00 00 00 -T 1E 00 3E 00 18 02 +T 1E 00 2E 01 R 00 00 00 00 -T 22 00 +T 20 00 R 00 00 00 00 -T 22 00 3E 01 -R 00 00 00 00 -T 24 00 -R 00 00 00 00 -T 24 00 6F 17 9F 67 33 C9 +T 20 00 26 00 33 C9 R 00 00 00 00 -isblank.rel/ 1458795423 2001 2501 100664 603 ` +isblank.rel/ 0 0 0 644 597 ` XL2 H 9 areas 2 global symbols M isblank O -mz80 S .__.ABS. Def0000 -A _CODE size 18 flags 0 addr 0 +A _CODE size 16 flags 0 addr 0 S _isblank Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -38735,26 +53466,26 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 21 02 00 39 7E FE 20 28 08 D6 09 28 04 3E +T 00 00 21 02 00 39 7E FE 20 28 08 D6 09 28 04 2E R 00 00 00 00 T 0E 00 00 18 02 R 00 00 00 00 T 11 00 R 00 00 00 00 -T 11 00 3E 01 +T 11 00 2E 01 R 00 00 00 00 T 13 00 R 00 00 00 00 -T 13 00 6F 17 9F 67 C9 +T 13 00 26 00 C9 R 00 00 00 00 -iscntrl.rel/ 1458795423 2001 2501 100664 732 ` +iscntrl.rel/ 0 0 0 644 726 ` XL2 H 9 areas 2 global symbols M iscntrl O -mz80 S .__.ABS. Def0000 -A _CODE size 2D flags 0 addr 0 +A _CODE size 2B flags 0 addr 0 S _iscntrl Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -38774,23 +53505,23 @@ T 1C 00 FD 7E 01 B7 28 04 R 00 00 00 00 T 22 00 R 00 00 00 00 -T 22 00 3E 00 18 02 +T 22 00 2E 00 18 02 R 00 00 00 00 T 26 00 R 00 00 00 00 -T 26 00 3E 01 +T 26 00 2E 01 R 00 00 00 00 T 28 00 R 00 00 00 00 -T 28 00 6F 17 9F 67 C9 +T 28 00 26 00 C9 R 00 00 00 00 -isdigit.rel/ 1458795423 2001 2501 100664 671 ` +isdigit.rel/ 0 0 0 644 653 ` XL2 H 9 areas 2 global symbols M isdigit O -mz80 S .__.ABS. Def0000 -A _CODE size 20 flags 0 addr 0 +A _CODE size 1A flags 0 addr 0 S _isdigit Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -38802,30 +53533,30 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 3B FD 21 03 00 FD 39 FD 66 00 7C D6 30 38 +T 00 00 3B 21 03 00 39 4E 79 D6 30 38 05 3E 39 91 R 00 00 00 00 -T 0E 00 05 3E 39 94 30 04 +T 0E 00 30 04 +R 00 00 00 00 +T 10 00 +R 00 00 00 00 +T 10 00 2E 00 18 02 R 00 00 00 00 T 14 00 R 00 00 00 00 -T 14 00 3E 00 18 02 +T 14 00 2E 01 R 00 00 00 00 -T 18 00 +T 16 00 R 00 00 00 00 -T 18 00 3E 01 -R 00 00 00 00 -T 1A 00 -R 00 00 00 00 -T 1A 00 6F 17 9F 67 33 C9 +T 16 00 26 00 33 C9 R 00 00 00 00 -isgraph.rel/ 1458795423 2001 2501 100664 916 ` +isgraph.rel/ 0 0 0 644 910 ` XL2 H 9 areas 2 global symbols M isgraph O -mz80 S .__.ABS. Def0000 -A _CODE size 3D flags 0 addr 0 +A _CODE size 3B flags 0 addr 0 S _isgraph Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -38853,23 +53584,23 @@ T 2E 00 F2 35 00 R 00 00 00 00 00 03 00 00 T 31 00 R 00 00 00 00 -T 31 00 3E 00 18 02 +T 31 00 2E 00 18 02 R 00 00 00 00 T 35 00 R 00 00 00 00 -T 35 00 3E 01 +T 35 00 2E 01 R 00 00 00 00 T 37 00 R 00 00 00 00 -T 37 00 6F 17 9F 67 33 C9 +T 37 00 26 00 33 C9 R 00 00 00 00 -islower.rel/ 1458795423 2001 2501 100664 671 ` +islower.rel/ 0 0 0 644 653 ` XL2 H 9 areas 2 global symbols M islower O -mz80 S .__.ABS. Def0000 -A _CODE size 20 flags 0 addr 0 +A _CODE size 1A flags 0 addr 0 S _islower Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -38881,30 +53612,30 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 3B FD 21 03 00 FD 39 FD 66 00 7C D6 61 38 +T 00 00 3B 21 03 00 39 4E 79 D6 61 38 05 3E 7A 91 R 00 00 00 00 -T 0E 00 05 3E 7A 94 30 04 +T 0E 00 30 04 +R 00 00 00 00 +T 10 00 +R 00 00 00 00 +T 10 00 2E 00 18 02 R 00 00 00 00 T 14 00 R 00 00 00 00 -T 14 00 3E 00 18 02 +T 14 00 2E 01 R 00 00 00 00 -T 18 00 +T 16 00 R 00 00 00 00 -T 18 00 3E 01 -R 00 00 00 00 -T 1A 00 -R 00 00 00 00 -T 1A 00 6F 17 9F 67 33 C9 +T 16 00 26 00 33 C9 R 00 00 00 00 -isprint.rel/ 1458795423 2001 2501 100664 821 ` +isprint.rel/ 0 0 0 644 815 ` XL2 H 9 areas 2 global symbols M isprint O -mz80 S .__.ABS. Def0000 -A _CODE size 34 flags 0 addr 0 +A _CODE size 32 flags 0 addr 0 S _isprint Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -38928,18 +53659,18 @@ T 25 00 F2 2C 00 R 00 00 00 00 00 03 00 00 T 28 00 R 00 00 00 00 -T 28 00 3E 00 18 02 +T 28 00 2E 00 18 02 R 00 00 00 00 T 2C 00 R 00 00 00 00 -T 2C 00 3E 01 +T 2C 00 2E 01 R 00 00 00 00 T 2E 00 R 00 00 00 00 -T 2E 00 6F 17 9F 67 33 C9 +T 2E 00 26 00 33 C9 R 00 00 00 00 -ispunct.rel/ 1458795423 2001 2501 100664 840 ` +ispunct.rel/ 0 0 0 644 834 ` XL2 H 9 areas 5 global symbols M ispunct @@ -38948,7 +53679,7 @@ S _isspace Ref0000 S _isalnum Ref0000 S .__.ABS. Def0000 S _isprint Ref0000 -A _CODE size 32 flags 0 addr 0 +A _CODE size 30 flags 0 addr 0 S _ispunct Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -38968,23 +53699,23 @@ T 1C 00 E5 C5 E5 CD 00 00 F1 7C B5 28 04 R 00 00 00 00 02 06 01 00 T 27 00 R 00 00 00 00 -T 27 00 3E 00 18 02 +T 27 00 2E 00 18 02 R 00 00 00 00 T 2B 00 R 00 00 00 00 -T 2B 00 3E 01 +T 2B 00 2E 01 R 00 00 00 00 T 2D 00 R 00 00 00 00 -T 2D 00 6F 17 9F 67 C9 +T 2D 00 26 00 C9 R 00 00 00 00 -isspace.rel/ 1458795423 2001 2501 100664 1092 ` +isspace.rel/ 0 0 0 644 1086 ` XL2 H 9 areas 2 global symbols M isspace O -mz80 S .__.ABS. Def0000 -A _CODE size 63 flags 0 addr 0 +A _CODE size 61 flags 0 addr 0 S _isspace Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -39022,23 +53753,23 @@ T 49 00 DD 7E 04 D6 0B 20 06 DD 7E 05 B7 28 04 R 00 00 00 00 T 56 00 R 00 00 00 00 -T 56 00 3E 00 18 02 +T 56 00 2E 00 18 02 R 00 00 00 00 T 5A 00 R 00 00 00 00 -T 5A 00 3E 01 +T 5A 00 2E 01 R 00 00 00 00 T 5C 00 R 00 00 00 00 -T 5C 00 6F 17 9F 67 DD E1 C9 +T 5C 00 26 00 DD E1 C9 R 00 00 00 00 -isupper.rel/ 1458795423 2001 2501 100664 671 ` +isupper.rel/ 0 0 0 644 653 ` XL2 H 9 areas 2 global symbols M isupper O -mz80 S .__.ABS. Def0000 -A _CODE size 20 flags 0 addr 0 +A _CODE size 1A flags 0 addr 0 S _isupper Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -39050,30 +53781,30 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 3B FD 21 03 00 FD 39 FD 66 00 7C D6 41 38 +T 00 00 3B 21 03 00 39 4E 79 D6 41 38 05 3E 5A 91 R 00 00 00 00 -T 0E 00 05 3E 5A 94 30 04 +T 0E 00 30 04 +R 00 00 00 00 +T 10 00 +R 00 00 00 00 +T 10 00 2E 00 18 02 R 00 00 00 00 T 14 00 R 00 00 00 00 -T 14 00 3E 00 18 02 +T 14 00 2E 01 R 00 00 00 00 -T 18 00 +T 16 00 R 00 00 00 00 -T 18 00 3E 01 -R 00 00 00 00 -T 1A 00 -R 00 00 00 00 -T 1A 00 6F 17 9F 67 33 C9 +T 16 00 26 00 33 C9 R 00 00 00 00 -isxdigit.rel/ 1458795423 2001 2501 100664 1345 ` +isxdigit.rel/ 0 0 0 644 1339 ` XL2 H 9 areas 2 global symbols M isxdigit O -mz80 S .__.ABS. Def0000 -A _CODE size 7A flags 0 addr 0 +A _CODE size 78 flags 0 addr 0 S _isxdigit Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -39121,18 +53852,18 @@ T 69 00 F2 70 00 R 00 00 00 00 00 03 00 00 T 6C 00 R 00 00 00 00 -T 6C 00 3E 00 18 02 +T 6C 00 2E 00 18 02 R 00 00 00 00 T 70 00 R 00 00 00 00 -T 70 00 3E 01 +T 70 00 2E 01 R 00 00 00 00 T 72 00 R 00 00 00 00 -T 72 00 6F 17 9F 67 33 DD E1 C9 +T 72 00 26 00 33 DD E1 C9 R 00 00 00 00 -tolower.rel/ 1458795423 2001 2501 100664 565 ` +tolower.rel/ 0 0 0 644 565 ` XL2 H 9 areas 2 global symbols M tolower @@ -39150,16 +53881,16 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 3B 21 03 00 39 7E 23 66 6F 55 7A D6 41 38 +T 00 00 3B 21 03 00 39 7E 23 66 6F 4D 79 D6 41 38 R 00 00 00 00 -T 0E 00 09 3E 5A 92 38 04 01 20 00 09 +T 0E 00 09 3E 5A 91 38 04 01 20 00 09 R 00 00 00 00 T 18 00 R 00 00 00 00 T 18 00 33 C9 R 00 00 00 00 -toupper.rel/ 1458795423 2001 2501 100664 565 ` +toupper.rel/ 0 0 0 644 565 ` XL2 H 9 areas 2 global symbols M toupper @@ -39177,22 +53908,22 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 3B 21 03 00 39 7E 23 66 6F 55 7A D6 61 38 +T 00 00 3B 21 03 00 39 7E 23 66 6F 4D 79 D6 61 38 R 00 00 00 00 -T 0E 00 09 3E 7A 92 38 04 01 E0 FF 09 +T 0E 00 09 3E 7A 91 38 04 01 E0 FF 09 R 00 00 00 00 T 18 00 R 00 00 00 00 T 18 00 33 C9 R 00 00 00 00 -atoi.rel/ 1458795424 2001 2501 100664 1539 ` +atoi.rel/ 0 0 0 644 1455 ` XL2 H 9 areas 2 global symbols M atoi O -mz80 S .__.ABS. Def0000 -A _CODE size A2 flags 0 addr 0 +A _CODE size 9C flags 0 addr 0 S _atoi Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -39204,75 +53935,69 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 DD E5 DD 21 00 00 DD 39 F5 F5 DD 36 FD 00 +T 00 00 DD E5 DD 21 00 00 DD 39 F5 F5 3B 01 00 00 R 00 00 00 00 -T 0E 00 DD 36 FE 00 DD 5E 04 DD 56 05 +T 0E 00 DD 5E 04 DD 56 05 R 00 00 00 00 -T 18 00 +T 14 00 R 00 00 00 00 -T 18 00 1A 67 6F 17 9F 47 7D FE 20 28 04 D6 09 20 +T 14 00 1A DD 77 FD DD 77 FC 6B 62 23 DD 7E FC D6 R 00 00 00 00 -T 26 00 03 +T 22 00 20 28 07 DD 7E FC D6 09 20 03 R 00 00 00 00 -T 27 00 +T 2C 00 R 00 00 00 00 -T 27 00 13 18 EE +T 2C 00 EB 18 E5 R 00 00 00 00 -T 2A 00 +T 2F 00 R 00 00 00 00 -T 2A 00 DD 73 04 DD 72 05 7C D6 2D 20 04 3E 01 18 +T 2F 00 DD 73 04 DD 72 05 DD 7E FD D6 2D 20 04 3E R 00 00 00 00 -T 38 00 01 +T 3D 00 01 18 01 R 00 00 00 00 -T 39 00 +T 40 00 R 00 00 00 00 -T 39 00 AF +T 40 00 AF R 00 00 00 00 -T 3A 00 +T 41 00 R 00 00 00 00 -T 3A 00 DD 77 FC CB 47 20 05 7C D6 2B 20 07 +T 41 00 DD 77 FB CB 47 20 07 DD 7E FD D6 2B 20 06 R 00 00 00 00 -T 46 00 +T 4F 00 R 00 00 00 00 -T 46 00 13 DD 73 04 DD 72 05 +T 4F 00 DD 75 04 DD 74 05 R 00 00 00 00 -T 4D 00 +T 55 00 R 00 00 00 00 -T 4D 00 DD 4E 04 DD 46 05 +T 55 00 DD 5E 04 DD 56 05 R 00 00 00 00 -T 53 00 +T 5B 00 R 00 00 00 00 -T 53 00 0A 5F 17 9F 57 6B 7D D6 30 38 25 3E 39 95 +T 5B 00 1A DD 77 FE DD 36 FF 00 DD 6E FE 7D D6 30 R 00 00 00 00 -T 61 00 38 20 D5 DD 5E FD DD 56 FE 6B 62 29 29 19 +T 69 00 38 1D 3E 39 95 38 18 69 60 29 29 09 29 13 R 00 00 00 00 -T 6F 00 29 D1 03 7B C6 D0 5F 7A CE FF 57 19 DD 75 +T 77 00 DD 7E FE C6 D0 4F DD 7E FF CE FF 47 09 4D R 00 00 00 00 -T 7D 00 FD DD 74 FE 18 D0 +T 85 00 44 18 D3 R 00 00 00 00 -T 83 00 +T 88 00 R 00 00 00 00 -T 83 00 DD CB FC 46 28 0D AF DD 96 FD 6F 3E 00 DD +T 88 00 DD CB FB 46 28 07 AF 91 4F 3E 00 98 47 R 00 00 00 00 -T 91 00 9E FE 47 18 06 +T 95 00 R 00 00 00 00 -T 96 00 -R 00 00 00 00 -T 96 00 DD 6E FD DD 46 FE -R 00 00 00 00 -T 9C 00 -R 00 00 00 00 -T 9C 00 60 DD F9 DD E1 C9 +T 95 00 69 60 DD F9 DD E1 C9 R 00 00 00 00 -atol.rel/ 1458795424 2001 2501 100664 1958 ` +atol.rel/ 0 0 0 644 2035 ` XL2 H 9 areas 3 global symbols M atol O -mz80 S .__.ABS. Def0000 S __mullong Ref0000 -A _CODE size F7 flags 0 addr 0 +A _CODE size 109 flags 0 addr 0 S _atol Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -39284,79 +54009,82 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 DD E5 DD 21 00 00 DD 39 21 F6 FF 39 F9 AF +T 00 00 DD E5 DD 21 00 00 DD 39 21 F3 FF 39 F9 11 R 00 00 00 00 -T 0E 00 DD 77 F7 DD 77 F8 DD 77 F9 DD 77 FA DD 5E +T 0E 00 00 00 01 00 00 DD 6E 04 DD 66 05 R 00 00 00 00 -T 1C 00 04 DD 56 05 +T 19 00 R 00 00 00 00 -T 20 00 +T 19 00 7E DD 77 F6 DD 77 F3 DD 36 F4 00 DD 7E F3 R 00 00 00 00 -T 20 00 1A 6F 67 17 9F 47 7C FE 20 28 04 D6 09 20 +T 27 00 DD 77 FB 7D C6 01 DD 77 FC 7C CE 00 DD 77 R 00 00 00 00 -T 2E 00 03 +T 35 00 FD DD 7E FB D6 20 28 07 DD 7E FB D6 09 20 R 00 00 00 00 -T 2F 00 +T 43 00 08 R 00 00 00 00 -T 2F 00 13 18 EE +T 44 00 R 00 00 00 00 -T 32 00 +T 44 00 DD 6E FC DD 66 FD 18 CD R 00 00 00 00 -T 32 00 DD 73 04 DD 72 05 7D D6 2D 20 04 3E 01 18 +T 4C 00 R 00 00 00 00 -T 40 00 01 +T 4C 00 DD 75 04 DD 74 05 DD 7E F6 D6 2D 20 04 3E R 00 00 00 00 -T 41 00 +T 5A 00 01 18 01 R 00 00 00 00 -T 41 00 AF +T 5D 00 R 00 00 00 00 -T 42 00 +T 5D 00 AF R 00 00 00 00 -T 42 00 DD 77 F6 CB 47 20 05 7D D6 2B 20 07 +T 5E 00 R 00 00 00 00 -T 4E 00 +T 5E 00 DD 77 F5 CB 47 20 07 DD 7E F6 D6 2B 20 0C R 00 00 00 00 -T 4E 00 13 DD 73 04 DD 72 05 +T 6C 00 R 00 00 00 00 -T 55 00 +T 6C 00 DD 7E FC DD 77 04 DD 7E FD DD 77 05 R 00 00 00 00 -T 55 00 DD 4E 04 DD 46 05 +T 78 00 R 00 00 00 00 -T 5B 00 +T 78 00 DD 7E 04 DD 77 FC DD 7E 05 DD 77 FD R 00 00 00 00 -T 5B 00 0A 5F 17 9F 57 6B 7D D6 30 38 61 3E 39 95 +T 84 00 R 00 00 00 00 -T 69 00 38 5C C5 D5 DD 6E F9 DD 66 FA E5 DD 6E F7 +T 84 00 DD 6E FC DD 66 FD 6E DD 75 FE DD 36 FF 00 R 00 00 00 00 -T 77 00 DD 66 F8 E5 21 00 00 E5 21 0A 00 E5 CD +T 92 00 DD 6E FE 7D D6 30 38 50 3E 39 95 38 4B C5 R 00 00 00 00 -T 84 00 00 00 F1 F1 F1 F1 DD 72 FE DD 73 FD DD 74 -R 00 00 00 00 02 02 01 00 -T 92 00 FC DD 75 FB D1 C1 03 7B C6 D0 6F 7A CE FF +T A0 00 D5 21 00 00 E5 21 0A 00 E5 CD 00 00 F1 F1 +R 00 00 00 00 02 0C 01 00 +T AE 00 F1 F1 EB DD 34 FC 20 03 DD 34 FD R 00 00 00 00 -T A0 00 67 17 9F 5F 57 DD 7E FB 85 6F DD 7E FC 8C +T B9 00 R 00 00 00 00 -T AE 00 67 DD 7E FD 8B 5F DD 7E FE 8A 57 DD 75 F7 +T B9 00 DD 7E FE C6 D0 4F DD 7E FF CE FF 47 DD 71 R 00 00 00 00 -T BC 00 DD 74 F8 DD 73 F9 DD 72 FA 18 94 +T C7 00 F7 DD 70 F8 78 17 9F DD 77 F9 DD 77 FA 7B R 00 00 00 00 -T C7 00 +T D5 00 DD 86 F7 5F 7A DD 8E F8 57 7D DD 8E F9 4F R 00 00 00 00 -T C7 00 DD CB F6 46 28 19 AF DD 96 F7 6F 3E 00 DD +T E3 00 7C DD 8E FA 47 18 9A R 00 00 00 00 -T D5 00 9E F8 67 3E 00 DD 9E F9 5F 3E 00 DD 9E FA +T EA 00 R 00 00 00 00 -T E3 00 57 18 0C +T EA 00 DD CB F5 46 28 11 AF 93 5F 3E 00 9A 57 3E R 00 00 00 00 -T E6 00 +T F8 00 00 99 6F 3E 00 98 67 18 02 R 00 00 00 00 -T E6 00 DD 6E F7 DD 66 F8 DD 5E F9 DD 56 FA +T 01 01 R 00 00 00 00 -T F2 00 +T 01 01 69 60 R 00 00 00 00 -T F2 00 DD F9 DD E1 C9 +T 03 01 R 00 00 00 00 -atoll.rel/ 1458795424 2001 2501 100664 355 ` +T 03 01 EB DD F9 DD E1 C9 +R 00 00 00 00 + +atoll.rel/ 0 0 0 644 355 ` XL2 H 9 areas 1 global symbols M atoll @@ -39372,7 +54100,7 @@ A _GSFINAL size 0 flags 0 addr 0 A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 -abs.rel/ 1458795406 2001 2501 100664 175 ` +abs.rel/ 0 0 0 644 175 ` XL2 H 1 areas 2 global symbols S .__.ABS. Def0000 @@ -39383,7 +54111,7 @@ R 00 00 00 00 T 00 00 E1 D1 D5 E5 AF 6F 67 ED 52 F0 EB C9 R 00 00 00 00 -labs.rel/ 1458795424 2001 2501 100664 690 ` +labs.rel/ 0 0 0 644 690 ` XL2 H 9 areas 2 global symbols M labs @@ -39413,16 +54141,15 @@ T 24 00 FD 21 02 00 FD 39 FD 6E 00 FD 66 01 FD 5E R 00 00 00 00 T 32 00 02 FD 56 03 C9 R 00 00 00 00 -rand.rel/ 1458795424 2001 2501 100664 1273 ` +rand.rel/ 0 0 0 644 1618 ` XL2 -H 9 areas 4 global symbols +H 9 areas 3 global symbols M rand O -mz80 S .__.ABS. Def0000 -S __mullong Ref0000 -A _CODE size 77 flags 0 addr 0 +A _CODE size DA flags 0 addr 0 S _rand Def0000 -S _srand Def005C +S _srand Def00BC A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 4 flags 0 addr 0 A _DABS size 0 flags 8 addr 0 @@ -39437,34 +54164,49 @@ T 00 00 R 00 00 02 00 T 00 00 R 00 00 00 00 -T 00 00 2A 02 00 E5 2A 00 00 E5 21 C6 41 E5 21 -R 00 00 00 00 00 03 02 00 00 07 02 00 -T 0D 00 6D 4E E5 CD 00 00 F1 F1 F1 F1 4D 44 79 21 -R 00 00 00 00 02 06 01 00 -T 1B 00 00 00 C6 39 77 78 CE 30 23 77 7B CE 00 23 -R 00 00 00 00 00 02 02 00 -T 29 00 77 7A CE 00 23 77 F5 FD 21 00 00 FD 6E 00 -R 00 00 00 00 00 0B 02 00 -T 37 00 FD 21 00 00 FD 66 01 FD 21 00 00 FD 5E 02 -R 00 00 00 00 00 04 02 00 00 0B 02 00 -T 45 00 FD 21 00 00 FD 56 03 F1 06 10 -R 00 00 00 00 00 04 02 00 -T 4F 00 +T 00 00 DD E5 DD 21 00 00 DD 39 F5 F5 FD 21 00 00 +R 00 00 00 00 00 0E 02 00 +T 0E 00 FD 5E 00 FD 56 01 FD 6E 02 FD 66 03 DD 72 R 00 00 00 00 -T 4F 00 CB 3A CB 1B CB 1C CB 1D 10 F6 CB BC C9 +T 1C 00 FC DD 75 FD DD 74 FE DD 36 FF 00 06 02 R 00 00 00 00 -T 5C 00 +T 29 00 +R 00 00 00 00 +T 29 00 DD CB FE 3E DD CB FD 1E DD CB FC 1E 10 F2 +R 00 00 00 00 +T 37 00 7B DD AE FC 4F 7A DD AE FD 47 7D DD AE FE +R 00 00 00 00 +T 45 00 5F 7C DD AE FF 57 DD 71 FD DD 70 FE DD 73 +R 00 00 00 00 +T 53 00 FF DD 36 FC 00 DD CB FD 26 DD CB FE 16 DD +R 00 00 00 00 +T 61 00 CB FF 16 79 DD AE FC 4F 78 DD AE FD 47 7B +R 00 00 00 00 +T 6F 00 DD AE FE 5F 7A DD AE FF 57 DD 72 FC DD 36 +R 00 00 00 00 +T 7D 00 FD 00 DD 36 FE 00 DD 36 FF 00 DD CB FC 3E +R 00 00 00 00 +T 8B 00 DD 7E FC A9 DD 77 FC DD 7E FD A8 DD 77 FD +R 00 00 00 00 +T 99 00 DD 7E FE AB DD 77 FE DD 7E FF AA DD 77 FF +R 00 00 00 00 +T A7 00 11 00 00 21 00 00 39 01 04 00 ED B0 E1 E5 +R 00 00 00 00 00 03 02 00 +T B5 00 CB BC DD F9 DD E1 C9 +R 00 00 00 00 +T BC 00 +R 00 00 00 00 +T BC 00 21 02 00 39 4E 23 46 11 00 00 FD 21 00 00 +R 00 00 00 00 00 0E 02 00 +T CA 00 FD 71 00 FD 70 01 FD 73 02 7A CB FF FD 77 +R 00 00 00 00 +T D8 00 03 C9 R 00 00 00 00 -T 5C 00 21 02 00 39 7E 32 00 00 21 03 00 39 7E 32 -R 00 00 00 00 00 08 02 00 -T 6A 00 01 00 21 02 00 36 00 21 03 00 36 00 C9 -R 00 00 00 00 00 02 02 00 00 05 02 00 00 0A 02 00 T 00 00 R 00 00 07 00 -T 00 00 01 00 00 00 +T 00 00 01 00 00 80 R 00 00 07 00 - -_strcat.rel/ 1458795424 2001 2501 100664 703 ` +_strcat.rel/ 0 0 0 644 703 ` XL2 H 9 areas 2 global symbols M _strcat @@ -39482,30 +54224,30 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 DD E5 DD 21 00 00 DD 39 DD 4E 04 DD 46 05 +T 00 00 DD E5 DD 21 00 00 DD 39 DD 5E 04 DD 56 05 R 00 00 00 00 T 0E 00 R 00 00 00 00 -T 0E 00 0A B7 28 03 03 18 F9 +T 0E 00 1A B7 28 03 13 18 F9 R 00 00 00 00 T 15 00 R 00 00 00 00 -T 15 00 DD 5E 06 DD 56 07 +T 15 00 DD 4E 06 DD 46 07 R 00 00 00 00 T 1B 00 R 00 00 00 00 -T 1B 00 1A 13 02 03 B7 20 F9 DD 6E 04 DD 66 05 DD +T 1B 00 0A 03 12 13 B7 20 F9 DD 6E 04 DD 66 05 DD R 00 00 00 00 T 29 00 E1 C9 R 00 00 00 00 -_strchr.rel/ 1458795424 2001 2501 100664 944 ` +_strchr.rel/ 0 0 0 644 932 ` XL2 H 9 areas 2 global symbols M _strchr O -mz80 S .__.ABS. Def0000 -A _CODE size 48 flags 0 addr 0 +A _CODE size 44 flags 0 addr 0 S _strchr Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -39523,71 +54265,37 @@ T 0E 00 05 R 00 00 00 00 T 0F 00 R 00 00 00 00 -T 0F 00 0A DD 77 FF 57 DD 7E FF 17 9F 5F DD 7E 06 +T 0F 00 0A DD 77 FF 5F 16 00 DD 7E 06 93 20 0A DD R 00 00 00 00 -T 1D 00 92 20 0A DD 7E 07 93 20 04 3E 01 18 01 +T 1D 00 7E 07 92 20 04 3E 01 18 01 R 00 00 00 00 -T 2A 00 +T 26 00 R 00 00 00 00 -T 2A 00 AF +T 26 00 AF R 00 00 00 00 -T 2B 00 +T 27 00 R 00 00 00 00 -T 2B 00 57 DD 7E FF B7 28 07 7A B7 20 03 03 18 D6 +T 27 00 5F DD 7E FF B7 28 07 CB 43 20 03 03 18 DA R 00 00 00 00 -T 39 00 +T 35 00 R 00 00 00 00 -T 39 00 7A B7 28 04 69 60 18 03 +T 35 00 CB 43 28 04 69 60 18 03 R 00 00 00 00 -T 41 00 +T 3D 00 R 00 00 00 00 -T 41 00 21 00 00 +T 3D 00 21 00 00 R 00 00 00 00 -T 44 00 +T 40 00 R 00 00 00 00 -T 44 00 33 DD E1 C9 +T 40 00 33 DD E1 C9 R 00 00 00 00 -_strcmp.rel/ 1458795424 2001 2501 100664 772 ` -XL2 -H 9 areas 2 global symbols -M _strcmp -O -mz80 -S .__.ABS. Def0000 -A _CODE size 42 flags 0 addr 0 -S _strcmp Def0000 -A _DATA size 0 flags 0 addr 0 -A _INITIALIZED size 0 flags 0 addr 0 -A _DABS size 0 flags 8 addr 0 -A _HOME size 0 flags 0 addr 0 -A _GSINIT size 0 flags 0 addr 0 -A _GSFINAL size 0 flags 0 addr 0 -A _INITIALIZER size 0 flags 0 addr 0 -A _CABS size 0 flags 8 addr 0 -T 00 00 -R 00 00 00 00 -T 00 00 DD E5 DD 21 00 00 DD 39 3B DD 4E 04 DD 46 -R 00 00 00 00 -T 0E 00 05 DD 5E 06 DD 56 07 D5 FD E1 -R 00 00 00 00 -T 18 00 -R 00 00 00 00 -T 18 00 0A 5F 17 9F 57 FD 7E 00 DD 77 FF 6F DD 7E -R 00 00 00 00 -T 26 00 FF 17 9F 67 7B 95 6F 7A 9C 67 B5 20 0B DD -R 00 00 00 00 -T 34 00 7E FF B7 28 05 03 FD 23 18 DA -R 00 00 00 00 -T 3E 00 -R 00 00 00 00 -T 3E 00 33 DD E1 C9 -R 00 00 00 00 -_strcspn.rel/ 1458795424 2001 2501 100664 807 ` +_strcspn.rel/ 0 0 0 644 779 ` XL2 H 9 areas 2 global symbols M _strcspn O -mz80 S .__.ABS. Def0000 -A _CODE size 37 flags 0 addr 0 +A _CODE size 35 flags 0 addr 0 S _strcspn Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -39605,24 +54313,22 @@ T 0E 00 DD 46 05 R 00 00 00 00 T 11 00 R 00 00 00 00 -T 11 00 0A 67 B7 28 1D 17 9F D5 54 DD 6E 06 DD 66 +T 11 00 0A 6F B7 28 1B D5 55 DD 6E 06 DD 66 07 R 00 00 00 00 -T 1F 00 07 +T 1E 00 R 00 00 00 00 -T 20 00 +T 1E 00 7E BA 28 06 B7 23 20 F8 6F 67 R 00 00 00 00 -T 20 00 7E BA 28 06 B7 23 20 F8 6F 67 +T 28 00 R 00 00 00 00 -T 2A 00 +T 28 00 D1 7C B5 20 04 13 03 18 E0 R 00 00 00 00 -T 2A 00 D1 7C B5 20 04 13 03 18 DE +T 31 00 R 00 00 00 00 -T 33 00 -R 00 00 00 00 -T 33 00 EB DD E1 C9 +T 31 00 EB DD E1 C9 R 00 00 00 00 -_strncat.rel/ 1458795425 2001 2501 100664 1262 ` +_strncat.rel/ 0 0 0 644 1262 ` XL2 H 9 areas 2 global symbols M _strncat @@ -39642,25 +54348,25 @@ T 00 00 R 00 00 00 00 T 00 00 DD E5 DD 21 00 00 DD 39 F5 F5 3B DD 4E 04 R 00 00 00 00 -T 0E 00 DD 46 05 69 60 +T 0E 00 DD 46 05 59 50 R 00 00 00 00 T 13 00 R 00 00 00 00 -T 13 00 7E 23 B7 20 FB 7D C6 FF DD 77 04 7C CE FF +T 13 00 1A 13 B7 20 FB 7B C6 FF DD 77 04 7A CE FF R 00 00 00 00 T 21 00 DD 77 05 DD 5E 06 DD 56 07 DD 7E 04 DD 77 R 00 00 00 00 -T 2F 00 FB DD 7E 05 DD 77 FC DD 7E 08 DD 77 FE DD +T 2F 00 FB DD 7E 05 DD 77 FC DD 7E 08 DD 77 FD DD R 00 00 00 00 -T 3D 00 7E 09 DD 77 FF +T 3D 00 7E 09 DD 77 FE R 00 00 00 00 T 42 00 R 00 00 00 00 -T 42 00 DD 6E FE DD 66 FF DD 7E FE C6 FF DD 77 FE +T 42 00 DD 6E FD DD 66 FE DD 7E FD C6 FF DD 77 FD R 00 00 00 00 -T 50 00 DD 7E FF CE FF DD 77 FF 7C B5 28 29 1A DD +T 50 00 DD 7E FE CE FF DD 77 FE 7C B5 28 29 1A DD R 00 00 00 00 -T 5E 00 77 FD 13 E1 E5 DD 7E FD 77 DD 34 FB 20 03 +T 5E 00 77 FF 13 E1 E5 DD 7E FF 77 DD 34 FB 20 03 R 00 00 00 00 T 6C 00 DD 34 FC R 00 00 00 00 @@ -39668,23 +54374,23 @@ T 6F 00 R 00 00 00 00 T 6F 00 DD 7E FB DD 77 04 DD 7E FC DD 77 05 DD 7E R 00 00 00 00 -T 7D 00 FD B7 20 C1 69 60 18 0A +T 7D 00 FF B7 20 C1 69 60 18 0A R 00 00 00 00 T 85 00 R 00 00 00 00 -T 85 00 DD 6E 04 DD 66 05 36 00 69 60 +T 85 00 DD 5E 04 DD 56 05 AF 12 69 60 R 00 00 00 00 T 8F 00 R 00 00 00 00 T 8F 00 DD F9 DD E1 C9 R 00 00 00 00 -_strncmp.rel/ 1458795425 2001 2501 100664 1182 ` +_strncmp.rel/ 0 0 0 644 1075 ` XL2 H 9 areas 2 global symbols M _strncmp O -mz80 S .__.ABS. Def0000 -A _CODE size 88 flags 0 addr 0 +A _CODE size 73 flags 0 addr 0 S _strncmp Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -39696,41 +54402,38 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 DD E5 DD 21 00 00 DD 39 21 FA FF 39 F9 DD +T 00 00 DD E5 DD 21 00 00 DD 39 F5 F5 3B DD 7E 09 R 00 00 00 00 -T 0E 00 7E 09 DD B6 08 20 05 21 00 00 18 69 +T 0E 00 DD B6 08 20 05 21 00 00 18 56 R 00 00 00 00 -T 1A 00 +T 18 00 R 00 00 00 00 -T 1A 00 DD 7E 04 DD 77 FC DD 7E 05 DD 77 FD DD 7E +T 18 00 DD 4E 04 DD 46 05 DD 7E 06 DD 77 FE DD 7E R 00 00 00 00 -T 28 00 06 DD 77 FA DD 7E 07 DD 77 FB DD 7E 08 DD +T 26 00 07 DD 77 FF DD 7E 08 DD 77 FB DD 7E 09 DD R 00 00 00 00 -T 36 00 77 FE DD 7E 09 DD 77 FF +T 34 00 77 FC R 00 00 00 00 -T 3E 00 +T 36 00 R 00 00 00 00 -T 3E 00 DD 6E FE DD 66 FF 2B DD 75 FE DD 74 FF DD +T 36 00 E1 E5 2B E3 0A DD 77 FD DD 6E FE DD 66 FF R 00 00 00 00 -T 4C 00 6E FC DD 66 FD 5E E1 E5 4E DD 7E FF DD B6 +T 44 00 5E DD 7E FC DD B6 FB 28 17 DD 7E FD B7 28 R 00 00 00 00 -T 5A 00 FE 28 1A 7B B7 28 16 7B 91 20 12 DD 34 FC +T 52 00 11 DD 7E FD 93 20 0B 03 DD 34 FE 20 D7 DD R 00 00 00 00 -T 68 00 20 03 DD 34 FD +T 60 00 34 FF 18 D2 R 00 00 00 00 -T 6D 00 +T 64 00 R 00 00 00 00 -T 6D 00 DD 34 FA 20 CC DD 34 FB 18 C7 +T 64 00 DD 6E FD 26 00 16 00 BF ED 52 R 00 00 00 00 -T 77 00 +T 6E 00 R 00 00 00 00 -T 77 00 7B 6F 17 9F 67 79 17 9F 47 BF ED 42 +T 6E 00 DD F9 DD E1 C9 R 00 00 00 00 -T 83 00 -R 00 00 00 00 -T 83 00 DD F9 DD E1 C9 -R 00 00 00 00 -strxfrm.rel/ 1458795425 2001 2501 100664 686 ` + +strxfrm.rel/ 0 0 0 644 686 ` XL2 H 9 areas 4 global symbols M strxfrm @@ -39758,7 +54461,7 @@ T 1C 00 06 00 39 F9 21 04 00 39 4E 23 46 C5 CD R 00 00 00 00 T 29 00 00 00 F1 23 C9 R 00 00 00 00 02 02 02 00 -_strncpy.rel/ 1458795425 2001 2501 100664 870 ` +_strncpy.rel/ 0 0 0 644 870 ` XL2 H 9 areas 2 global symbols M _strncpy @@ -39784,7 +54487,7 @@ T 1C 00 4E 06 DD 46 07 C5 FD E1 C1 C5 R 00 00 00 00 T 26 00 R 00 00 00 00 -T 26 00 7A B3 28 0F FD 66 00 7C B7 28 08 1B 7C FD +T 26 00 7A B3 28 0F FD 6E 00 7D B7 28 08 1B 7D FD R 00 00 00 00 T 34 00 23 02 03 18 ED R 00 00 00 00 @@ -39792,19 +54495,19 @@ T 39 00 R 00 00 00 00 T 39 00 R 00 00 00 00 -T 39 00 63 6A 1B 7D B4 28 05 AF 02 03 18 F4 +T 39 00 6B 62 1B 7C B5 28 05 AF 02 03 18 F4 R 00 00 00 00 T 45 00 R 00 00 00 00 T 45 00 E1 E5 DD F9 DD E1 C9 R 00 00 00 00 -_strpbrk.rel/ 1458795425 2001 2501 100664 961 ` +_strpbrk.rel/ 0 0 0 644 955 ` XL2 H 9 areas 2 global symbols M _strpbrk O -mz80 S .__.ABS. Def0000 -A _CODE size 4D flags 0 addr 0 +A _CODE size 4B flags 0 addr 0 S _strpbrk Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -39818,42 +54521,42 @@ T 00 00 R 00 00 00 00 T 00 00 DD E5 DD 21 00 00 DD 39 F5 21 00 00 E3 DD R 00 00 00 00 -T 0E 00 6E 06 DD 66 07 +T 0E 00 4E 06 DD 46 07 R 00 00 00 00 T 13 00 R 00 00 00 00 -T 13 00 7E 4F B7 28 2E 17 9F DD 5E 04 DD 56 05 +T 13 00 0A 6F B7 28 2C DD 5E 04 DD 56 05 R 00 00 00 00 -T 20 00 +T 1E 00 R 00 00 00 00 -T 20 00 1A B9 28 06 B7 13 20 F8 5F 57 +T 1E 00 1A BD 28 06 B7 13 20 F8 5F 57 R 00 00 00 00 -T 2A 00 +T 28 00 R 00 00 00 00 -T 2A 00 7A B3 28 15 DD 7E FF DD B6 FE 28 0A 7B DD +T 28 00 7A B3 28 15 DD 7E FF DD B6 FE 28 0A 7B DD R 00 00 00 00 -T 38 00 96 FE 7A DD 9E FF 30 03 +T 36 00 96 FE 7A DD 9E FF 30 03 R 00 00 00 00 -T 40 00 +T 3E 00 R 00 00 00 00 -T 40 00 33 33 D5 +T 3E 00 33 33 D5 R 00 00 00 00 -T 43 00 +T 41 00 R 00 00 00 00 -T 43 00 23 18 CD +T 41 00 03 18 CF R 00 00 00 00 -T 46 00 +T 44 00 R 00 00 00 00 -T 46 00 E1 E5 DD F9 DD E1 C9 +T 44 00 E1 E5 DD F9 DD E1 C9 R 00 00 00 00 -_strrchr.rel/ 1458795425 2001 2501 100664 1070 ` +_strrchr.rel/ 0 0 0 644 1101 ` XL2 H 9 areas 2 global symbols M _strrchr O -mz80 S .__.ABS. Def0000 -A _CODE size 54 flags 0 addr 0 +A _CODE size 57 flags 0 addr 0 S _strrchr Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -39865,51 +54568,54 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 DD E5 DD 21 00 00 DD 39 F5 DD 7E 04 DD 77 +T 00 00 DD E5 DD 21 00 00 DD 39 F5 DD 5E 04 DD 56 R 00 00 00 00 -T 0E 00 FE DD 7E 05 DD 77 FF C1 C5 +T 0E 00 05 4B 42 R 00 00 00 00 -T 17 00 +T 11 00 R 00 00 00 00 -T 17 00 0A 03 B7 20 FB +T 11 00 0A 03 B7 20 FB R 00 00 00 00 -T 1C 00 +T 16 00 R 00 00 00 00 -T 1C 00 0B 0A 57 17 9F 5F DD 7E 06 92 20 0A DD 7E +T 16 00 0B 0A DD 77 FE DD 36 FF 00 DD 7E 06 DD 96 R 00 00 00 00 -T 2A 00 07 93 20 04 3E 01 18 01 +T 24 00 FE 20 0C DD 7E 07 DD 96 FF 20 04 3E 01 18 R 00 00 00 00 -T 32 00 -R 00 00 00 00 -T 32 00 AF +T 32 00 01 R 00 00 00 00 T 33 00 R 00 00 00 00 -T 33 00 57 DD 7E FE 91 20 06 DD 7E FF 90 28 04 +T 33 00 AF R 00 00 00 00 -T 40 00 +T 34 00 R 00 00 00 00 -T 40 00 7A B7 28 D8 +T 34 00 DD 77 FE 7B 91 20 04 7A 90 28 06 R 00 00 00 00 -T 44 00 +T 3F 00 R 00 00 00 00 -T 44 00 7A B7 28 04 69 60 18 03 +T 3F 00 DD CB FE 46 28 D1 R 00 00 00 00 -T 4C 00 +T 45 00 R 00 00 00 00 -T 4C 00 21 00 00 +T 45 00 DD CB FE 46 28 04 69 60 18 03 R 00 00 00 00 T 4F 00 R 00 00 00 00 -T 4F 00 DD F9 DD E1 C9 +T 4F 00 21 00 00 R 00 00 00 00 -_strspn.rel/ 1458795425 2001 2501 100664 805 ` +T 52 00 +R 00 00 00 00 +T 52 00 DD F9 DD E1 C9 +R 00 00 00 00 + +_strspn.rel/ 0 0 0 644 777 ` XL2 H 9 areas 2 global symbols M _strspn O -mz80 S .__.ABS. Def0000 -A _CODE size 37 flags 0 addr 0 +A _CODE size 35 flags 0 addr 0 S _strspn Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -39927,30 +54633,28 @@ T 0E 00 DD 46 05 R 00 00 00 00 T 11 00 R 00 00 00 00 -T 11 00 0A 67 B7 28 1D 17 9F D5 54 DD 6E 06 DD 66 +T 11 00 0A 6F B7 28 1B D5 55 DD 6E 06 DD 66 07 R 00 00 00 00 -T 1F 00 07 +T 1E 00 R 00 00 00 00 -T 20 00 +T 1E 00 7E BA 28 06 B7 23 20 F8 6F 67 R 00 00 00 00 -T 20 00 7E BA 28 06 B7 23 20 F8 6F 67 +T 28 00 R 00 00 00 00 -T 2A 00 +T 28 00 D1 7C B5 28 04 13 03 18 E0 R 00 00 00 00 -T 2A 00 D1 7C B5 28 04 13 03 18 DE +T 31 00 R 00 00 00 00 -T 33 00 -R 00 00 00 00 -T 33 00 EB DD E1 C9 +T 31 00 EB DD E1 C9 R 00 00 00 00 -_strstr.rel/ 1458795425 2001 2501 100664 1562 ` +_strstr.rel/ 0 0 0 644 1516 ` XL2 H 9 areas 2 global symbols M _strstr O -mz80 S .__.ABS. Def0000 -A _CODE size B2 flags 0 addr 0 +A _CODE size AA flags 0 addr 0 S _strstr Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -39966,7 +54670,7 @@ T 00 00 DD E5 DD 21 00 00 DD 39 21 F6 FF 39 F9 DD R 00 00 00 00 T 0E 00 4E 04 DD 46 05 DD 5E 06 DD 56 07 1A B7 20 R 00 00 00 00 -T 1C 00 05 69 60 C3 AD 00 +T 1C 00 05 69 60 C3 A5 00 R 00 00 00 00 00 06 00 00 T 22 00 R 00 00 00 00 @@ -39974,7 +54678,7 @@ T 22 00 33 33 C5 R 00 00 00 00 T 25 00 R 00 00 00 00 -T 25 00 E1 E5 7E B7 CA AA 00 DD 73 FE DD 72 FF DD +T 25 00 E1 E5 7E B7 CA A2 00 DD 73 FE DD 72 FF DD R 00 00 00 00 00 07 00 00 T 33 00 7E F6 DD 77 FC DD 7E F7 DD 77 FD R 00 00 00 00 @@ -39982,47 +54686,45 @@ T 3E 00 R 00 00 00 00 T 3E 00 DD 6E FC DD 66 FD 7E DD 77 FB DD 6E FE DD R 00 00 00 00 -T 4C 00 66 FF 7E DD 77 FA DD 7E FB B7 28 3B DD 7E +T 4C 00 66 FF 7E DD 77 FA DD 7E FB B7 28 33 DD 7E R 00 00 00 00 -T 5A 00 FA B7 28 35 DD 7E FB DD 77 F8 DD 7E FB 17 +T 5A 00 FA B7 28 2D DD 6E FB 26 00 DD 7E FA DD 77 R 00 00 00 00 -T 68 00 9F DD 77 F9 DD 66 FA DD 7E FA 17 9F 6F DD +T 68 00 F8 DD 36 F9 00 7D DD 96 F8 6F 7C DD 9E F9 R 00 00 00 00 -T 76 00 7E F8 94 67 DD 7E F9 9D B4 20 12 DD 34 FC +T 76 00 B5 20 12 DD 34 FC 20 03 DD 34 FD R 00 00 00 00 -T 84 00 20 03 DD 34 FD +T 81 00 R 00 00 00 00 -T 89 00 +T 81 00 DD 34 FE 20 B8 DD 34 FF 18 B3 R 00 00 00 00 -T 89 00 DD 34 FE 20 B0 DD 34 FF 18 AB +T 8B 00 R 00 00 00 00 -T 93 00 +T 8B 00 DD 7E FA B7 20 04 69 60 18 10 R 00 00 00 00 -T 93 00 DD 7E FA B7 20 04 69 60 18 10 +T 95 00 +R 00 00 00 00 +T 95 00 DD 34 F6 20 03 DD 34 F7 R 00 00 00 00 T 9D 00 R 00 00 00 00 -T 9D 00 DD 34 F6 20 03 DD 34 F7 +T 9D 00 C1 C5 C3 25 00 +R 00 00 00 00 00 05 00 00 +T A2 00 +R 00 00 00 00 +T A2 00 21 00 00 R 00 00 00 00 T A5 00 R 00 00 00 00 -T A5 00 C1 C5 C3 25 00 -R 00 00 00 00 00 05 00 00 -T AA 00 +T A5 00 DD F9 DD E1 C9 R 00 00 00 00 -T AA 00 21 00 00 -R 00 00 00 00 -T AD 00 -R 00 00 00 00 -T AD 00 DD F9 DD E1 C9 -R 00 00 00 00 -_strtok.rel/ 1458795425 2001 2501 100664 1807 ` +_strtok.rel/ 0 0 0 644 1787 ` XL2 H 9 areas 2 global symbols M _strtok O -mz80 S .__.ABS. Def0000 -A _CODE size AF flags 0 addr 0 +A _CODE size B1 flags 0 addr 0 S _strtok Def0000 A _DATA size 2 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -40044,68 +54746,70 @@ T 0E 00 FD 7E 00 32 00 00 21 03 00 39 7E 32 01 00 R 00 00 00 00 00 06 01 00 00 0E 01 00 T 1C 00 R 00 00 00 00 -T 1C 00 3A 01 00 21 00 00 B6 20 04 21 00 00 C9 -R 00 00 00 00 00 03 01 00 00 06 01 00 -T 29 00 +T 1C 00 FD 21 00 00 FD 7E 01 FD B6 00 20 04 21 +R 00 00 00 00 00 04 01 00 +T 29 00 00 00 C9 R 00 00 00 00 -T 29 00 2A 00 00 7E B7 28 2A 5F 17 9F 57 FD 21 +T 2C 00 +R 00 00 00 00 +T 2C 00 2A 00 00 4E 79 B7 28 24 51 21 04 00 39 4E R 00 00 00 00 00 03 01 00 -T 36 00 04 00 FD 39 FD 6E 00 FD 66 01 +T 3A 00 23 46 R 00 00 00 00 -T 40 00 +T 3C 00 R 00 00 00 00 -T 40 00 7E BB 28 06 B7 23 20 F8 6F 67 +T 3C 00 0A BA 28 06 B7 03 20 F8 4F 47 R 00 00 00 00 -T 4A 00 +T 46 00 R 00 00 00 00 -T 4A 00 7C B5 28 0C 21 00 00 34 20 D5 21 01 00 34 +T 46 00 78 B1 28 0E FD 21 00 00 FD 34 00 20 D9 FD +R 00 00 00 00 00 08 01 00 +T 54 00 34 01 18 D4 +R 00 00 00 00 +T 58 00 +R 00 00 00 00 +T 58 00 ED 4B 00 00 +R 00 00 00 00 00 04 01 00 +T 5C 00 +R 00 00 00 00 +T 5C 00 2A 00 00 6E 7D B7 28 3C FD 21 04 00 FD 39 +R 00 00 00 00 00 03 01 00 +T 6A 00 FD 5E 00 FD 56 01 +R 00 00 00 00 +T 70 00 +R 00 00 00 00 +T 70 00 1A BD 28 06 B7 13 20 F8 5F 57 +R 00 00 00 00 +T 7A 00 +R 00 00 00 00 +T 7A 00 7A B3 28 14 2A 00 00 36 00 FD 21 00 00 FD R 00 00 00 00 00 07 01 00 00 0D 01 00 -T 58 00 18 CF +T 88 00 34 00 20 03 FD 34 01 R 00 00 00 00 -T 5A 00 +T 8F 00 R 00 00 00 00 -T 5A 00 ED 5B 00 00 +T 8F 00 69 60 C9 +R 00 00 00 00 +T 92 00 +R 00 00 00 00 +T 92 00 FD 21 00 00 FD 34 00 20 C1 FD 34 01 18 BC R 00 00 00 00 00 04 01 00 -T 5E 00 +T A0 00 R 00 00 00 00 -T 5E 00 2A 00 00 7E B7 28 3A 47 17 9F FD 21 04 00 -R 00 00 00 00 00 03 01 00 -T 6C 00 FD 39 FD 6E 00 FD 66 01 -R 00 00 00 00 -T 74 00 -R 00 00 00 00 -T 74 00 7E B8 28 06 B7 23 20 F8 6F 67 -R 00 00 00 00 -T 7E 00 -R 00 00 00 00 -T 7E 00 7C B5 28 11 2A 00 00 36 00 21 00 00 34 20 -R 00 00 00 00 00 07 01 00 00 0C 01 00 -T 8C 00 04 21 01 00 34 -R 00 00 00 00 00 04 01 00 -T 91 00 -R 00 00 00 00 -T 91 00 EB C9 -R 00 00 00 00 -T 93 00 -R 00 00 00 00 -T 93 00 21 00 00 34 20 C5 21 01 00 34 18 BF -R 00 00 00 00 00 03 01 00 00 09 01 00 -T 9F 00 -R 00 00 00 00 -T 9F 00 21 00 00 22 00 00 1A B7 28 02 EB C9 +T A0 00 21 00 00 22 00 00 0A B7 28 03 69 60 C9 R 00 00 00 00 00 06 01 00 -T AB 00 +T AD 00 R 00 00 00 00 -T AB 00 21 00 00 C9 +T AD 00 21 00 00 C9 R 00 00 00 00 -_memchr.rel/ 1458795426 2001 2501 100664 1016 ` +_memchr.rel/ 0 0 0 644 1057 ` XL2 H 9 areas 2 global symbols M _memchr O -mz80 S .__.ABS. Def0000 -A _CODE size 60 flags 0 addr 0 +A _CODE size 5F flags 0 addr 0 S _memchr Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -40117,43 +54821,48 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 DD E5 DD 21 00 00 DD 39 F5 F5 DD 7E 04 DD +T 00 00 DD E5 DD 21 00 00 DD 39 F5 F5 DD 4E 04 DD R 00 00 00 00 -T 0E 00 77 FE DD 7E 05 DD 77 FF DD 7E 08 DD 86 FE +T 0E 00 46 05 DD 6E 08 DD 66 09 09 33 33 E5 DD 71 R 00 00 00 00 -T 1C 00 67 DD 7E 09 DD 8E FF DD 74 FC DD 77 FD C1 +T 1C 00 FE DD 70 FF R 00 00 00 00 -T 2A 00 D1 D5 C5 +T 20 00 R 00 00 00 00 -T 2D 00 +T 20 00 DD 7E FC DD 96 FE 20 08 DD 7E FD DD 96 FF R 00 00 00 00 -T 2D 00 DD 7E FC 93 20 06 DD 7E FD 92 28 1F +T 2E 00 28 27 R 00 00 00 00 -T 39 00 +T 30 00 R 00 00 00 00 -T 39 00 1A 47 0E 00 DD 7E 06 90 20 0C DD 7E 07 91 +T 30 00 DD 6E FE DD 66 FF 5E 16 00 DD 7E 06 93 20 R 00 00 00 00 -T 47 00 20 06 C1 E1 E5 C5 18 0C +T 3E 00 0A DD 7E 07 92 20 04 69 60 18 11 R 00 00 00 00 -T 4F 00 +T 49 00 R 00 00 00 00 -T 4F 00 13 DD 73 FE DD 72 FF 18 D5 +T 49 00 DD 34 FE 20 03 DD 34 FF R 00 00 00 00 -T 58 00 +T 51 00 R 00 00 00 00 -T 58 00 21 00 00 +T 51 00 D1 C1 C5 D5 18 C9 R 00 00 00 00 -T 5B 00 +T 57 00 R 00 00 00 00 -T 5B 00 DD F9 DD E1 C9 +T 57 00 21 00 00 R 00 00 00 00 -_memcmp.rel/ 1458795426 2001 2501 100664 1088 ` +T 5A 00 +R 00 00 00 00 +T 5A 00 DD F9 DD E1 C9 +R 00 00 00 00 + +_memcmp.rel/ 0 0 0 644 1048 ` XL2 H 9 areas 2 global symbols M _memcmp O -mz80 S .__.ABS. Def0000 -A _CODE size 78 flags 0 addr 0 +A _CODE size 72 flags 0 addr 0 S _memcmp Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -40165,74 +54874,35 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 DD E5 DD 21 00 00 DD 39 F5 DD 7E 09 DD B6 +T 00 00 DD E5 DD 21 00 00 DD 39 F5 F5 DD 7E 09 DD R 00 00 00 00 -T 0E 00 08 20 05 21 00 00 18 5D +T 0E 00 B6 08 20 05 21 00 00 18 56 R 00 00 00 00 -T 16 00 +T 17 00 R 00 00 00 00 -T 16 00 DD 5E 08 DD 56 09 +T 17 00 DD 4E 08 DD 46 09 R 00 00 00 00 -T 1C 00 +T 1D 00 R 00 00 00 00 -T 1C 00 1B 7A B3 28 3A DD 4E 04 DD 46 05 C5 FD E1 +T 1D 00 0B DD 5E 04 DD 56 05 DD 7E 06 DD 77 FD DD R 00 00 00 00 -T 2A 00 FD 7E 00 DD 77 FE DD 4E 06 DD 46 07 0A DD +T 2B 00 7E 07 DD 77 FE 1A DD 77 FF DD 6E FD DD 66 R 00 00 00 00 -T 38 00 77 FF DD 7E FE DD 96 FF 20 19 FD 23 FD E5 +T 39 00 FE 7E DD 77 FC 78 B1 28 1E DD 7E FF DD 96 R 00 00 00 00 -T 46 00 F1 DD 77 05 FD E5 3B F1 33 DD 77 04 03 DD +T 47 00 FC 20 16 13 DD 73 04 DD 72 05 DD 5E FD DD R 00 00 00 00 -T 54 00 71 06 DD 70 07 18 C1 +T 55 00 56 FE 13 DD 73 06 DD 72 07 18 BD R 00 00 00 00 -T 5B 00 +T 60 00 R 00 00 00 00 -T 5B 00 DD 6E 04 DD 66 05 5E 16 00 DD 6E 06 DD 66 +T 60 00 DD 6E FF 26 00 DD 4E FC 06 00 BF ED 42 R 00 00 00 00 -T 69 00 07 6E 26 00 7B 95 6F 7A 9C 67 +T 6D 00 R 00 00 00 00 -T 73 00 +T 6D 00 DD F9 DD E1 C9 R 00 00 00 00 -T 73 00 DD F9 DD E1 C9 -R 00 00 00 00 -_memcpy.rel/ 1458795426 2001 2501 100664 833 ` -XL2 -H 9 areas 2 global symbols -M _memcpy -O -mz80 -S .__.ABS. Def0000 -A _CODE size 4F flags 0 addr 0 -S _memcpy Def0000 -A _DATA size 0 flags 0 addr 0 -A _INITIALIZED size 0 flags 0 addr 0 -A _DABS size 0 flags 8 addr 0 -A _HOME size 0 flags 0 addr 0 -A _GSINIT size 0 flags 0 addr 0 -A _GSFINAL size 0 flags 0 addr 0 -A _INITIALIZER size 0 flags 0 addr 0 -A _CABS size 0 flags 8 addr 0 -T 00 00 -R 00 00 00 00 -T 00 00 DD E5 DD 21 00 00 DD 39 F5 F5 DD 7E 04 DD -R 00 00 00 00 -T 0E 00 77 FC DD 7E 05 DD 77 FD DD 7E 04 DD 77 FE -R 00 00 00 00 -T 1C 00 DD 7E 05 DD 77 FF DD 5E 06 DD 56 07 DD 4E -R 00 00 00 00 -T 2A 00 08 DD 46 09 -R 00 00 00 00 -T 2E 00 -R 00 00 00 00 -T 2E 00 61 68 0B 7D B4 28 13 1A 13 DD 6E FE DD 66 -R 00 00 00 00 -T 3C 00 FF 77 DD 34 FE 20 EB DD 34 FF 18 E6 -R 00 00 00 00 -T 48 00 -R 00 00 00 00 -T 48 00 E1 E5 DD F9 DD E1 C9 -R 00 00 00 00 - -_memset.rel/ 1458795426 2001 2501 100664 659 ` +_memset.rel/ 0 0 0 644 659 ` XL2 H 9 areas 2 global symbols M _memset @@ -40250,29 +54920,45 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 DD E5 DD 21 00 00 DD 39 DD 6E 04 DD 66 05 +T 00 00 DD E5 DD 21 00 00 DD 39 DD 5E 04 DD 56 05 R 00 00 00 00 T 0E 00 DD 4E 08 DD 46 09 R 00 00 00 00 T 14 00 R 00 00 00 00 -T 14 00 51 58 0B 7B B2 28 07 DD 7E 06 77 23 18 F2 +T 14 00 69 60 0B 7C B5 28 07 DD 7E 06 12 13 18 F2 R 00 00 00 00 T 22 00 R 00 00 00 00 T 22 00 DD 6E 04 DD 66 05 DD E1 C9 R 00 00 00 00 -_calloc.rel/ 1458795426 2001 2501 100664 795 ` +/134 0 0 0 644 363 ` +XL2 +H 9 areas 1 global symbols +M aligned_alloc +O -mz80 +S .__.ABS. Def0000 +A _CODE size 0 flags 0 addr 0 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 + +calloc.rel/ 0 0 0 644 828 ` XL2 H 9 areas 5 global symbols -M _calloc +M calloc O -mz80 S __mulint Ref0000 S _malloc Ref0000 S .__.ABS. Def0000 S _memset Ref0000 -A _CODE size 3A flags 0 addr 0 +A _CODE size 3E flags 0 addr 0 S _calloc Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -40288,27 +54974,29 @@ T 00 00 DD E5 DD 21 00 00 DD 39 DD 6E 06 DD 66 07 R 00 00 00 00 T 0E 00 E5 DD 6E 04 DD 66 05 E5 CD 00 00 F1 F1 EB R 00 00 00 00 02 0B 00 00 -T 1C 00 D5 D5 CD 00 00 F1 D1 7C B5 28 10 E5 D5 01 +T 1C 00 D5 D5 CD 00 00 F1 D1 4D 7C 47 B5 28 10 C5 R 00 00 00 00 02 05 01 00 -T 2A 00 00 00 C5 E5 CD 00 00 21 06 00 39 F9 E1 -R 00 00 00 00 02 07 03 00 -T 37 00 +T 2A 00 D5 21 00 00 E5 C5 CD 00 00 21 06 00 39 F9 +R 00 00 00 00 02 09 03 00 +T 38 00 C1 R 00 00 00 00 -T 37 00 DD E1 C9 +T 39 00 R 00 00 00 00 - -_malloc.rel/ 1458795426 2001 2501 100664 2329 ` +T 39 00 69 60 DD E1 C9 +R 00 00 00 00 +malloc.rel/ 0 0 0 644 2406 ` XL2 -H 9 areas 5 global symbols -M _malloc +H 9 areas 6 global symbols +M malloc O -mz80 +S ___sdcc_heap_end Ref0000 S .__.ABS. Def0000 -S __sdcc_heap_start Ref0000 -S __sdcc_heap_end Ref0000 -A _CODE size 133 flags 0 addr 0 -S _malloc Def0029 -S __sdcc_heap_init Def0000 -A _DATA size 0 flags 0 addr 0 +S ___sdcc_heap Ref0000 +A _CODE size 128 flags 0 addr 0 +S ___sdcc_heap_init Def0000 +S _malloc Def001B +A _DATA size 2 flags 0 addr 0 +S ___sdcc_heap_free Def0000 A _INITIALIZED size 0 flags 0 addr 0 A _DABS size 0 flags 8 addr 0 A _HOME size 0 flags 0 addr 0 @@ -40317,95 +55005,97 @@ A _GSFINAL size 0 flags 0 addr 0 A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 +R 00 00 01 00 +T 00 00 +R 00 00 01 00 +T 00 00 R 00 00 00 00 -T 00 00 21 00 00 11 00 00 BF ED 52 19 7D C6 FA 5F -R 00 00 00 00 02 03 02 00 02 06 01 00 -T 0E 00 7C CE FF 57 ED 53 00 00 3E 00 12 13 3E 00 -R 00 00 00 00 02 08 01 00 -T 1C 00 12 21 00 00 22 02 00 2E 00 22 04 00 C9 -R 00 00 00 00 02 07 01 00 02 0C 01 00 -T 29 00 +T 00 00 21 00 00 22 00 00 ED 4B 00 00 3E +R 00 00 00 00 02 03 02 00 00 06 01 00 00 0A 01 00 +T 0B 00 00 00 02 03 3E 00 00 02 2A 00 00 23 23 AF +R 00 00 00 00 0B 02 00 00 8B 07 00 00 00 0B 01 00 +T 17 00 77 23 77 C9 R 00 00 00 00 -T 29 00 DD E5 DD 21 00 00 DD 39 F5 3E F9 DD BE 04 +T 1B 00 R 00 00 00 00 -T 37 00 3E FF DD 9E 05 30 06 21 00 00 C3 2E 01 -R 00 00 00 00 00 0D 00 00 -T 44 00 +T 1B 00 DD E5 DD 21 00 00 DD 39 21 F8 FF 39 F9 DD R 00 00 00 00 -T 44 00 DD 7E 04 C6 06 DD 77 04 DD 7E 05 CE 00 DD +T 29 00 7E 05 DD B6 04 28 12 DD 4E 04 DD 46 05 03 R 00 00 00 00 -T 52 00 77 05 DD 36 FE 00 00 DD 36 FF 00 00 ED 57 -R 00 00 00 00 0B 07 01 00 8B 0C 01 00 -T 5E 00 F3 F5 +T 37 00 03 79 DD 96 04 78 DD 9E 05 30 06 R 00 00 00 00 -T 60 00 +T 42 00 R 00 00 00 00 -T 60 00 DD 6E FE DD 66 FF 5E 23 56 6B 62 DD 4E FE +T 42 00 21 00 00 C3 23 01 +R 00 00 00 00 00 06 00 00 +T 48 00 R 00 00 00 00 -T 6E 00 DD 46 FF 7D 91 4F 7C 98 47 DD 6E FE DD 66 +T 48 00 DD 71 04 DD 70 05 DD 7E 04 D6 04 DD 7E 05 R 00 00 00 00 -T 7C 00 FF 23 23 23 23 7E 23 66 6F 79 95 6F 78 9C +T 56 00 DE 00 30 08 DD 36 04 04 DD 36 05 00 R 00 00 00 00 -T 8A 00 67 7D DD 96 04 7C DD 9E 05 38 0E DD 7E FE +T 62 00 R 00 00 00 00 -T 98 00 C6 06 4F DD 7E FF CE 00 47 18 16 +T 62 00 ED 4B 00 00 DD 36 FE 00 00 DD 36 FF 00 00 +R 00 00 00 00 00 04 01 00 09 09 01 00 89 0E 01 00 +T 6E 00 R 00 00 00 00 -T A3 00 +T 6E 00 78 B1 CA 20 01 0A DD 77 FC 03 0A DD 77 FD +R 00 00 00 00 00 05 00 00 +T 7C 00 0B DD 6E FC DD 66 FD 59 50 BF ED 52 79 C6 R 00 00 00 00 -T A3 00 DD 73 FE DD 72 FF DD 6E FE DD 66 FF 5E 23 +T 8A 00 02 DD 77 FA 78 CE 00 DD 77 FB 7D DD 96 04 R 00 00 00 00 -T B1 00 56 7A B3 20 AA 01 00 00 +T 98 00 7C DD 9E 05 38 6A DD 7E 04 C6 04 DD 77 F8 R 00 00 00 00 -T B9 00 +T A6 00 DD 7E 05 CE 00 DD 77 F9 7D DD 96 F8 7C DD R 00 00 00 00 -T B9 00 78 B1 28 6A FD 21 04 00 C5 DD 4E FE DD 46 +T B4 00 9E F9 38 38 DD 6E 04 DD 66 05 19 5D 54 DD R 00 00 00 00 -T C7 00 FF FD 09 C1 FD 6E 00 FD 66 01 7C B5 20 0E +T C2 00 7E FC 77 23 DD 7E FD 77 D5 FD E1 FD 23 FD R 00 00 00 00 -T D5 00 DD 7E 04 FD 77 00 DD 7E 05 FD 77 01 18 44 +T D0 00 23 DD 6E FA DD 66 FB 7E 23 66 FD 77 00 FD R 00 00 00 00 -T E3 00 +T DE 00 74 01 DD 6E FE DD 66 FF 73 23 72 7B 02 03 R 00 00 00 00 -T E3 00 DD 4E FE DD 46 FF 09 4D 44 73 23 72 69 60 +T EC 00 7A 02 18 12 R 00 00 00 00 -T F1 00 23 23 DD 7E FE 77 23 DD 7E FF 77 DD 6E FE +T F0 00 R 00 00 00 00 -T FF 00 DD 66 FF 71 23 70 69 60 7E 23 66 6F 7A B3 +T F0 00 DD 6E FA DD 66 FB 4E 23 46 DD 6E FE DD 66 R 00 00 00 00 -T 0D 01 28 05 23 23 71 23 70 +T FE 00 FF 71 23 70 R 00 00 00 00 -T 14 01 +T 02 01 R 00 00 00 00 -T 14 01 21 04 00 09 DD 7E 04 77 23 DD 7E 05 77 21 +T 02 01 C1 E1 E5 C5 18 1B R 00 00 00 00 -T 22 01 06 00 09 4D 44 +T 08 01 R 00 00 00 00 -T 27 01 +T 08 01 DD 7E FA DD 77 FE DD 7E FB DD 77 FF DD 6E R 00 00 00 00 -T 27 01 F1 E2 2C 01 FB -R 00 00 00 00 00 04 00 00 -T 2C 01 +T 16 01 FA DD 66 FB 4E 23 46 C3 6E 00 +R 00 00 00 00 00 0A 00 00 +T 20 01 R 00 00 00 00 -T 2C 01 69 60 +T 20 01 21 00 00 R 00 00 00 00 -T 2E 01 +T 23 01 R 00 00 00 00 -T 2E 01 DD F9 DD E1 C9 +T 23 01 DD F9 DD E1 C9 R 00 00 00 00 - -_realloc.rel/ 1458795427 2001 2501 100664 2658 ` +realloc.rel/ 0 0 0 644 4974 ` XL2 -H 9 areas 8 global symbols -M _realloc +H 9 areas 7 global symbols +M realloc O -mz80 S _free Ref0000 S _memmove Ref0000 S _malloc Ref0000 S .__.ABS. Def0000 -S __sdcc_find_memheader Ref0000 S _memcpy Ref0000 -S __sdcc_prev_memheader Ref0000 -A _CODE size 174 flags 0 addr 0 +S ___sdcc_heap_free Ref0000 +A _CODE size 323 flags 0 addr 0 S _realloc Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -40417,152 +55107,187 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 DD E5 DD 21 00 00 DD 39 21 FA FF 39 F9 ED +T 00 00 DD E5 DD 21 00 00 DD 39 21 EE FF 39 F9 DD R 00 00 00 00 -T 0E 00 57 F3 F5 DD 6E 04 DD 66 05 E5 CD 00 00 F1 -R 00 00 00 00 02 0D 04 00 -T 1C 00 4D 44 78 B1 CA 5D 01 3E F9 DD BE 06 3E FF -R 00 00 00 00 00 07 00 00 -T 2A 00 DD 9E 07 30 06 11 00 00 C3 69 01 -R 00 00 00 00 00 0B 00 00 -T 35 00 +T 0E 00 7E 05 DD B6 04 20 0E DD 6E 06 DD 66 07 E5 R 00 00 00 00 -T 35 00 DD 7E 06 C6 06 DD 77 06 DD 7E 07 CE 00 DD +T 1C 00 CD 00 00 F1 C3 1E 03 +R 00 00 00 00 02 03 02 00 00 07 00 00 +T 23 00 R 00 00 00 00 -T 43 00 77 07 69 60 5E 23 56 DD 73 FA DD 72 FB 69 +T 23 00 DD 7E 07 DD B6 06 20 11 DD 6E 04 DD 66 05 R 00 00 00 00 -T 51 00 60 DD 7E FA 95 6F DD 7E FB 9C 67 79 C6 04 +T 31 00 E5 CD 00 00 F1 21 00 00 C3 1E 03 +R 00 00 00 00 02 04 00 00 00 0B 00 00 +T 3C 00 R 00 00 00 00 -T 5F 00 DD 77 FA 78 CE 00 DD 77 FB 7D DD 96 06 7C +T 3C 00 DD 36 F6 00 DD 36 F7 00 DD 36 F4 00 DD 36 R 00 00 00 00 -T 6D 00 DD 9E 07 38 18 DD 6E FA DD 66 FB DD 7E 06 +T 4A 00 F5 00 ED 4B 00 00 DD 36 FE 00 00 DD 36 FF +R 00 00 00 00 02 06 05 00 0B 0B 05 00 +T 57 00 00 00 +R 00 00 00 00 8B 02 05 00 +T 58 00 R 00 00 00 00 -T 7B 00 77 23 DD 7E 07 77 DD 5E 04 DD 56 05 C3 +T 58 00 78 B1 28 2D DD 5E 04 DD 56 05 79 93 78 9A R 00 00 00 00 -T 88 00 69 01 -R 00 00 00 00 00 02 00 00 -T 8A 00 +T 66 00 30 21 DD 71 F6 DD 70 F7 DD 7E FE DD 77 F4 R 00 00 00 00 -T 8A 00 3A 01 00 21 00 00 B6 CA 13 01 2A -R 00 00 00 00 02 03 06 00 02 06 06 00 00 0A 00 00 -T 95 00 00 00 7B 95 DD 77 FE 7A 9C DD 77 FF 2A -R 00 00 00 00 02 02 06 00 -T A2 00 00 00 DD 75 FC DD 74 FD DD 6E FC DD 66 FD -R 00 00 00 00 02 02 06 00 -T B0 00 11 04 00 19 5E 23 56 DD 7E FE 93 67 DD 7E +T 74 00 DD 7E FF DD 77 F5 03 03 60 DD 71 FE DD 74 R 00 00 00 00 -T BE 00 FF 9A 6F 7C DD 96 06 7D DD 9E 07 38 48 2A +T 82 00 FF 69 4E 23 46 18 CF R 00 00 00 00 -T CC 00 00 00 19 EB DD 6E FC DD 66 FD 73 23 72 69 -R 00 00 00 00 02 02 06 00 -T DA 00 60 7E 23 66 6F 23 23 73 23 72 DD 6E FA DD +T 89 00 R 00 00 00 00 -T E8 00 66 FB 7E 23 66 6F D5 FD E1 D5 E5 C5 FD E5 +T 89 00 DD 71 F8 DD 70 F9 DD 7E 07 DD B6 06 28 12 R 00 00 00 00 -T F6 00 CD 00 00 21 06 00 39 F9 D1 21 04 00 19 DD -R 00 00 00 00 02 03 01 00 -T 04 01 7E 06 77 23 DD 7E 07 77 21 06 00 19 EB 18 +T 97 00 DD 4E 06 DD 46 07 03 03 79 DD 96 06 78 DD R 00 00 00 00 -T 12 01 56 +T A5 00 9E 07 30 06 R 00 00 00 00 -T 13 01 +T A9 00 R 00 00 00 00 -T 13 01 DD 7E 06 C6 FA 6F DD 7E 07 CE FF 67 C5 E5 +T A9 00 21 00 00 C3 1E 03 +R 00 00 00 00 00 06 00 00 +T AF 00 R 00 00 00 00 -T 21 01 CD 00 00 F1 C1 EB 7A B3 28 3E FD 21 06 00 -R 00 00 00 00 02 03 02 00 -T 2F 01 FD 09 DD 6E FA DD 66 FB 46 23 66 78 C6 FA +T AF 00 DD 71 F2 DD 70 F3 DD 7E F2 D6 04 DD 7E F3 R 00 00 00 00 -T 3D 01 6F 7C CE FF 67 D5 E5 FD E5 D5 CD 00 00 21 -R 00 00 00 00 02 0D 05 00 -T 4B 01 06 00 39 F9 DD 6E 04 DD 66 05 E5 CD 00 00 -R 00 00 00 00 02 0E 00 00 -T 59 01 F1 D1 18 0C +T BD 00 DE 00 30 08 DD 36 F2 04 DD 36 F3 00 R 00 00 00 00 -T 5D 01 +T C9 00 R 00 00 00 00 -T 5D 01 DD 6E 06 DD 66 07 E5 CD 00 00 F1 EB +T C9 00 DD 4E 04 DD 46 05 0B 0B DD 71 FA DD 70 FB +R 00 00 00 00 +T D7 00 DD 6E FA DD 66 FB 4E 23 46 59 50 DD 7E FA +R 00 00 00 00 +T E5 00 DD 77 FC DD 7E FB DD 77 FD 7B DD 96 FC 5F +R 00 00 00 00 +T F3 00 7A DD 9E FD DD 73 F0 DD 77 F1 DD 7E F0 DD +R 00 00 00 00 +T 01 01 77 EE DD 7E F1 DD 77 EF DD 7E F7 DD B6 F6 +R 00 00 00 00 +T 0F 01 28 2F DD 6E F6 DD 66 F7 5E 23 56 DD 7E FA +R 00 00 00 00 +T 1D 01 93 20 20 DD 7E FB 92 20 1A DD 5E F6 DD 56 +R 00 00 00 00 +T 2B 01 F7 DD 7E FC 93 5F DD 7E FD 9A 57 DD 6E F0 +R 00 00 00 00 +T 39 01 DD 66 F1 19 33 33 E5 +R 00 00 00 00 +T 40 01 +R 00 00 00 00 +T 40 01 DD 7E F8 91 20 27 DD 7E F9 90 20 21 DD 6E +R 00 00 00 00 +T 4E 01 F8 DD 66 F9 4E 23 66 69 DD 4E F8 DD 46 F9 +R 00 00 00 00 +T 5C 01 BF ED 42 DD 7E EE 85 DD 77 EE DD 7E EF 8C +R 00 00 00 00 +T 6A 01 DD 77 EF +R 00 00 00 00 +T 6D 01 +R 00 00 00 00 +T 6D 01 DD 7E EE DD 96 F2 DD 7E EF DD 9E F3 DA +R 00 00 00 00 +T 7A 01 D0 02 DD 7E F7 DD B6 F6 CA 06 02 DD 6E F6 +R 00 00 00 00 00 02 00 00 00 0B 00 00 +T 88 01 DD 66 F7 4E 23 46 DD 7E FA 91 20 72 DD 7E +R 00 00 00 00 +T 96 01 FB 90 20 6C DD 7E F0 DD 96 F2 DD 7E F1 DD +R 00 00 00 00 +T A4 01 9E F3 38 0E DD 7E F2 DD 77 FC DD 7E F3 DD +R 00 00 00 00 +T B2 01 77 FD 18 0C +R 00 00 00 00 +T B6 01 +R 00 00 00 00 +T B6 01 DD 7E F0 DD 77 FC DD 7E F1 DD 77 FD +R 00 00 00 00 +T C2 01 +R 00 00 00 00 +T C2 01 DD 5E FA DD 56 FB DD 4E F6 DD 46 F7 DD 6E +R 00 00 00 00 +T D0 01 FC DD 66 FD E5 D5 C5 CD 00 00 21 06 00 39 +R 00 00 00 00 02 0A 01 00 +T DE 01 F9 DD 7E F6 DD 77 FA DD 7E F7 DD 77 FB DD +R 00 00 00 00 +T EC 01 6E F4 DD 66 F5 DD 7E F8 77 23 DD 7E F9 77 +R 00 00 00 00 +T FA 01 DD 7E F4 DD 77 FE DD 7E F5 DD 77 FF +R 00 00 00 00 +T 06 02 +R 00 00 00 00 +T 06 02 DD 7E F9 DD B6 F8 28 5D DD 6E FA DD 66 FB +R 00 00 00 00 +T 14 02 7E DD 77 FC 23 7E DD 77 FD DD 7E F8 DD 96 +R 00 00 00 00 +T 22 02 FC 20 46 DD 7E F9 DD 96 FD 20 3E DD 6E F8 +R 00 00 00 00 +T 30 02 DD 66 F9 4E 23 46 DD 6E FA DD 66 FB 71 23 +R 00 00 00 00 +T 3E 02 70 DD 7E F8 DD 77 FC DD 7E F9 DD 77 FD DD +R 00 00 00 00 +T 4C 02 6E FC DD 66 FD 23 23 7E DD 77 FC 23 7E DD +R 00 00 00 00 +T 5A 02 77 FD DD 6E FE DD 66 FF DD 7E FC 77 23 DD +R 00 00 00 00 +T 68 02 7E FD 77 +R 00 00 00 00 +T 6B 02 +R 00 00 00 00 +T 6B 02 DD 7E F2 C6 04 4F DD 7E F3 CE 00 47 DD 7E +R 00 00 00 00 +T 79 02 EE 91 DD 7E EF 98 38 45 DD 4E FA DD 46 FB +R 00 00 00 00 +T 87 02 DD 6E F2 DD 66 F3 09 4D 44 DD 6E FA DD 66 +R 00 00 00 00 +T 95 02 FB 5E 23 56 69 60 73 23 72 C5 FD E1 FD 23 +R 00 00 00 00 +T A3 02 FD 23 DD 6E FE DD 66 FF 5E 23 56 FD 73 00 +R 00 00 00 00 +T B1 02 FD 72 01 DD 6E FE DD 66 FF 71 23 70 DD 6E +R 00 00 00 00 +T BF 02 FA DD 66 FB 71 23 70 +R 00 00 00 00 +T C6 02 +R 00 00 00 00 +T C6 02 DD 6E FA DD 66 FB 23 23 18 4E +R 00 00 00 00 +T D0 02 +R 00 00 00 00 +T D0 02 DD 6E 06 DD 66 07 E5 CD 00 00 F1 4D 44 69 R 00 00 00 00 02 0A 02 00 -T 69 01 +T DE 02 78 67 B1 28 38 DD 5E F0 DD 56 F1 1B 1B 7B R 00 00 00 00 -T 69 01 F1 E2 6E 01 FB -R 00 00 00 00 00 04 00 00 -T 6E 01 +T EC 02 DD 96 06 7A DD 9E 07 38 06 DD 5E 06 DD 56 R 00 00 00 00 -T 6E 01 EB DD F9 DD E1 C9 +T FA 02 07 R 00 00 00 00 -_free.rel/ 1458795427 2001 2501 100664 1388 ` +T FB 02 +R 00 00 00 00 +T FB 02 E5 D5 DD 4E 04 DD 46 05 C5 E5 CD 00 00 21 +R 00 00 00 00 02 0D 04 00 +T 09 03 06 00 39 F9 DD 4E 04 DD 46 05 C5 CD 00 00 +R 00 00 00 00 02 0E 00 00 +T 17 03 F1 E1 18 03 +R 00 00 00 00 +T 1B 03 +R 00 00 00 00 +T 1B 03 21 00 00 +R 00 00 00 00 +T 1E 03 +R 00 00 00 00 +T 1E 03 DD F9 DD E1 C9 +R 00 00 00 00 +free.rel/ 0 0 0 644 1687 ` XL2 -H 9 areas 4 global symbols -M _free +H 9 areas 3 global symbols +M free O -mz80 S .__.ABS. Def0000 -A _CODE size 90 flags 0 addr 0 -S _free Def002C -S __sdcc_find_memheader Def0000 -A _DATA size 2 flags 0 addr 0 -S __sdcc_prev_memheader Def0000 -A _INITIALIZED size 0 flags 0 addr 0 -A _DABS size 0 flags 8 addr 0 -A _HOME size 0 flags 0 addr 0 -A _GSINIT size 0 flags 0 addr 0 -A _GSFINAL size 0 flags 0 addr 0 -A _INITIALIZER size 0 flags 0 addr 0 -A _CABS size 0 flags 8 addr 0 -T 00 00 -R 00 00 01 00 -T 00 00 -R 00 00 01 00 -T 00 00 -R 00 00 00 00 -T 00 00 21 03 00 39 7E 2B B6 20 04 21 00 00 C9 -R 00 00 00 00 -T 0D 00 -R 00 00 00 00 -T 0D 00 C1 D1 D5 C5 7B C6 FA 5F 7A CE FF 57 6B 62 -R 00 00 00 00 -T 1B 00 23 23 7E FD 21 00 00 FD 77 00 23 7E 32 -R 00 00 00 00 00 07 01 00 -T 28 00 01 00 EB C9 -R 00 00 00 00 00 02 01 00 -T 2C 00 -R 00 00 00 00 -T 2C 00 DD E5 DD 21 00 00 DD 39 F5 DD 7E 05 DD B6 -R 00 00 00 00 -T 3A 00 04 28 4E ED 57 F3 F5 DD 7E 04 DD 66 05 C6 -R 00 00 00 00 -T 48 00 FA 4F 7C CE FF 47 69 60 23 23 5E 23 56 7A -R 00 00 00 00 -T 56 00 B3 28 25 0A DD 77 FE 03 0A DD 77 FF 0B 6B -R 00 00 00 00 -T 64 00 62 DD 7E FE 77 23 DD 7E FF 77 69 60 7E 23 -R 00 00 00 00 -T 72 00 66 6F B4 28 0F 23 23 73 23 72 18 08 -R 00 00 00 00 -T 7E 00 -R 00 00 00 00 -T 7E 00 21 04 00 09 AF 77 23 77 -R 00 00 00 00 -T 86 00 -R 00 00 00 00 -T 86 00 F1 E2 8B 00 FB -R 00 00 00 00 00 04 00 00 -T 8B 00 -R 00 00 00 00 -T 8B 00 -R 00 00 00 00 -T 8B 00 DD F9 DD E1 C9 -R 00 00 00 00 -/134 1458795433 2001 2501 100664 17041 ` -XL2 -H 9 areas 4 global symbols -M printf_large -O -mz80 -S .__.ABS. Def0000 -S ___sdcc_call_hl Ref0000 -S _strlen Ref0000 -A _CODE size B32 flags 0 addr 0 -S __print_format Def0111 +S ___sdcc_heap_free Ref0000 +A _CODE size EA flags 0 addr 0 +S _free Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 A _DABS size 0 flags 8 addr 0 @@ -40573,661 +55298,1869 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 FD 21 02 00 FD 39 FD 7E 00 C6 30 67 3E 39 +T 00 00 DD E5 DD 21 00 00 DD 39 21 F8 FF 39 F9 DD R 00 00 00 00 -T 0E 00 94 30 14 7C C6 07 67 FD 21 03 00 FD 39 FD +T 0E 00 7E 05 DD B6 04 CA E5 00 21 00 00 E3 ED 5B +R 00 00 00 00 00 08 00 00 +T 1C 00 00 00 01 00 00 +R 00 00 00 00 02 02 01 00 02 05 01 00 +T 21 00 R 00 00 00 00 -T 1C 00 CB 00 46 28 04 7C C6 20 67 +T 21 00 7A B3 28 1A DD 6E 04 DD 66 05 7B 95 7A 9C +R 00 00 00 00 +T 2F 00 30 0E 33 33 D5 13 13 62 4B 44 6B 5E 23 56 +R 00 00 00 00 +T 3D 00 18 E2 +R 00 00 00 00 +T 3F 00 +R 00 00 00 00 +T 3F 00 DD 73 FA DD 72 FB DD 5E 04 DD 56 05 1B 1B +R 00 00 00 00 +T 4D 00 21 02 00 19 DD 75 FE DD 74 FF DD 6E FE DD +R 00 00 00 00 +T 5B 00 66 FF DD 7E FA 77 23 DD 7E FB 77 7B 02 03 +R 00 00 00 00 +T 69 00 7A 02 6B 62 4E 23 46 DD 7E FA 91 20 24 DD +R 00 00 00 00 +T 77 00 7E FB 90 20 1E 69 60 23 23 4E 23 46 DD 6E +R 00 00 00 00 +T 85 00 FE DD 66 FF 71 23 70 6B 62 4E 23 66 69 4E +R 00 00 00 00 +T 93 00 23 46 6B 62 71 23 70 +R 00 00 00 00 +T 9A 00 +R 00 00 00 00 +T 9A 00 DD 7E F9 DD B6 F8 28 43 E1 E5 4E 23 46 7B +R 00 00 00 00 +T A8 00 91 20 3A 7A 90 20 36 1A DD 77 FC 13 1A DD +R 00 00 00 00 +T B6 00 77 FD E1 E5 DD 7E FC 77 23 DD 7E FD 77 DD +R 00 00 00 00 +T C4 00 7E F8 C6 02 DD 77 FC DD 7E F9 CE 00 DD 77 +R 00 00 00 00 +T D2 00 FD DD 6E FE DD 66 FF 4E 23 46 DD 6E FC DD +R 00 00 00 00 +T E0 00 66 FD 71 23 70 +R 00 00 00 00 +T E5 00 +R 00 00 00 00 +T E5 00 DD F9 DD E1 C9 +R 00 00 00 00 + +mblen.rel/ 0 0 0 644 1253 ` +XL2 +H 9 areas 2 global symbols +M mblen +O -mz80 +S .__.ABS. Def0000 +A _CODE size 6E flags 0 addr 0 +S _mblen Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 DD E5 DD 21 00 00 DD 39 DD 7E 05 DD B6 04 +R 00 00 00 00 +T 0E 00 20 05 21 00 00 18 56 +R 00 00 00 00 +T 15 00 +R 00 00 00 00 +T 15 00 DD 7E 07 DD B6 06 20 05 21 FF FF 18 49 +R 00 00 00 00 +T 22 00 +R 00 00 00 00 +T 22 00 DD 6E 04 DD 66 05 4E 79 B7 20 05 21 00 00 +R 00 00 00 00 +T 30 00 18 39 +R 00 00 00 00 +T 32 00 +R 00 00 00 00 +T 32 00 3E 7F 91 38 05 21 01 00 18 2F +R 00 00 00 00 +T 3C 00 +R 00 00 00 00 +T 3C 00 1E 00 +R 00 00 00 00 +T 3E 00 +R 00 00 00 00 +T 3E 00 CB 79 28 05 CB 21 1C 18 F7 +R 00 00 00 00 +T 47 00 +R 00 00 00 00 +T 47 00 4B 06 00 DD 7E 06 91 DD 7E 07 98 30 05 21 +R 00 00 00 00 +T 55 00 FF FF 18 12 +R 00 00 00 00 +T 59 00 +R 00 00 00 00 +T 59 00 +R 00 00 00 00 +T 59 00 1D 28 0D 23 7E E6 C0 D6 80 28 F5 21 FF FF +R 00 00 00 00 +T 67 00 18 02 +R 00 00 00 00 +T 69 00 +R 00 00 00 00 +T 69 00 69 60 +R 00 00 00 00 +T 6B 00 +R 00 00 00 00 +T 6B 00 DD E1 C9 +R 00 00 00 00 + +mbtowc.rel/ 0 0 0 644 2425 ` +XL2 +H 9 areas 2 global symbols +M mbtowc +O -mz80 +S .__.ABS. Def0000 +A _CODE size 129 flags 0 addr 0 +S _mbtowc Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 DD E5 DD 21 00 00 DD 39 21 F6 FF 39 F9 DD +R 00 00 00 00 +T 0E 00 7E 07 DD B6 06 20 06 21 00 00 C3 24 01 +R 00 00 00 00 00 0D 00 00 +T 1B 00 +R 00 00 00 00 +T 1B 00 DD 36 FB 01 DD 4E 06 DD 46 07 0A 5F CB 7B +R 00 00 00 00 +T 29 00 28 2B 2E 01 +R 00 00 00 00 +T 2D 00 +R 00 00 00 00 +T 2D 00 7D F5 16 80 F1 3C 18 02 +R 00 00 00 00 +T 35 00 +R 00 00 00 00 +T 35 00 CB 3A +R 00 00 00 00 +T 37 00 +R 00 00 00 00 +T 37 00 3D 20 FB 7B A2 28 03 2C 18 EC +R 00 00 00 00 +T 41 00 +R 00 00 00 00 +T 41 00 DD 75 FB 26 00 23 F5 16 FF F1 2C 18 02 +R 00 00 00 00 +T 4E 00 +R 00 00 00 00 +T 4E 00 CB 3A +R 00 00 00 00 +T 50 00 +R 00 00 00 00 +T 50 00 2D 20 FB 7B A2 5F +R 00 00 00 00 +T 56 00 +R 00 00 00 00 +T 56 00 DD 56 FB 2E 00 DD 7E 08 92 DD 7E 09 9D 30 +R 00 00 00 00 +T 64 00 06 21 FF FF C3 24 01 +R 00 00 00 00 00 07 00 00 +T 6B 00 +R 00 00 00 00 +T 6B 00 16 01 +R 00 00 00 00 +T 6D 00 +R 00 00 00 00 +T 6D 00 7A DD 96 FB 30 14 6A 26 00 09 7E E6 C0 D6 +R 00 00 00 00 +T 7B 00 80 28 06 21 FF FF C3 24 01 +R 00 00 00 00 00 09 00 00 +T 84 00 +R 00 00 00 00 +T 84 00 14 18 E6 +R 00 00 00 00 +T 87 00 +R 00 00 00 00 +T 87 00 DD 73 FC DD 36 FD 00 DD 36 FE 00 DD 36 FF +R 00 00 00 00 +T 95 00 00 03 DD 71 06 DD 70 07 DD 7E FB C6 FF DD +R 00 00 00 00 +T A3 00 77 FA DD 6E 06 DD 66 07 +R 00 00 00 00 +T AB 00 +R 00 00 00 00 +T AB 00 DD 7E FA B7 28 4D DD 4E FC DD 46 FD DD 5E +R 00 00 00 00 +T B9 00 FE DD 56 FF 3E 06 +R 00 00 00 00 +T BF 00 +R 00 00 00 00 +T BF 00 CB 21 CB 10 CB 13 CB 12 3D 20 F5 7E E6 3F +R 00 00 00 00 +T CD 00 DD 77 F6 DD 36 F7 00 DD 36 F8 00 DD 36 F9 +R 00 00 00 00 +T DB 00 00 79 DD B6 F6 DD 77 FC 78 DD B6 F7 DD 77 +R 00 00 00 00 +T E9 00 FD 7B DD B6 F8 DD 77 FE 7A DD B6 F9 DD 77 +R 00 00 00 00 +T F7 00 FF 23 DD 35 FA 18 AD +R 00 00 00 00 +T FE 00 +R 00 00 00 00 +T FE 00 DD 5E 04 DD 56 05 21 06 00 39 01 04 00 ED +R 00 00 00 00 +T 0C 01 B0 DD 7E FF DD B6 FE DD B6 FD DD B6 FC 28 +R 00 00 00 00 +T 1A 01 05 DD 6E FB 18 02 +R 00 00 00 00 +T 20 01 +R 00 00 00 00 +T 20 01 2E 00 +R 00 00 00 00 +T 22 01 +R 00 00 00 00 +T 22 01 26 00 +R 00 00 00 00 +T 24 01 +R 00 00 00 00 +T 24 01 DD F9 DD E1 C9 +R 00 00 00 00 + +wctomb.rel/ 0 0 0 644 2353 ` +XL2 +H 9 areas 2 global symbols +M wctomb +O -mz80 +S .__.ABS. Def0000 +A _CODE size 169 flags 0 addr 0 +S _wctomb Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 DD E5 DD 21 00 00 DD 39 21 F4 FF 39 F9 DD +R 00 00 00 00 +T 0E 00 7E 05 DD B6 04 20 06 21 00 00 C3 64 01 +R 00 00 00 00 00 0D 00 00 +T 1B 00 +R 00 00 00 00 +T 1B 00 DD 5E 04 DD 56 05 DD 7E 06 D6 80 DD 7E 07 +R 00 00 00 00 +T 29 00 DE 00 DD 7E 08 DE 00 DD 7E 09 DE 00 30 0A +R 00 00 00 00 +T 37 00 DD 7E 06 12 21 01 00 C3 64 01 +R 00 00 00 00 00 0A 00 00 +T 41 00 +R 00 00 00 00 +T 41 00 DD 7E 06 DD 77 FC DD 7E 07 DD 77 FD DD 7E +R 00 00 00 00 +T 4F 00 08 DD 77 FE DD 7E 09 DD 77 FF 06 06 +R 00 00 00 00 +T 5B 00 +R 00 00 00 00 +T 5B 00 DD CB FF 3E DD CB FE 1E DD CB FD 1E DD CB +R 00 00 00 00 +T 69 00 FC 1E 10 EE DD 4E 06 7B C6 01 DD 77 FA 7A +R 00 00 00 00 +T 77 00 CE 00 DD 77 FB 79 E6 3F CB FF DD 77 F9 DD +R 00 00 00 00 +T 85 00 7E 07 D6 08 DD 7E 08 DE 00 DD 7E 09 DE 00 +R 00 00 00 00 +T 93 00 30 19 DD 7E FC E6 1F 4F F6 C0 12 DD 6E FA +R 00 00 00 00 +T A1 00 DD 66 FB DD 7E F9 77 21 02 00 C3 64 01 +R 00 00 00 00 00 0D 00 00 +T AE 00 +R 00 00 00 00 +T AE 00 DD 7E 07 DD 77 F5 DD 7E 08 DD 77 F6 DD 7E +R 00 00 00 00 +T BC 00 09 DD 77 F7 DD 36 F8 00 06 04 +R 00 00 00 00 +T C6 00 +R 00 00 00 00 +T C6 00 DD CB F7 3E DD CB F6 1E DD CB F5 1E 10 F2 +R 00 00 00 00 +T D4 00 DD 7E FC E6 3F 4F 7B C6 02 DD 77 FC 7A CE +R 00 00 00 00 +T E2 00 00 DD 77 FD 79 CB FF DD 77 F4 DD 7E 08 D6 +R 00 00 00 00 +T F0 00 01 DD 7E 09 DE 00 30 21 DD 7E F5 E6 0F F6 +R 00 00 00 00 +T FE 00 E0 12 DD 6E FA DD 66 FB DD 7E F4 77 DD 6E +R 00 00 00 00 +T 0C 01 FC DD 66 FD DD 7E F9 77 21 03 00 18 4B +R 00 00 00 00 +T 19 01 +R 00 00 00 00 +T 19 01 DD 7E 08 D6 11 DD 7E 09 DE 00 30 3C DD 4E +R 00 00 00 00 +T 27 01 08 DD 46 09 3E 02 +R 00 00 00 00 +T 2D 01 +R 00 00 00 00 +T 2D 01 CB 38 CB 19 3D 20 F9 79 E6 07 F6 F0 12 DD +R 00 00 00 00 +T 3B 01 7E F5 E6 3F CB FF 4F DD 6E FA DD 66 FB 71 +R 00 00 00 00 +T 49 01 DD 6E FC DD 66 FD DD 7E F4 77 13 13 13 62 +R 00 00 00 00 +T 57 01 6B DD 7E F9 77 21 04 00 18 03 +R 00 00 00 00 +T 61 01 +R 00 00 00 00 +T 61 01 21 FF FF +R 00 00 00 00 +T 64 01 +R 00 00 00 00 +T 64 01 DD F9 DD E1 C9 +R 00 00 00 00 + +mbstowcs.rel/ 0 0 0 644 1207 ` +XL2 +H 9 areas 3 global symbols +M mbstowcs +O -mz80 +S .__.ABS. Def0000 +S _mbtowc Ref0000 +A _CODE size 86 flags 0 addr 0 +S _mbstowcs Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 DD E5 DD 21 00 00 DD 39 F5 F5 DD 36 FE 00 +R 00 00 00 00 +T 0E 00 DD 36 FF 00 DD 6E 04 DD 66 05 DD 36 FC 00 +R 00 00 00 00 +T 1C 00 DD 36 FD 00 DD 4E 08 DD 46 09 +R 00 00 00 00 +T 26 00 +R 00 00 00 00 +T 26 00 59 50 0B 7A B3 28 50 E5 FD E1 11 04 00 19 +R 00 00 00 00 +T 34 00 E5 C5 11 04 00 D5 DD 5E 06 DD 56 07 D5 FD +R 00 00 00 00 +T 42 00 E5 CD 00 00 F1 F1 F1 EB C1 E1 7A B3 28 2D +R 00 00 00 00 02 04 01 00 +T 50 00 CB 7A 28 05 21 FF FF 18 28 +R 00 00 00 00 +T 59 00 +R 00 00 00 00 +T 59 00 DD 7E 06 83 DD 77 06 DD 7E 07 8A DD 77 07 +R 00 00 00 00 +T 67 00 DD 34 FC 20 03 DD 34 FD +R 00 00 00 00 +T 6F 00 +R 00 00 00 00 +T 6F 00 DD 7E FC DD 77 FE DD 7E FD DD 77 FF 18 A9 +R 00 00 00 00 +T 7D 00 +R 00 00 00 00 +T 7D 00 C1 E1 E5 C5 +R 00 00 00 00 +T 81 00 +R 00 00 00 00 +T 81 00 DD F9 DD E1 C9 +R 00 00 00 00 + +wcstombs.rel/ 0 0 0 644 1616 ` +XL2 +H 9 areas 3 global symbols +M wcstombs +O -mz80 +S .__.ABS. Def0000 +S _wctomb Ref0000 +A _CODE size D3 flags 0 addr 0 +S _wcstombs Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 DD E5 DD 21 00 00 DD 39 21 F8 FF 39 F9 DD +R 00 00 00 00 +T 0E 00 36 FC 00 DD 36 FD 00 21 00 00 39 DD 75 FE +R 00 00 00 00 +T 1C 00 DD 74 FF DD 4E 06 DD 46 07 R 00 00 00 00 T 25 00 R 00 00 00 00 -T 25 00 FD 21 06 00 FD 39 FD 4E 00 FD 46 01 C5 E5 +T 25 00 3E 04 DD BE 08 3E 00 DD 9E 09 38 2C 69 60 R 00 00 00 00 -T 33 00 33 21 07 00 39 7E 23 66 6F CD 00 00 F1 33 -R 00 00 00 00 02 0C 01 00 -T 41 00 C9 +T 33 00 5E 23 56 23 23 7E 2B 6E 67 E5 DD 6E FE DD R 00 00 00 00 +T 41 00 66 FF E5 FD E1 E1 C5 E5 D5 FD E5 CD 00 00 +R 00 00 00 00 02 0E 01 00 +T 4F 00 F1 F1 F1 C1 DD 7E 08 95 DD 7E 09 9C 38 6B +R 00 00 00 00 +T 5D 00 +R 00 00 00 00 +T 5D 00 69 60 5E 23 56 23 23 7E 2B 6E 67 C5 E5 D5 +R 00 00 00 00 +T 6B 00 DD 6E 04 DD 66 05 E5 CD 00 00 F1 F1 F1 EB +R 00 00 00 00 02 0A 01 00 +T 79 00 C1 7B 3D 20 0E 7A B7 20 0A DD 6E 04 DD 66 +R 00 00 00 00 +T 87 00 05 7E B7 28 3C +R 00 00 00 00 +T 8C 00 +R 00 00 00 00 +T 8C 00 CB 7A 28 05 21 FF FF 18 39 +R 00 00 00 00 +T 95 00 +R 00 00 00 00 +T 95 00 6B 62 DD 7E 08 95 DD 77 08 DD 7E 09 9C DD +R 00 00 00 00 +T A3 00 77 09 DD 7E FC 85 DD 77 FC DD 7E FD 8C DD +R 00 00 00 00 +T B1 00 77 FD DD 7E 04 83 DD 77 04 DD 7E 05 8A DD +R 00 00 00 00 +T BF 00 77 05 03 03 03 03 C3 25 00 +R 00 00 00 00 00 09 00 00 +T C8 00 +R 00 00 00 00 +T C8 00 DD 6E FC DD 66 FD +R 00 00 00 00 +T CE 00 +R 00 00 00 00 +T CE 00 DD F9 DD E1 C9 +R 00 00 00 00 +mbrtoc16.rel/ 0 0 0 644 3241 ` +XL2 +H 9 areas 3 global symbols +M mbrtoc16 +O -mz80 +S _mbrtowc Ref0000 +S .__.ABS. Def0000 +A _CODE size 1E4 flags 0 addr 0 +S _mbrtoc16 Def0000 +A _DATA size 3 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 01 00 +T 00 00 +R 00 00 01 00 +T 00 00 +R 00 00 00 00 +T 00 00 DD E5 DD 21 00 00 DD 39 21 F0 FF 39 F9 DD +R 00 00 00 00 +T 0E 00 7E 07 DD B6 06 20 1D DD 6E 0A DD 66 0B E5 +R 00 00 00 00 +T 1C 00 21 01 00 E5 21 E3 01 E5 21 00 00 E5 CD +R 00 00 00 00 00 07 00 00 +T 29 00 00 00 F1 F1 F1 F1 C3 DE 01 +R 00 00 00 00 00 02 00 00 00 09 00 00 +T 32 00 +R 00 00 00 00 +T 32 00 DD 7E 0B DD B6 0A 20 08 DD 36 0A 00 00 DD +R 00 00 00 00 09 0D 01 00 +T 3F 00 36 0B 00 00 +R 00 00 00 00 89 04 01 00 T 42 00 R 00 00 00 00 -T 42 00 DD E5 DD 21 00 00 DD 39 DD 7E 04 07 07 07 +T 42 00 DD 4E 0A DD 46 0B 0A 5F DD 7E 04 DD 77 FA R 00 00 00 00 -T 50 00 07 E6 0F 57 DD 6E 08 DD 66 09 E5 DD 6E 06 +T 50 00 DD 7E 05 DD 77 FB 21 01 00 09 DD 75 FC DD R 00 00 00 00 -T 5E 00 DD 66 07 E5 DD 7E 05 F5 33 D5 33 CD 00 00 -R 00 00 00 00 00 0E 00 00 -T 6C 00 21 06 00 39 F9 DD 7E 04 E6 0F 57 DD 6E 08 +T 5E 00 74 FD 21 02 00 09 DD 75 F8 DD 74 F9 7B B7 R 00 00 00 00 -T 7A 00 DD 66 09 E5 DD 6E 06 DD 66 07 E5 DD 7E 05 +T 6C 00 20 5B DD 6E FC DD 66 FD 7E B7 20 0A DD 6E R 00 00 00 00 -T 88 00 F5 33 D5 33 CD 00 00 21 06 00 39 F9 DD E1 -R 00 00 00 00 00 07 00 00 -T 96 00 C9 +T 7A 00 F8 DD 66 F9 7E B7 28 47 R 00 00 00 00 -T 97 00 +T 82 00 R 00 00 00 00 -T 97 00 DD E5 DD 21 00 00 DD 39 21 F9 FF 39 F9 DD +T 82 00 DD 6E 0A DD 66 0B 4D 44 03 EB 13 13 DD 7E R 00 00 00 00 -T A5 00 5E 04 DD 56 05 D5 21 03 00 39 EB 01 04 00 +T 90 00 05 DD B6 04 28 29 0A DD 77 FE DD 36 FF 00 R 00 00 00 00 -T B3 00 ED B0 D1 21 04 00 19 4D 44 DD 36 F9 20 +T 9E 00 1A 67 2E 00 DD 7E FE 85 DD 77 FE DD 7E FF R 00 00 00 00 -T C0 00 +T AC 00 8C DD 77 FF DD 6E FA DD 66 FB DD 7E FE 77 R 00 00 00 00 -T C0 00 0A 87 DD 77 FE DD 7E FD CB 07 E6 01 DD 77 +T BA 00 23 DD 7E FF 77 R 00 00 00 00 -T CE 00 FF DD 7E FE DD B6 FF 02 F5 F1 DD CB FA 26 +T BF 00 R 00 00 00 00 -T DC 00 DD CB FB 16 DD CB FC 16 DD CB FD 16 0A 67 +T BF 00 AF 12 AF 02 21 FD FF C3 DE 01 +R 00 00 00 00 00 0A 00 00 +T C9 00 R 00 00 00 00 -T EA 00 DD 96 06 38 09 7C DD 96 06 02 DD CB FA C6 +T C9 00 21 04 00 39 C5 DD 5E 0A DD 56 0B D5 DD 5E R 00 00 00 00 -T F8 00 +T D7 00 08 DD 56 09 D5 DD 5E 06 DD 56 07 D5 E5 CD R 00 00 00 00 -T F8 00 DD 7E F9 C6 FF DD 77 F9 B7 20 BD 21 01 00 +T E5 00 00 00 F1 F1 F1 F1 C1 DD 75 F2 DD 74 F3 3E +R 00 00 00 00 02 02 00 00 +T F3 00 04 DD BE F2 3E 00 DD 9E F3 30 07 C1 E1 E5 R 00 00 00 00 -T 06 01 39 01 04 00 ED B0 DD F9 DD E1 C9 -R 00 00 00 00 -T 11 01 -R 00 00 00 00 -T 11 01 DD E5 DD 21 00 00 DD 39 21 CA FF 39 F9 DD -R 00 00 00 00 -T 1F 01 36 EB 00 DD 36 EC 00 21 0D 00 39 DD 75 F2 -R 00 00 00 00 -T 2D 01 DD 74 F3 21 05 00 39 DD 75 E2 DD 74 E3 21 -R 00 00 00 00 -T 3B 01 0D 00 39 DD 75 E9 DD 74 EA DD 7E E9 C6 04 -R 00 00 00 00 -T 49 01 DD 77 E5 DD 7E EA CE 00 DD 77 E6 -R 00 00 00 00 -T 54 01 -R 00 00 00 00 -T 54 01 DD 6E 08 DD 66 09 56 23 DD 75 08 DD 74 09 -R 00 00 00 00 -T 62 01 DD 72 E4 7A B7 CA 1C 0B DD 7E E4 D6 25 C2 -R 00 00 00 00 00 08 00 00 -T 70 01 F9 0A DD 36 DD 00 DD 36 D6 00 DD 36 D5 00 -R 00 00 00 00 00 02 00 00 -T 7E 01 DD 36 E1 00 DD 36 DF 00 DD 36 DE 00 DD 36 -R 00 00 00 00 -T 8C 01 D1 00 DD 36 D0 00 DD 36 D4 00 DD 36 ED 00 -R 00 00 00 00 -T 9A 01 DD 36 D3 FF DD 7E 08 DD 77 FC DD 7E 09 DD -R 00 00 00 00 -T A8 01 77 FD -R 00 00 00 00 -T AA 01 -R 00 00 00 00 -T AA 01 DD 6E FC DD 66 FD 7E DD 77 FE DD 34 FC 20 -R 00 00 00 00 -T B8 01 03 DD 34 FD -R 00 00 00 00 -T BC 01 -R 00 00 00 00 -T BC 01 DD 7E FC DD 77 08 DD 7E FD DD 77 09 DD 7E -R 00 00 00 00 -T CA 01 FE D6 25 20 23 DD 6E 06 DD 66 07 E5 DD 7E -R 00 00 00 00 -T D8 01 FE F5 33 DD 6E 04 DD 66 05 CD 00 00 F1 33 -R 00 00 00 00 02 0C 01 00 -T E6 01 DD 34 EB C2 54 01 DD 34 EC C3 54 01 -R 00 00 00 00 00 06 00 00 00 0C 00 00 -T F2 01 -R 00 00 00 00 -T F2 01 DD 66 FE 7C D6 30 38 3B 3E 39 94 38 36 DD -R 00 00 00 00 -T 00 02 7E D3 3C 20 1C DD 7E ED 4F 87 87 81 87 DD -R 00 00 00 00 -T 0E 02 77 FF DD 86 FE C6 D0 DD 77 ED B7 20 8F DD -R 00 00 00 00 -T 1C 02 36 D6 01 18 89 -R 00 00 00 00 -T 21 02 -R 00 00 00 00 -T 21 02 DD 6E D3 4D 29 29 09 29 7D DD 86 FE C6 D0 -R 00 00 00 00 -T 2F 02 DD 77 D3 C3 AA 01 -R 00 00 00 00 00 06 00 00 -T 35 02 -R 00 00 00 00 -T 35 02 DD 7E FE D6 2E 20 0E DD 7E D3 3C C2 AA 01 -R 00 00 00 00 00 0E 00 00 -T 43 02 DD 36 D3 00 C3 AA 01 -R 00 00 00 00 00 07 00 00 -T 4A 02 -R 00 00 00 00 -T 4A 02 DD 6E FE 7D D6 61 38 0F 3E 7A 95 38 0A DD -R 00 00 00 00 -T 58 02 CB FE AE DD 36 DC 01 18 04 -R 00 00 00 00 -T 61 02 -R 00 00 00 00 -T 61 02 DD 36 DC 00 -R 00 00 00 00 -T 65 02 -R 00 00 00 00 -T 65 02 DD 7E FE D6 20 CA 04 03 DD 7E FE D6 2B CA -R 00 00 00 00 00 08 00 00 -T 73 02 FD 02 DD 7E FE D6 2D 28 7A DD 7E FE D6 42 -R 00 00 00 00 00 02 00 00 -T 81 02 CA 0B 03 DD 7E FE D6 43 CA 19 03 DD 7E FE -R 00 00 00 00 00 03 00 00 00 0B 00 00 -T 8F 02 D6 44 CA 2E 05 DD 7E FE D6 46 CA 4A 05 DD -R 00 00 00 00 00 05 00 00 00 0D 00 00 -T 9D 02 7E FE D6 48 CA AA 01 DD 7E FE D6 49 CA -R 00 00 00 00 00 07 00 00 -T AA 02 2E 05 DD 7E FE D6 4A CA AA 01 DD 7E FE D6 -R 00 00 00 00 00 02 00 00 00 0A 00 00 -T B8 02 4C 28 57 DD 7E FE D6 4F CA 38 05 DD 7E FE -R 00 00 00 00 00 0B 00 00 -T C6 02 D6 50 CA 85 04 DD 7E FE D6 53 CA 63 03 DD -R 00 00 00 00 00 05 00 00 00 0D 00 00 -T D4 02 7E FE D6 54 CA AA 01 DD 7E FE D6 55 CA -R 00 00 00 00 00 07 00 00 -T E1 02 3E 05 DD 7E FE D6 58 CA 44 05 DD 7E FE D6 -R 00 00 00 00 00 02 00 00 00 0A 00 00 -T EF 02 5A CA AA 01 C3 50 05 -R 00 00 00 00 00 04 00 00 00 07 00 00 -T F6 02 -R 00 00 00 00 -T F6 02 DD 36 DD 01 C3 AA 01 -R 00 00 00 00 00 07 00 00 -T FD 02 -R 00 00 00 00 -T FD 02 DD 36 D5 01 C3 AA 01 -R 00 00 00 00 00 07 00 00 -T 04 03 -R 00 00 00 00 -T 04 03 DD 36 E1 01 C3 AA 01 -R 00 00 00 00 00 07 00 00 -T 0B 03 -R 00 00 00 00 -T 0B 03 DD 36 DE 01 C3 AA 01 -R 00 00 00 00 00 07 00 00 -T 12 03 -R 00 00 00 00 -T 12 03 DD 36 D1 01 C3 AA 01 -R 00 00 00 00 00 07 00 00 -T 19 03 -R 00 00 00 00 -T 19 03 DD CB DE 46 28 11 DD 6E 0A DD 66 0B 23 DD -R 00 00 00 00 -T 27 03 75 0A DD 74 0B 2B 56 18 13 -R 00 00 00 00 -T 30 03 -R 00 00 00 00 -T 30 03 DD 6E 0A DD 66 0B 23 23 DD 75 0A DD 74 0B -R 00 00 00 00 -T 3E 03 2B 2B 56 23 66 -R 00 00 00 00 -T 43 03 -R 00 00 00 00 -T 43 03 DD 6E 06 DD 66 07 E5 D5 33 DD 6E 04 DD 66 -R 00 00 00 00 -T 51 03 05 CD 00 00 F1 33 DD 34 EB C2 7A 05 DD 34 -R 00 00 00 00 02 04 01 00 00 0C 00 00 -T 5F 03 EC C3 7A 05 +T 01 01 C5 C3 DE 01 R 00 00 00 00 00 04 00 00 -T 63 03 +T 05 01 R 00 00 00 00 -T 63 03 21 0D 00 39 DD 75 FC DD 74 FD DD 6E 0A DD +T 05 01 DD 7E F4 D6 FF DD 7E F5 DE D7 DD 7E F6 DE R 00 00 00 00 -T 71 03 66 0B 23 23 DD 75 0A DD 74 0B 2B 2B 5E 23 +T 13 01 00 DD 7E F7 DE 00 38 25 DD 7E F5 D6 E0 DD R 00 00 00 00 -T 7F 03 56 DD 6E FC DD 66 FD 73 23 72 D5 CD 00 00 +T 21 01 7E F6 DE 00 DD 7E F7 DE 00 38 32 3E FF DD +R 00 00 00 00 +T 2F 01 BE F4 DD 9E F5 3E 00 DD 9E F6 3E 00 DD 9E +R 00 00 00 00 +T 3D 01 F7 38 1E +R 00 00 00 00 +T 40 01 +R 00 00 00 00 +T 40 01 DD 7E 05 DD B6 04 28 0F DD 4E F4 DD 46 F5 +R 00 00 00 00 +T 4E 01 DD 6E FA DD 66 FB 71 23 70 +R 00 00 00 00 +T 57 01 +R 00 00 00 00 +T 57 01 C1 E1 E5 C5 C3 DE 01 +R 00 00 00 00 00 07 00 00 +T 5E 01 +R 00 00 00 00 +T 5E 01 DD 7E F4 C6 00 DD 77 F4 DD 7E F5 CE 00 DD +R 00 00 00 00 +T 6C 01 77 F5 DD 7E F6 CE F0 DD 77 F6 DD 7E F7 CE +R 00 00 00 00 +T 7A 01 FF DD 77 F7 DD 7E 05 DD B6 04 28 26 DD 5E +R 00 00 00 00 +T 88 01 F5 DD 56 F6 DD 6E F7 3E 02 +R 00 00 00 00 +T 91 01 +R 00 00 00 00 +T 91 01 CB 3D CB 1A CB 1B 3D 20 F7 7A E6 03 57 21 +R 00 00 00 00 +T 9F 01 00 D8 19 EB DD 6E FA DD 66 FB 73 23 72 +R 00 00 00 00 +T AC 01 +R 00 00 00 00 +T AC 01 DD 5E F4 DD 7E F5 E6 03 57 21 00 DC 19 E3 +R 00 00 00 00 +T BA 01 AF 02 DD 4E F0 DD 6E FC DD 66 FD 71 DD 7E +R 00 00 00 00 +T C8 01 F1 DD 77 FE DD 36 FF 00 DD 4E FE DD 6E F8 +R 00 00 00 00 +T D6 01 DD 66 F9 71 C1 E1 E5 C5 +R 00 00 00 00 +T DE 01 +R 00 00 00 00 +T DE 01 DD F9 DD E1 C9 +R 00 00 00 00 +T E3 01 +R 00 00 00 00 +T E3 01 00 +R 00 00 00 00 + +c16rtomb.rel/ 0 0 0 644 1322 ` +XL2 +H 9 areas 3 global symbols +M c16rtomb +O -mz80 +S .__.ABS. Def0000 +S _wctomb Ref0000 +A _CODE size 8F flags 0 addr 0 +S _c16rtomb Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 DD E5 DD 21 00 00 DD 39 F5 DD 5E 08 DD 56 +R 00 00 00 00 +T 0E 00 09 21 01 00 19 E3 E1 E5 4E 13 13 1A 6F 79 +R 00 00 00 00 +T 1C 00 B7 20 03 B5 28 2C +R 00 00 00 00 +T 22 00 +R 00 00 00 00 +T 22 00 06 00 65 2E 00 09 4D AF 12 E1 E5 36 00 79 +R 00 00 00 00 +T 30 00 87 87 47 0E 00 DD 6E 06 DD 66 07 09 11 +R 00 00 00 00 +T 3D 00 00 00 4D 7C C6 24 47 7B CE 00 5F 7A CE 00 +R 00 00 00 00 +T 4B 00 57 18 2D +R 00 00 00 00 +T 4E 00 +R 00 00 00 00 +T 4E 00 DD 7E 06 D6 FF DD 7E 07 DE D7 38 07 DD 7E +R 00 00 00 00 +T 5C 00 07 D6 E0 38 0B +R 00 00 00 00 +T 61 00 +R 00 00 00 00 +T 61 00 DD 4E 06 DD 46 07 11 00 00 18 0F +R 00 00 00 00 +T 6C 00 +R 00 00 00 00 +T 6C 00 DD 4E 06 E1 E5 71 DD 7E 07 12 21 00 00 18 +R 00 00 00 00 +T 7A 00 0F +R 00 00 00 00 +T 7B 00 +R 00 00 00 00 +T 7B 00 D5 C5 DD 6E 04 DD 66 05 E5 CD 00 00 F1 F1 +R 00 00 00 00 02 0C 01 00 +T 89 00 F1 +R 00 00 00 00 +T 8A 00 +R 00 00 00 00 +T 8A 00 DD F9 DD E1 C9 +R 00 00 00 00 +mbrtoc32.rel/ 0 0 0 644 1275 ` +XL2 +H 9 areas 3 global symbols +M mbrtoc32 +O -mz80 +S _mbrtowc Ref0000 +S .__.ABS. Def0000 +A _CODE size 87 flags 0 addr 0 +S _mbrtoc32 Def0000 +A _DATA size 3 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 01 00 +T 00 00 +R 00 00 01 00 +T 00 00 +R 00 00 00 00 +T 00 00 DD E5 DD 21 00 00 DD 39 F5 F5 DD 7E 0B DD +R 00 00 00 00 +T 0E 00 B6 0A 20 08 DD 36 0A 00 00 DD 36 0B 00 00 +R 00 00 00 00 09 09 01 00 89 0E 01 00 +T 1A 00 +R 00 00 00 00 +T 1A 00 DD 7E 05 DD B6 04 20 22 DD 6E 0A DD 66 0B +R 00 00 00 00 +T 28 00 E5 DD 6E 08 DD 66 09 E5 DD 6E 06 DD 66 07 +R 00 00 00 00 +T 36 00 E5 21 00 00 E5 CD 00 00 F1 F1 F1 F1 18 3E +R 00 00 00 00 02 08 00 00 +T 44 00 +R 00 00 00 00 +T 44 00 21 00 00 39 DD 4E 0A DD 46 0B C5 DD 4E 08 +R 00 00 00 00 +T 52 00 DD 46 09 C5 DD 4E 06 DD 46 07 C5 E5 CD +R 00 00 00 00 +T 5F 00 00 00 F1 F1 F1 F1 4D 44 3E 04 B9 3E 00 98 +R 00 00 00 00 02 02 00 00 +T 6D 00 38 11 DD 5E 04 DD 56 05 C5 21 02 00 39 01 +R 00 00 00 00 +T 7B 00 04 00 ED B0 C1 +R 00 00 00 00 +T 80 00 +R 00 00 00 00 +T 80 00 69 60 +R 00 00 00 00 +T 82 00 +R 00 00 00 00 +T 82 00 DD F9 DD E1 C9 +R 00 00 00 00 + +c32rtomb.rel/ 0 0 0 644 602 ` +XL2 +H 9 areas 3 global symbols +M c32rtomb +O -mz80 +S .__.ABS. Def0000 +S _wctomb Ref0000 +A _CODE size 23 flags 0 addr 0 +S _c32rtomb Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 FD 21 04 00 FD 39 FD 6E 02 FD 66 03 E5 FD +R 00 00 00 00 +T 0E 00 6E 00 FD 66 01 E5 21 06 00 39 4E 23 46 C5 +R 00 00 00 00 +T 1C 00 CD 00 00 F1 F1 F1 C9 +R 00 00 00 00 02 03 01 00 +wcscmp.rel/ 0 0 0 644 1424 ` +XL2 +H 9 areas 2 global symbols +M wcscmp +O -mz80 +S .__.ABS. Def0000 +A _CODE size B5 flags 0 addr 0 +S _wcscmp Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 DD E5 DD 21 00 00 DD 39 21 F8 FF 39 F9 DD +R 00 00 00 00 +T 0E 00 4E 04 DD 46 05 DD 5E 06 DD 56 07 +R 00 00 00 00 +T 19 00 +R 00 00 00 00 +T 19 00 D5 C5 59 50 21 04 00 39 EB 01 04 00 ED B0 +R 00 00 00 00 +T 27 00 C1 D1 D5 C5 21 08 00 39 EB 01 04 00 ED B0 +R 00 00 00 00 +T 35 00 C1 D1 DD 7E F8 DD 96 FC 20 30 DD 7E F9 DD +R 00 00 00 00 +T 43 00 96 FD 20 28 DD 7E FA DD 96 FE 20 20 DD 7E +R 00 00 00 00 +T 51 00 FB DD 96 FF 20 18 DD 7E FB DD B6 FA DD B6 +R 00 00 00 00 +T 5F 00 F9 DD B6 F8 28 0A 03 03 03 03 13 13 13 13 +R 00 00 00 00 +T 6D 00 18 AA +R 00 00 00 00 +T 6F 00 +R 00 00 00 00 +T 6F 00 DD 7E F8 DD 96 FC DD 7E F9 DD 9E FD DD 7E +R 00 00 00 00 +T 7D 00 FA DD 9E FE DD 7E FB DD 9E FF 30 05 21 +R 00 00 00 00 +T 8A 00 FF FF 18 22 +R 00 00 00 00 +T 8E 00 +R 00 00 00 00 +T 8E 00 DD 7E FC DD 96 F8 DD 7E FD DD 9E F9 DD 7E +R 00 00 00 00 +T 9C 00 FE DD 9E FA DD 7E FF DD 9E FB 30 05 21 +R 00 00 00 00 +T A9 00 01 00 18 03 +R 00 00 00 00 +T AD 00 +R 00 00 00 00 +T AD 00 21 00 00 +R 00 00 00 00 +T B0 00 +R 00 00 00 00 +T B0 00 DD F9 DD E1 C9 +R 00 00 00 00 +wcslen.rel/ 0 0 0 644 756 ` +XL2 +H 9 areas 2 global symbols +M wcslen +O -mz80 +S .__.ABS. Def0000 +A _CODE size 3D flags 0 addr 0 +S _wcslen Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 DD E5 DD 21 00 00 DD 39 F5 F5 01 00 00 DD +R 00 00 00 00 +T 0E 00 5E 04 DD 56 05 +R 00 00 00 00 +T 13 00 +R 00 00 00 00 +T 13 00 D5 C5 21 04 00 39 EB 01 04 00 ED B0 C1 D1 +R 00 00 00 00 +T 21 00 DD 7E FF DD B6 FE DD B6 FD DD B6 FC 28 07 +R 00 00 00 00 +T 2F 00 03 13 13 13 13 18 DD +R 00 00 00 00 +T 36 00 +R 00 00 00 00 +T 36 00 69 60 DD F9 DD E1 C9 +R 00 00 00 00 +btowc.rel/ 0 0 0 644 585 ` +XL2 +H 9 areas 2 global symbols +M btowc +O -mz80 +S .__.ABS. Def0000 +A _CODE size 22 flags 0 addr 0 +S _btowc Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 21 02 00 39 7E 07 30 06 21 FF FF 5D 54 C9 +R 00 00 00 00 +T 0E 00 +R 00 00 00 00 +T 0E 00 FD 21 02 00 FD 39 FD 6E 00 FD 66 01 FD 7E +R 00 00 00 00 +T 1C 00 01 17 9F 5F 57 C9 +R 00 00 00 00 + +wctob.rel/ 0 0 0 644 666 ` +XL2 +H 9 areas 2 global symbols +M wctob +O -mz80 +S .__.ABS. Def0000 +A _CODE size 27 flags 0 addr 0 +S _wctob Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 FD 21 02 00 FD 39 FD 7E 00 07 38 12 FD 7E +R 00 00 00 00 +T 0E 00 01 B7 20 0C FD 7E 02 B7 20 06 FD 7E 03 B7 +R 00 00 00 00 +T 1C 00 28 04 +R 00 00 00 00 +T 1E 00 +R 00 00 00 00 +T 1E 00 21 FF FF C9 +R 00 00 00 00 +T 22 00 +R 00 00 00 00 +T 22 00 C1 E1 E5 C5 C9 +R 00 00 00 00 +mbsinit.rel/ 0 0 0 644 720 ` +XL2 +H 9 areas 2 global symbols +M mbsinit +O -mz80 +S .__.ABS. Def0000 +A _CODE size 29 flags 0 addr 0 +S _mbsinit Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 21 03 00 39 7E 2B B6 28 1B D1 C1 C5 D5 0A +R 00 00 00 00 +T 0E 00 B7 20 0F 69 60 23 7E B7 20 08 69 60 23 23 +R 00 00 00 00 +T 1C 00 7E B7 28 04 +R 00 00 00 00 +T 20 00 +R 00 00 00 00 +T 20 00 2E 00 18 02 +R 00 00 00 00 +T 24 00 +R 00 00 00 00 +T 24 00 2E 01 +R 00 00 00 00 +T 26 00 +R 00 00 00 00 +T 26 00 26 00 C9 +R 00 00 00 00 +mbrlen.rel/ 0 0 0 644 822 ` +XL2 +H 9 areas 3 global symbols +M mbrlen +O -mz80 +S _mbrtowc Ref0000 +S .__.ABS. Def0000 +A _CODE size 36 flags 0 addr 0 +S _mbrlen Def0000 +A _DATA size 3 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 01 00 +T 00 00 +R 00 00 01 00 +T 00 00 +R 00 00 00 00 +T 00 00 FD 21 06 00 FD 39 FD 7E 01 FD B6 00 28 08 +R 00 00 00 00 +T 0E 00 FD 4E 00 FD 46 01 18 03 +R 00 00 00 00 +T 16 00 +R 00 00 00 00 +T 16 00 01 00 00 +R 00 00 00 00 00 03 01 00 +T 19 00 +R 00 00 00 00 +T 19 00 C5 21 06 00 39 4E 23 46 C5 21 06 00 39 4E +R 00 00 00 00 +T 27 00 23 46 C5 21 00 00 E5 CD 00 00 F1 F1 F1 F1 +R 00 00 00 00 02 0A 00 00 +T 35 00 C9 +R 00 00 00 00 +mbrtowc.rel/ 0 0 0 644 4560 ` +XL2 +H 9 areas 3 global symbols +M mbrtowc +O -mz80 +S _errno Ref0000 +S .__.ABS. Def0000 +A _CODE size 291 flags 0 addr 0 +S _mbrtowc Def0000 +A _DATA size 3 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 01 00 +T 00 00 +R 00 00 01 00 +T 00 00 +R 00 00 00 00 +T 00 00 DD E5 DD 21 00 00 DD 39 21 E5 FF 39 F9 DD +R 00 00 00 00 +T 0E 00 7E 07 DD B6 06 20 1D DD 6E 0A DD 66 0B E5 +R 00 00 00 00 +T 1C 00 21 01 00 E5 21 90 02 E5 21 00 00 E5 CD +R 00 00 00 00 00 07 00 00 +T 29 00 00 00 F1 F1 F1 F1 C3 8B 02 +R 00 00 00 00 00 02 00 00 00 09 00 00 +T 32 00 +R 00 00 00 00 +T 32 00 DD 7E 09 DD B6 08 CA 82 02 DD 7E 0B DD B6 +R 00 00 00 00 00 09 00 00 +T 40 00 0A 20 08 DD 36 0A 00 00 DD 36 0B 00 00 +R 00 00 00 00 09 08 01 00 89 0D 01 00 +T 4B 00 +R 00 00 00 00 +T 4B 00 21 00 00 39 DD 75 F3 DD 74 F4 DD 4E 0A DD +R 00 00 00 00 +T 59 00 46 0B DD 71 FA DD 70 FB 1E 00 +R 00 00 00 00 +T 63 00 +R 00 00 00 00 +T 63 00 DD 6E FA DD 66 FB 16 00 19 7E DD 77 F7 B7 +R 00 00 00 00 +T 71 00 28 21 7B D6 03 30 1C DD 7E F3 83 DD 77 F8 +R 00 00 00 00 +T 7F 00 DD 7E F4 CE 00 DD 77 F9 DD 6E F8 DD 66 F9 +R 00 00 00 00 +T 8D 00 DD 7E F7 77 1C 18 CF +R 00 00 00 00 +T 94 00 +R 00 00 00 00 +T 94 00 DD 73 F8 DD 36 F7 01 DD 6E 0A DD 66 0B 5E +R 00 00 00 00 +T A2 00 DD 7E 06 DD 77 FA DD 7E 07 DD 77 FB 7B B7 +R 00 00 00 00 +T B0 00 20 07 DD 6E FA DD 66 FB 5E +R 00 00 00 00 +T B9 00 +R 00 00 00 00 +T B9 00 DD 73 E9 DD CB E9 7E 28 31 2E 01 +R 00 00 00 00 +T C4 00 +R 00 00 00 00 +T C4 00 7D F5 1E 80 F1 3C 18 02 +R 00 00 00 00 +T CC 00 +R 00 00 00 00 +T CC 00 CB 3B +R 00 00 00 00 +T CE 00 +R 00 00 00 00 +T CE 00 3D 20 FB DD 7E E9 A3 28 03 2C 18 EA +R 00 00 00 00 +T DA 00 +R 00 00 00 00 +T DA 00 DD 75 F7 26 00 23 F5 1E FF F1 2C 18 02 +R 00 00 00 00 +T E7 00 +R 00 00 00 00 +T E7 00 CB 3B +R 00 00 00 00 +T E9 00 +R 00 00 00 00 +T E9 00 2D 20 FB DD 7E E9 A3 DD 77 E9 +R 00 00 00 00 +T F3 00 +R 00 00 00 00 +T F3 00 3E 04 DD 96 F7 DA 82 02 DD 5E F8 16 00 DD +R 00 00 00 00 00 08 00 00 +T 01 01 6E 08 DD 66 09 19 DD 5E F7 16 00 BF ED 52 +R 00 00 00 00 +T 0F 01 30 4E DD 5E FA DD 56 FB DD 7E F8 DD 77 F2 +R 00 00 00 00 +T 1D 01 DD 7E 08 DD 77 EE DD 7E 09 DD 77 EF +R 00 00 00 00 +T 29 01 +R 00 00 00 00 +T 29 01 DD 6E EE DD 66 EF DD 7E EE C6 FF DD 77 EE +R 00 00 00 00 +T 37 01 DD 7E EF CE FF DD 77 EF 7C B5 28 16 E5 DD +R 00 00 00 00 +T 45 01 6E F2 26 00 E5 FD E1 E1 FD 09 1A 13 FD 77 +R 00 00 00 00 +T 53 01 00 DD 34 F2 18 D0 +R 00 00 00 00 +T 59 01 +R 00 00 00 00 +T 59 01 21 FE FF C3 8B 02 +R 00 00 00 00 00 06 00 00 +T 5F 01 +R 00 00 00 00 +T 5F 01 1E 00 +R 00 00 00 00 +T 61 01 +R 00 00 00 00 +T 61 01 7B DD 96 F8 30 09 6B 26 00 09 36 00 1C 18 +R 00 00 00 00 +T 6F 01 F1 +R 00 00 00 00 +T 70 01 +R 00 00 00 00 +T 70 01 DD 36 08 01 DD 36 09 00 DD 7E F8 B7 28 05 +R 00 00 00 00 +T 7E 01 DD 4E F8 18 02 +R 00 00 00 00 +T 83 01 +R 00 00 00 00 +T 83 01 0E 01 +R 00 00 00 00 +T 85 01 +R 00 00 00 00 +T 85 01 DD 71 EE DD 7E F3 DD 77 F8 DD 7E F4 DD 77 +R 00 00 00 00 +T 93 01 F9 DD 36 F0 01 DD 36 F1 00 +R 00 00 00 00 +T 9C 01 +R 00 00 00 00 +T 9C 01 DD 7E EE DD 96 F7 30 53 DD 7E F8 DD 86 EE +R 00 00 00 00 +T AA 01 DD 77 F5 DD 7E F9 CE 00 DD 77 F6 DD 6E FA +R 00 00 00 00 +T B8 01 DD 66 FB 7E DD 77 F2 DD 34 FA 20 03 DD 34 +R 00 00 00 00 +T C6 01 FB +R 00 00 00 00 +T C7 01 +R 00 00 00 00 +T C7 01 DD 6E F5 DD 66 F6 DD 7E F2 77 DD 7E F2 E6 +R 00 00 00 00 +T D5 01 C0 DD 77 F5 D6 80 C2 82 02 DD 34 EE DD 34 +R 00 00 00 00 00 09 00 00 +T E3 01 F0 20 03 DD 34 F1 +R 00 00 00 00 +T E9 01 +R 00 00 00 00 +T E9 01 DD 7E F0 DD 77 08 DD 7E F1 DD 77 09 18 A5 +R 00 00 00 00 +T F7 01 +R 00 00 00 00 +T F7 01 DD 7E E9 DD 77 EA DD 36 EB 00 DD 36 EC 00 +R 00 00 00 00 +T 05 02 DD 36 ED 00 DD 6E F3 DD 66 F4 23 DD 7E F7 +R 00 00 00 00 +T 13 02 C6 FF DD 77 F5 +R 00 00 00 00 +T 18 02 +R 00 00 00 00 +T 18 02 DD 7E F5 B7 28 4D DD 4E EA DD 46 EB DD 5E +R 00 00 00 00 +T 26 02 EC DD 56 ED 3E 06 +R 00 00 00 00 +T 2C 02 +R 00 00 00 00 +T 2C 02 CB 21 CB 10 CB 13 CB 12 3D 20 F5 7E E6 3F +R 00 00 00 00 +T 3A 02 DD 77 FC DD 36 FD 00 DD 36 FE 00 DD 36 FF +R 00 00 00 00 +T 48 02 00 79 DD B6 FC DD 77 EA 78 DD B6 FD DD 77 +R 00 00 00 00 +T 56 02 EB 7B DD B6 FE DD 77 EC 7A DD B6 FF DD 77 +R 00 00 00 00 +T 64 02 ED 23 DD 35 F5 18 AD +R 00 00 00 00 +T 6B 02 +R 00 00 00 00 +T 6B 02 DD 5E 04 DD 56 05 21 05 00 39 01 04 00 ED +R 00 00 00 00 +T 79 02 B0 DD 6E 08 DD 66 09 18 09 +R 00 00 00 00 +T 82 02 +R 00 00 00 00 +T 82 02 21 54 00 22 00 00 21 FF FF +R 00 00 00 00 02 06 00 00 +T 8B 02 +R 00 00 00 00 +T 8B 02 DD F9 DD E1 C9 +R 00 00 00 00 +T 90 02 +R 00 00 00 00 +T 90 02 00 +R 00 00 00 00 +wcrtomb.rel/ 0 0 0 644 600 ` +XL2 +H 9 areas 3 global symbols +M wcrtomb +O -mz80 +S .__.ABS. Def0000 +S _wctomb Ref0000 +A _CODE size 23 flags 0 addr 0 +S _wcrtomb Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 FD 21 04 00 FD 39 FD 6E 02 FD 66 03 E5 FD +R 00 00 00 00 +T 0E 00 6E 00 FD 66 01 E5 21 06 00 39 4E 23 46 C5 +R 00 00 00 00 +T 1C 00 CD 00 00 F1 F1 F1 C9 +R 00 00 00 00 02 03 01 00 +/153 0 0 0 644 17126 ` +XL2 +H 9 areas 4 global symbols +M printf_large +O -mz80 +S .__.ABS. Def0000 +S ___sdcc_call_hl Ref0000 +S _strlen Ref0000 +A _CODE size B47 flags 0 addr 0 +S __print_format Def00FF +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 21 02 00 39 7E C6 30 47 3E 39 90 30 10 78 +R 00 00 00 00 +T 0E 00 C6 07 47 21 03 00 39 CB 46 28 04 78 C6 20 +R 00 00 00 00 +T 1C 00 47 +R 00 00 00 00 +T 1D 00 +R 00 00 00 00 +T 1D 00 21 06 00 39 7E 23 66 6F E5 C5 33 21 07 00 +R 00 00 00 00 +T 2B 00 39 7E 23 66 6F CD 00 00 F1 33 C9 +R 00 00 00 00 02 08 01 00 +T 36 00 +R 00 00 00 00 +T 36 00 DD E5 DD 21 00 00 DD 39 DD 7E 04 07 07 07 +R 00 00 00 00 +T 44 00 07 E6 0F 47 DD 6E 08 DD 66 09 E5 DD 6E 06 +R 00 00 00 00 +T 52 00 DD 66 07 E5 DD 7E 05 F5 33 C5 33 CD 00 00 +R 00 00 00 00 00 0E 00 00 +T 60 00 21 06 00 39 F9 DD 7E 04 E6 0F 47 DD 6E 08 +R 00 00 00 00 +T 6E 00 DD 66 09 E5 DD 6E 06 DD 66 07 E5 DD 7E 05 +R 00 00 00 00 +T 7C 00 F5 33 C5 33 CD 00 00 21 06 00 39 F9 DD E1 +R 00 00 00 00 00 07 00 00 +T 8A 00 C9 +R 00 00 00 00 +T 8B 00 +R 00 00 00 00 +T 8B 00 DD E5 DD 21 00 00 DD 39 21 FA FF 39 F9 DD +R 00 00 00 00 +T 99 00 5E 04 DD 56 05 D5 21 03 00 39 EB 01 04 00 +R 00 00 00 00 +T A7 00 ED B0 D1 21 04 00 19 4D 44 DD 36 FA 20 +R 00 00 00 00 +T B4 00 +R 00 00 00 00 +T B4 00 0A 87 DD 77 FF DD 7E FE CB 07 E6 01 DD B6 +R 00 00 00 00 +T C2 00 FF DD 77 FF 02 DD CB FB 26 DD CB FC 16 DD +R 00 00 00 00 +T D0 00 CB FD 16 DD CB FE 16 DD 7E FF DD 96 06 38 +R 00 00 00 00 +T DE 00 09 0A DD 96 06 02 DD CB FB C6 +R 00 00 00 00 +T E8 00 +R 00 00 00 00 +T E8 00 DD 35 FA DD 7E FA B7 20 C3 21 01 00 39 01 +R 00 00 00 00 +T F6 00 04 00 ED B0 DD F9 DD E1 C9 +R 00 00 00 00 +T FF 00 +R 00 00 00 00 +T FF 00 DD E5 DD 21 00 00 DD 39 21 C4 FF 39 F9 DD +R 00 00 00 00 +T 0D 01 36 E1 00 DD 36 E2 00 21 0F 00 39 DD 75 F9 +R 00 00 00 00 +T 1B 01 DD 74 FA 21 05 00 39 DD 75 EB DD 74 EC 21 +R 00 00 00 00 +T 29 01 0F 00 39 DD 75 ED DD 74 EE DD 7E ED C6 04 +R 00 00 00 00 +T 37 01 DD 77 E8 DD 7E EE CE 00 DD 77 E9 DD 7E E8 +R 00 00 00 00 +T 45 01 DD 77 DE DD 7E E9 DD 77 DF DD 7E E8 DD 77 +R 00 00 00 00 +T 53 01 E3 DD 7E E9 DD 77 E4 +R 00 00 00 00 +T 5A 01 +R 00 00 00 00 +T 5A 01 DD 6E 08 DD 66 09 4E 23 DD 75 08 DD 74 09 +R 00 00 00 00 +T 68 01 DD 71 E5 79 B7 CA 31 0B DD 7E E5 D6 25 C2 +R 00 00 00 00 00 08 00 00 +T 76 01 0E 0B DD 36 CF 00 DD 36 DC 00 DD 36 DD 00 +R 00 00 00 00 00 02 00 00 +T 84 01 DD 36 D0 00 DD 36 CE 00 DD 36 CD 00 DD 36 +R 00 00 00 00 +T 92 01 D2 00 DD 36 D1 00 DD 36 DB 00 DD 36 E0 00 +R 00 00 00 00 +T A0 01 DD 36 DA FF DD 7E 08 DD 77 E6 DD 7E 09 DD +R 00 00 00 00 +T AE 01 77 E7 +R 00 00 00 00 +T B0 01 +R 00 00 00 00 +T B0 01 DD 6E E6 DD 66 E7 7E DD 77 FF DD 34 E6 20 +R 00 00 00 00 +T BE 01 03 DD 34 E7 +R 00 00 00 00 +T C2 01 +R 00 00 00 00 +T C2 01 DD 7E E6 DD 77 08 DD 7E E7 DD 77 09 DD 7E +R 00 00 00 00 +T D0 01 FF D6 25 20 23 DD 6E 06 DD 66 07 E5 DD 7E +R 00 00 00 00 +T DE 01 FF F5 33 DD 6E 04 DD 66 05 CD 00 00 F1 33 +R 00 00 00 00 02 0C 01 00 +T EC 01 DD 34 E1 C2 5A 01 DD 34 E2 C3 5A 01 +R 00 00 00 00 00 06 00 00 00 0C 00 00 +T F8 01 +R 00 00 00 00 +T F8 01 DD 7E FF D6 30 38 3E 3E 39 DD 96 FF 38 37 +R 00 00 00 00 +T 06 02 DD 7E DA 3C 20 1C DD 7E E0 4F 87 87 81 87 +R 00 00 00 00 +T 14 02 DD 77 EA DD 86 FF C6 D0 DD 77 E0 B7 20 8E +R 00 00 00 00 +T 22 02 DD 36 DC 01 18 88 +R 00 00 00 00 +T 28 02 +R 00 00 00 00 +T 28 02 DD 6E DA 4D 29 29 09 29 DD 4E FF 09 7D C6 +R 00 00 00 00 +T 36 02 D0 DD 77 DA C3 B0 01 +R 00 00 00 00 00 07 00 00 +T 3D 02 +R 00 00 00 00 +T 3D 02 DD 7E FF D6 2E 20 0E DD 7E DA 3C C2 B0 01 +R 00 00 00 00 00 0E 00 00 +T 4B 02 DD 36 DA 00 C3 B0 01 +R 00 00 00 00 00 07 00 00 +T 52 02 +R 00 00 00 00 +T 52 02 DD 7E FF D6 61 38 11 3E 7A DD 96 FF 38 0A +R 00 00 00 00 +T 60 02 DD CB FF AE DD 36 D8 01 18 04 +R 00 00 00 00 +T 6A 02 +R 00 00 00 00 +T 6A 02 DD 36 D8 00 +R 00 00 00 00 +T 6E 02 +R 00 00 00 00 +T 6E 02 DD 7E FF D6 20 CA 0D 03 DD 7E FF D6 2B CA +R 00 00 00 00 00 08 00 00 +T 7C 02 06 03 DD 7E FF D6 2D 28 7A DD 7E FF D6 42 +R 00 00 00 00 00 02 00 00 +T 8A 02 CA 14 03 DD 7E FF D6 43 CA 22 03 DD 7E FF +R 00 00 00 00 00 03 00 00 00 0B 00 00 +T 98 02 D6 44 CA 38 05 DD 7E FF D6 46 CA 54 05 DD +R 00 00 00 00 00 05 00 00 00 0D 00 00 +T A6 02 7E FF D6 48 CA B0 01 DD 7E FF D6 49 CA +R 00 00 00 00 00 07 00 00 +T B3 02 38 05 DD 7E FF D6 4A CA B0 01 DD 7E FF D6 +R 00 00 00 00 00 02 00 00 00 0A 00 00 +T C1 02 4C 28 57 DD 7E FF D6 4F CA 42 05 DD 7E FF +R 00 00 00 00 00 0B 00 00 +T CF 02 D6 50 CA 8E 04 DD 7E FF D6 53 CA 6C 03 DD +R 00 00 00 00 00 05 00 00 00 0D 00 00 +T DD 02 7E FF D6 54 CA B0 01 DD 7E FF D6 55 CA +R 00 00 00 00 00 07 00 00 +T EA 02 48 05 DD 7E FF D6 58 CA 4E 05 DD 7E FF D6 +R 00 00 00 00 00 02 00 00 00 0A 00 00 +T F8 02 5A CA B0 01 C3 5A 05 +R 00 00 00 00 00 04 00 00 00 07 00 00 +T FF 02 +R 00 00 00 00 +T FF 02 DD 36 CF 01 C3 B0 01 +R 00 00 00 00 00 07 00 00 +T 06 03 +R 00 00 00 00 +T 06 03 DD 36 DD 01 C3 B0 01 +R 00 00 00 00 00 07 00 00 +T 0D 03 +R 00 00 00 00 +T 0D 03 DD 36 D0 01 C3 B0 01 +R 00 00 00 00 00 07 00 00 +T 14 03 +R 00 00 00 00 +T 14 03 DD 36 CD 01 C3 B0 01 +R 00 00 00 00 00 07 00 00 +T 1B 03 +R 00 00 00 00 +T 1B 03 DD 36 D2 01 C3 B0 01 +R 00 00 00 00 00 07 00 00 +T 22 03 +R 00 00 00 00 +T 22 03 DD CB CD 46 28 11 DD 6E 0A DD 66 0B 23 DD +R 00 00 00 00 +T 30 03 75 0A DD 74 0B 2B 46 18 13 +R 00 00 00 00 +T 39 03 +R 00 00 00 00 +T 39 03 DD 6E 0A DD 66 0B 23 23 DD 75 0A DD 74 0B +R 00 00 00 00 +T 47 03 2B 2B 46 23 4E +R 00 00 00 00 +T 4C 03 +R 00 00 00 00 +T 4C 03 DD 6E 06 DD 66 07 E5 C5 33 DD 6E 04 DD 66 +R 00 00 00 00 +T 5A 03 05 CD 00 00 F1 33 DD 34 E1 C2 84 05 DD 34 +R 00 00 00 00 02 04 01 00 00 0C 00 00 +T 68 03 E2 C3 84 05 +R 00 00 00 00 00 04 00 00 +T 6C 03 +R 00 00 00 00 +T 6C 03 21 0F 00 39 DD 75 E6 DD 74 E7 DD 6E 0A DD +R 00 00 00 00 +T 7A 03 66 0B 23 23 DD 75 0A DD 74 0B 2B 2B 4E 23 +R 00 00 00 00 +T 88 03 46 DD 6E E6 DD 66 E7 71 23 70 C5 CD 00 00 R 00 00 00 00 02 0E 02 00 -T 8D 03 F1 5D DD 7E D3 3C 20 03 DD 73 D3 +T 96 03 F1 5D DD 7E DA 3C 20 03 DD 73 DA R 00 00 00 00 -T 98 03 +T A1 03 R 00 00 00 00 -T 98 03 DD CB DD 46 20 46 7B DD 96 ED 30 40 DD 7E +T A1 03 DD CB CF 46 20 46 7B DD 96 E0 30 40 DD 7E R 00 00 00 00 -T A6 03 ED 93 DD 77 FF DD 4E EB DD 46 EC +T AF 03 E0 93 DD 77 EA DD 4E E1 DD 46 E2 R 00 00 00 00 -T B1 03 +T BA 03 R 00 00 00 00 -T B1 03 DD 66 FF DD 35 FF 7C B7 28 1D C5 D5 DD 6E +T BA 03 DD 56 EA DD 35 EA 7A B7 28 1D C5 D5 DD 6E R 00 00 00 00 -T BF 03 06 DD 66 07 E5 3E 20 F5 33 DD 6E 04 DD 66 +T C8 03 06 DD 66 07 E5 3E 20 F5 33 DD 6E 04 DD 66 R 00 00 00 00 -T CD 03 05 CD 00 00 F1 33 D1 C1 03 18 D9 +T D6 03 05 CD 00 00 F1 33 D1 C1 03 18 D9 R 00 00 00 00 02 04 01 00 -T D8 03 +T E1 03 R 00 00 00 00 -T D8 03 DD 71 EB DD 70 EC DD 7E FF DD 77 ED -R 00 00 00 00 -T E4 03 -R 00 00 00 00 -T E4 03 DD 56 D3 DD 4E EB DD 46 EC +T E1 03 DD 71 E1 DD 70 E2 DD 7E EA DD 77 E0 R 00 00 00 00 T ED 03 R 00 00 00 00 -T ED 03 DD 6E FC DD 66 FD 7E 23 66 6F 7E DD 77 FF +T ED 03 DD 56 DA DD 4E E1 DD 46 E2 R 00 00 00 00 -T FB 03 B7 28 4A 62 15 AF 94 E2 07 04 EE 80 +T F6 03 +R 00 00 00 00 +T F6 03 DD 6E E6 DD 66 E7 7E 23 66 6F 7E DD 77 EA +R 00 00 00 00 +T 04 04 B7 28 4A 6A 15 AF 95 E2 10 04 EE 80 R 00 00 00 00 00 0A 00 00 -T 07 04 +T 10 04 R 00 00 00 00 -T 07 04 F2 48 04 C5 D5 DD 6E 06 DD 66 07 E5 DD 7E +T 10 04 F2 51 04 C5 D5 DD 6E 06 DD 66 07 E5 DD 7E R 00 00 00 00 00 03 00 00 -T 15 04 FF F5 33 DD 6E 04 DD 66 05 CD 00 00 F1 33 +T 1E 04 EA F5 33 DD 6E 04 DD 66 05 CD 00 00 F1 33 R 00 00 00 00 02 0C 01 00 -T 23 04 D1 C1 03 DD 6E FC DD 66 FD 7E 23 66 6F 23 +T 2C 04 D1 C1 03 DD 6E E6 DD 66 E7 7E 23 66 6F 23 R 00 00 00 00 -T 31 04 DD 75 E7 DD 74 E8 DD 6E FC DD 66 FD DD 7E +T 3A 04 DD 75 EF DD 74 F0 DD 6E E6 DD 66 E7 DD 7E R 00 00 00 00 -T 3F 04 E7 77 23 DD 7E E8 77 18 A5 +T 48 04 EF 77 23 DD 7E F0 77 18 A5 R 00 00 00 00 -T 48 04 +T 51 04 R 00 00 00 00 -T 48 04 DD 71 EB DD 70 EC DD CB DD 46 CA 7A 05 7B +T 51 04 DD 71 E1 DD 70 E2 DD CB CF 46 CA 84 05 7B R 00 00 00 00 00 0D 00 00 -T 56 04 DD 96 ED D2 7A 05 DD 7E ED 93 5F +T 5F 04 DD 96 E0 D2 84 05 DD 7E E0 93 5F R 00 00 00 00 00 06 00 00 -T 61 04 +T 6A 04 R 00 00 00 00 -T 61 04 63 1D 7C B7 CA 71 05 C5 D5 DD 6E 06 DD 66 +T 6A 04 53 1D 7A B7 CA 7B 05 C5 D5 DD 6E 06 DD 66 R 00 00 00 00 00 07 00 00 -T 6F 04 07 E5 3E 20 F5 33 DD 6E 04 DD 66 05 CD +T 78 04 07 E5 3E 20 F5 33 DD 6E 04 DD 66 05 CD R 00 00 00 00 -T 7C 04 00 00 F1 33 D1 C1 03 18 DC +T 85 04 00 00 F1 33 D1 C1 03 18 DC R 00 00 00 00 02 02 01 00 -T 85 04 +T 8E 04 R 00 00 00 00 -T 85 04 21 0D 00 39 EB DD 6E 0A DD 66 0B 23 23 DD +T 8E 04 21 0F 00 39 4D 44 DD 6E 0A DD 66 0B 23 23 R 00 00 00 00 -T 93 04 75 0A DD 74 0B 2B 2B 4E 23 46 79 12 13 78 +T 9C 04 DD 75 0A DD 74 0B 2B 2B 5E 23 56 7B 02 03 R 00 00 00 00 -T A1 04 12 DD 6E 06 DD 66 07 E5 3E 30 F5 33 DD 6E +T AA 04 7A 02 DD 6E 06 DD 66 07 E5 3E 30 F5 33 DD R 00 00 00 00 -T AF 04 04 DD 66 05 CD 00 00 F1 33 DD 5E EB DD 56 -R 00 00 00 00 02 07 01 00 -T BD 04 EC 13 D5 DD 6E 06 DD 66 07 E5 3E 78 F5 33 +T B8 04 6E 04 DD 66 05 CD 00 00 F1 33 DD 4E E1 DD +R 00 00 00 00 02 08 01 00 +T C6 04 46 E2 03 C5 DD 6E 06 DD 66 07 E5 3E 78 F5 R 00 00 00 00 -T CB 04 DD 6E 04 DD 66 05 CD 00 00 F1 33 D1 13 21 -R 00 00 00 00 02 09 01 00 -T D9 04 0E 00 39 46 D5 DD 6E 06 DD 66 07 E5 DD 6E +T D4 04 33 DD 6E 04 DD 66 05 CD 00 00 F1 33 C1 03 +R 00 00 00 00 02 0A 01 00 +T E2 04 21 10 00 39 56 C5 DD 6E 06 DD 66 07 E5 DD R 00 00 00 00 -T E7 04 04 DD 66 05 E5 DD 7E DC F5 33 C5 33 CD +T F0 04 6E 04 DD 66 05 E5 DD 7E D8 F5 33 D5 33 CD R 00 00 00 00 -T F4 04 42 00 21 06 00 39 F9 D1 13 13 DD 6E F2 DD +T FE 04 36 00 21 06 00 39 F9 C1 03 03 DD 6E F9 DD R 00 00 00 00 00 02 00 00 -T 02 05 66 F3 46 D5 DD 6E 06 DD 66 07 E5 DD 6E 04 +T 0C 05 66 FA 56 C5 DD 6E 06 DD 66 07 E5 DD 6E 04 R 00 00 00 00 -T 10 05 DD 66 05 E5 DD 7E DC F5 33 C5 33 CD 42 00 +T 1A 05 DD 66 05 E5 DD 7E D8 F5 33 D5 33 CD 36 00 R 00 00 00 00 00 0E 00 00 -T 1E 05 21 06 00 39 F9 D1 13 13 DD 73 EB DD 72 EC +T 28 05 21 06 00 39 F9 C1 03 03 DD 71 E1 DD 70 E2 R 00 00 00 00 -T 2C 05 18 4C -R 00 00 00 00 -T 2E 05 -R 00 00 00 00 -T 2E 05 DD 36 DF 01 DD 36 D4 0A 18 42 +T 36 05 18 4C R 00 00 00 00 T 38 05 R 00 00 00 00 -T 38 05 DD 36 D4 08 18 3C +T 38 05 DD 36 CE 01 DD 36 DB 0A 18 42 R 00 00 00 00 -T 3E 05 +T 42 05 R 00 00 00 00 -T 3E 05 DD 36 D4 0A 18 36 +T 42 05 DD 36 DB 08 18 3C R 00 00 00 00 -T 44 05 +T 48 05 R 00 00 00 00 -T 44 05 DD 36 D4 10 18 30 +T 48 05 DD 36 DB 0A 18 36 R 00 00 00 00 -T 4A 05 +T 4E 05 R 00 00 00 00 -T 4A 05 DD 36 D0 01 18 2A +T 4E 05 DD 36 DB 10 18 30 R 00 00 00 00 -T 50 05 +T 54 05 R 00 00 00 00 -T 50 05 DD 6E 06 DD 66 07 E5 DD 7E FE F5 33 DD 6E +T 54 05 DD 36 D1 01 18 2A R 00 00 00 00 -T 5E 05 04 DD 66 05 CD 00 00 F1 33 DD 34 EB 20 0E +T 5A 05 +R 00 00 00 00 +T 5A 05 DD 6E 06 DD 66 07 E5 DD 7E FF F5 33 DD 6E +R 00 00 00 00 +T 68 05 04 DD 66 05 CD 00 00 F1 33 DD 34 E1 20 0E R 00 00 00 00 02 07 01 00 -T 6C 05 DD 34 EC 18 09 +T 76 05 DD 34 E2 18 09 R 00 00 00 00 -T 71 05 +T 7B 05 R 00 00 00 00 -T 71 05 DD 71 EB DD 70 EC DD 73 ED +T 7B 05 DD 71 E1 DD 70 E2 DD 73 E0 R 00 00 00 00 -T 7A 05 +T 84 05 R 00 00 00 00 -T 7A 05 DD CB D0 46 CA 3C 06 21 0D 00 39 DD 75 E7 +T 84 05 DD CB D1 46 CA 46 06 21 0F 00 39 DD 75 EF R 00 00 00 00 00 07 00 00 -T 88 05 DD 74 E8 DD 7E 0A C6 04 DD 77 FC DD 7E 0B +T 92 05 DD 74 F0 DD 7E 0A C6 04 DD 77 E6 DD 7E 0B R 00 00 00 00 -T 96 05 CE 00 DD 77 FD DD 7E FC DD 77 0A DD 7E FD +T A0 05 CE 00 DD 77 E7 DD 7E E6 DD 77 0A DD 7E E7 R 00 00 00 00 -T A4 05 DD 77 0B DD 7E FC C6 FC DD 77 FC DD 7E FD +T AE 05 DD 77 0B DD 7E E6 C6 FC DD 77 E6 DD 7E E7 R 00 00 00 00 -T B2 05 CE FF DD 77 FD DD 5E FC DD 56 FD 21 24 00 +T BC 05 CE FF DD 77 E7 DD 5E E6 DD 56 E7 21 2D 00 R 00 00 00 00 -T C0 05 39 EB 01 04 00 ED B0 DD 5E E7 DD 56 E8 21 +T CA 05 39 EB 01 04 00 ED B0 DD 5E EF DD 56 F0 21 R 00 00 00 00 -T CE 05 24 00 39 01 04 00 ED B0 21 0D 00 39 DD 75 +T D8 05 2D 00 39 01 04 00 ED B0 21 0F 00 39 DD 75 R 00 00 00 00 -T DC 05 EE DD 74 EF DD 6E EE DD 66 EF 36 27 0B 23 +T E6 05 F1 DD 74 F2 DD 6E F1 DD 66 F2 36 3C 0B 23 R 00 00 00 00 09 0D 00 00 -T E9 05 36 27 0B DD 7E EB DD 77 E7 DD 7E EC DD 77 +T F3 05 36 3C 0B DD 7E E1 DD 77 EF DD 7E E2 DD 77 R 00 00 00 00 89 03 00 00 -T F6 05 E8 +T 00 06 F0 R 00 00 00 00 -T F7 05 +T 01 06 R 00 00 00 00 -T F7 05 DD 6E EE DD 66 EF 5E 23 56 4B 42 03 DD 6E +T 01 06 DD 6E F1 DD 66 F2 4E 23 46 59 50 13 DD 6E R 00 00 00 00 -T 05 06 EE DD 66 EF 71 23 70 1A 67 B7 CA 54 01 DD +T 0F 06 F1 DD 66 F2 73 23 72 0A 47 B7 CA 5A 01 DD R 00 00 00 00 00 0D 00 00 -T 13 06 4E 06 DD 46 07 C5 E5 33 DD 6E 04 DD 66 05 +T 1D 06 6E 06 DD 66 07 E5 C5 33 DD 6E 04 DD 66 05 R 00 00 00 00 -T 21 06 CD 00 00 F1 33 DD 34 E7 20 03 DD 34 E8 +T 2B 06 CD 00 00 F1 33 DD 34 EF 20 03 DD 34 F0 R 00 00 00 00 02 03 01 00 -T 2E 06 +T 38 06 R 00 00 00 00 -T 2E 06 DD 7E E7 DD 77 EB DD 7E E8 DD 77 EC 18 BB +T 38 06 DD 7E EF DD 77 E1 DD 7E F0 DD 77 E2 18 BB R 00 00 00 00 -T 3C 06 +T 46 06 R 00 00 00 00 -T 3C 06 DD 7E D4 B7 CA 54 01 DD 7E E2 DD 77 EE DD +T 46 06 DD 7E DB B7 CA 5A 01 DD 7E EB DD 77 F1 DD R 00 00 00 00 00 07 00 00 -T 4A 06 7E E3 DD 77 EF DD CB DE 46 CA E8 06 21 +T 54 06 7E EC DD 77 F2 DD CB CD 46 CA E4 06 21 R 00 00 00 00 00 0C 00 00 -T 57 06 0D 00 39 DD 75 E7 DD 74 E8 DD 7E 0A C6 01 +T 61 06 0F 00 39 DD 75 EF DD 74 F0 DD 7E 0A C6 01 R 00 00 00 00 -T 65 06 DD 77 FC DD 7E 0B CE 00 DD 77 FD DD 7E FC +T 6F 06 DD 77 E6 DD 7E 0B CE 00 DD 77 E7 DD 7E E6 R 00 00 00 00 -T 73 06 DD 77 0A DD 7E FD DD 77 0B DD 6E FC DD 66 +T 7D 06 DD 77 0A DD 7E E7 DD 77 0B DD 6E E6 DD 66 R 00 00 00 00 -T 81 06 FD 2B DD 75 FC DD 74 FD DD 6E FC DD 66 FD +T 8B 06 E7 2B 7E DD 77 EA DD 77 F5 DD 36 F6 00 DD R 00 00 00 00 -T 8F 06 7E DD 77 FF DD 77 F4 DD 7E FF 17 9F DD 77 +T 99 06 36 F7 00 DD 36 F8 00 DD 5E EF DD 56 F0 21 R 00 00 00 00 -T 9D 06 F5 DD 77 F6 DD 77 F7 DD 5E E7 DD 56 E8 21 +T A7 06 31 00 39 01 04 00 ED B0 DD CB CE 46 C2 R 00 00 00 00 -T AB 06 2A 00 39 01 04 00 ED B0 DD CB DF 46 C2 -R 00 00 00 00 -T B8 06 E7 07 DD 5E E7 DD 56 E8 21 2A 00 39 EB 01 +T B4 06 E3 07 DD 5E EF DD 56 F0 21 31 00 39 EB 01 R 00 00 00 00 00 02 00 00 -T C6 06 04 00 ED B0 DD 36 F5 00 DD 36 F6 00 DD 36 +T C2 06 04 00 ED B0 DD 36 F6 00 DD 36 F7 00 DD 36 R 00 00 00 00 -T D4 06 F7 00 DD 5E E7 DD 56 E8 21 2A 00 39 01 +T D0 06 F8 00 DD 5E EF DD 56 F0 21 31 00 39 01 R 00 00 00 00 -T E1 06 04 00 ED B0 C3 E7 07 +T DD 06 04 00 ED B0 C3 E3 07 R 00 00 00 00 00 07 00 00 -T E8 06 +T E4 06 R 00 00 00 00 -T E8 06 DD CB D1 46 28 58 21 0D 00 39 DD 75 F4 DD +T E4 06 DD CB D2 46 28 58 21 0F 00 39 DD 75 F5 DD R 00 00 00 00 -T F6 06 74 F5 DD 7E 0A C6 04 DD 77 E7 DD 7E 0B CE +T F2 06 74 F6 DD 7E 0A C6 04 DD 77 EF DD 7E 0B CE R 00 00 00 00 -T 04 07 00 DD 77 E8 DD 7E E7 DD 77 0A DD 7E E8 DD +T 00 07 00 DD 77 F0 DD 7E EF DD 77 0A DD 7E F0 DD R 00 00 00 00 -T 12 07 77 0B DD 7E E7 C6 FC DD 77 E7 DD 7E E8 CE +T 0E 07 77 0B DD 7E EF C6 FC DD 77 EF DD 7E F0 CE R 00 00 00 00 -T 20 07 FF DD 77 E8 DD 5E E7 DD 56 E8 21 2E 00 39 +T 1C 07 FF DD 77 F0 DD 5E EF DD 56 F0 21 37 00 39 R 00 00 00 00 -T 2E 07 EB 01 04 00 ED B0 DD 5E F4 DD 56 F5 21 +T 2A 07 EB 01 04 00 ED B0 DD 5E F5 DD 56 F6 21 R 00 00 00 00 -T 3B 07 2E 00 39 01 04 00 ED B0 C3 E7 07 +T 37 07 37 00 39 01 04 00 ED B0 C3 E3 07 R 00 00 00 00 00 0B 00 00 -T 46 07 +T 42 07 R 00 00 00 00 -T 46 07 21 0D 00 39 DD 75 F8 DD 74 F9 DD 7E 0A C6 +T 42 07 21 0F 00 39 DD 75 FB DD 74 FC DD 7E 0A C6 R 00 00 00 00 -T 54 07 02 DD 77 F4 DD 7E 0B CE 00 DD 77 F5 DD 7E +T 50 07 02 DD 77 F5 DD 7E 0B CE 00 DD 77 F6 DD 7E R 00 00 00 00 -T 62 07 F4 DD 77 0A DD 7E F5 DD 77 0B DD 7E F4 C6 +T 5E 07 F5 DD 77 0A DD 7E F6 DD 77 0B DD 7E F5 C6 R 00 00 00 00 -T 70 07 FE DD 77 F4 DD 7E F5 CE FF DD 77 F5 DD 7E +T 6C 07 FE DD 77 F5 DD 7E F6 CE FF DD 77 F6 DD 7E R 00 00 00 00 -T 7E 07 F4 DD 77 F4 DD 7E F5 DD 77 F5 DD 6E F4 DD +T 7A 07 F5 DD 77 F5 DD 7E F6 DD 77 F6 DD 6E F5 DD R 00 00 00 00 -T 8C 07 66 F5 7E DD 77 F4 23 7E DD 77 F5 DD 7E F4 +T 88 07 66 F6 7E DD 77 F5 23 7E DD 77 F6 DD 7E F5 R 00 00 00 00 -T 9A 07 DD 77 F4 DD 7E F5 DD 77 F5 17 9F DD 77 F6 +T 96 07 DD 77 F5 DD 7E F6 DD 77 F6 17 9F DD 77 F7 R 00 00 00 00 -T A8 07 DD 77 F7 DD 5E F8 DD 56 F9 21 2A 00 39 01 +T A4 07 DD 77 F8 DD 5E FB DD 56 FC 21 31 00 39 01 R 00 00 00 00 -T B6 07 04 00 ED B0 DD CB DF 46 20 27 DD 5E F8 DD +T B2 07 04 00 ED B0 DD CB CE 46 20 27 DD 5E FB DD R 00 00 00 00 -T C4 07 56 F9 21 2A 00 39 EB 01 04 00 ED B0 DD 36 +T C0 07 56 FC 21 31 00 39 EB 01 04 00 ED B0 DD 36 R 00 00 00 00 -T D2 07 F6 00 DD 36 F7 00 DD 5E F8 DD 56 F9 21 +T CE 07 F7 00 DD 36 F8 00 DD 5E FB DD 56 FC 21 R 00 00 00 00 -T DF 07 2A 00 39 01 04 00 ED B0 +T DB 07 31 00 39 01 04 00 ED B0 R 00 00 00 00 -T E7 07 +T E3 07 R 00 00 00 00 -T E7 07 DD CB DF 46 28 4A 21 0D 00 39 DD 75 F8 DD +T E3 07 DD CB CE 46 28 4A 21 0F 00 39 DD 75 FB DD R 00 00 00 00 -T F5 07 74 F9 EB 21 2A 00 39 EB 01 04 00 ED B0 DD +T F1 07 74 FC EB 21 31 00 39 EB 01 04 00 ED B0 DD R 00 00 00 00 -T 03 08 CB F7 7E 28 2B DD 6E F8 DD 66 F9 5E 23 56 +T FF 07 CB F8 7E 28 2B DD 6E FB DD 66 FC 4E 23 46 R 00 00 00 00 -T 11 08 23 4E 23 46 AF 93 5F 3E 00 9A 57 3E 00 99 +T 0D 08 23 5E 23 56 AF 91 4F 3E 00 98 47 3E 00 9B R 00 00 00 00 -T 1F 08 4F 3E 00 98 47 DD 6E F8 DD 66 F9 73 23 72 +T 1B 08 5F 3E 00 9A 57 DD 6E FB DD 66 FC 71 23 70 R 00 00 00 00 -T 2D 08 23 71 23 70 18 04 +T 29 08 23 73 23 72 18 04 +R 00 00 00 00 +T 2F 08 +R 00 00 00 00 +T 2F 08 DD 36 CE 00 R 00 00 00 00 T 33 08 R 00 00 00 00 -T 33 08 DD 36 DF 00 +T 33 08 DD 36 CA 01 DD 4E F1 DD 46 F2 DD 36 D9 00 R 00 00 00 00 -T 37 08 +T 41 08 R 00 00 00 00 -T 37 08 DD 36 E0 01 DD 4E EE DD 46 EF DD 36 D2 00 +T 41 08 21 13 00 39 36 00 DD 5E ED DD 56 EE C5 DD R 00 00 00 00 -T 45 08 -R 00 00 00 00 -T 45 08 21 11 00 39 36 00 DD 5E E9 DD 56 EA C5 DD -R 00 00 00 00 -T 53 08 7E D4 F5 33 D5 CD 97 00 F1 33 C1 DD CB E0 +T 4F 08 7E DB F5 33 D5 CD 8B 00 F1 33 C1 DD CB CA R 00 00 00 00 00 08 00 00 -T 61 08 46 20 23 DD 6E E5 DD 66 E6 7E 07 07 07 07 +T 5D 08 46 20 23 DD 6E DE DD 66 DF 7E 07 07 07 07 R 00 00 00 00 -T 6F 08 E6 F0 57 DD 6E E5 DD 66 E6 7E 07 07 07 07 +T 6B 08 E6 F0 5F DD 6E DE DD 66 DF 7E 07 07 07 07 R 00 00 00 00 -T 7D 08 E6 0F B2 57 0A B2 02 0B 18 08 +T 79 08 E6 0F B3 5F 0A B3 02 0B 18 08 R 00 00 00 00 -T 87 08 +T 83 08 R 00 00 00 00 -T 87 08 DD 6E E5 DD 66 E6 7E 02 +T 83 08 DD 6E E8 DD 66 E9 7E 02 R 00 00 00 00 -T 8F 08 +T 8B 08 R 00 00 00 00 -T 8F 08 DD 34 D2 DD 7E E0 EE 01 DD 77 E0 DD 6E E9 +T 8B 08 DD 34 D9 DD 7E CA EE 01 DD 77 CA DD 6E ED R 00 00 00 00 -T 9D 08 DD 66 EA 5E 23 56 23 23 7E 2B 66 B4 B2 B3 +T 99 08 DD 66 EE 5E 23 56 23 23 7E 2B 6E B5 B2 B3 R 00 00 00 00 -T AB 08 20 98 DD 71 F8 DD 70 F9 DD 7E D2 DD 77 F4 +T A7 08 20 98 DD 71 FB DD 70 FC DD 7E D9 DD 77 F5 R 00 00 00 00 -T B9 08 DD 7E ED B7 20 04 DD 36 ED 01 +T B5 08 DD 7E E0 B7 20 04 DD 36 E0 01 R 00 00 00 00 -T C3 08 +T BF 08 R 00 00 00 00 -T C3 08 DD CB D6 46 20 54 DD CB DD 46 20 4E DD 7E +T BF 08 DD CB DC 46 20 54 DD CB CF 46 20 4E DD 7E R 00 00 00 00 -T D1 08 F4 3C DD 77 EE DD 7E EB DD 77 E7 DD 7E EC +T CD 08 F5 3C DD 77 F1 DD 7E E1 DD 77 EF DD 7E E2 R 00 00 00 00 -T DF 08 DD 77 E8 DD 56 ED +T DB 08 DD 77 F0 DD 4E E0 R 00 00 00 00 -T E5 08 +T E1 08 R 00 00 00 00 -T E5 08 DD 7E EE 92 30 23 D5 DD 6E 06 DD 66 07 E5 +T E1 08 DD 7E F1 91 30 23 C5 DD 6E 06 DD 66 07 E5 R 00 00 00 00 -T F3 08 3E 20 F5 33 DD 6E 04 DD 66 05 CD 00 00 F1 +T EF 08 3E 20 F5 33 DD 6E 04 DD 66 05 CD 00 00 F1 R 00 00 00 00 02 0D 01 00 -T 01 09 33 D1 DD 34 E7 20 03 DD 34 E8 +T FD 08 33 C1 DD 34 EF 20 03 DD 34 F0 R 00 00 00 00 -T 0B 09 +T 07 09 R 00 00 00 00 -T 0B 09 15 18 D7 +T 07 09 0D 18 D7 R 00 00 00 00 -T 0E 09 +T 0A 09 R 00 00 00 00 -T 0E 09 DD 7E E7 DD 77 EB DD 7E E8 DD 77 EC DD 72 +T 0A 09 DD 7E EF DD 77 E1 DD 7E F0 DD 77 E2 DD 71 R 00 00 00 00 -T 1C 09 ED +T 18 09 E0 R 00 00 00 00 -T 1D 09 +T 19 09 R 00 00 00 00 -T 1D 09 DD CB DF 46 28 23 DD 6E 06 DD 66 07 E5 3E +T 19 09 DD CB CE 46 28 23 DD 6E 06 DD 66 07 E5 3E R 00 00 00 00 -T 2B 09 2D F5 33 DD 6E 04 DD 66 05 CD 00 00 F1 33 +T 27 09 2D F5 33 DD 6E 04 DD 66 05 CD 00 00 F1 33 R 00 00 00 00 02 0C 01 00 -T 39 09 DD 34 EB 20 03 DD 34 EC +T 35 09 DD 34 E1 20 03 DD 34 E2 R 00 00 00 00 -T 41 09 +T 3D 09 R 00 00 00 00 -T 41 09 DD 35 ED 18 56 +T 3D 09 DD 35 E0 18 56 R 00 00 00 00 -T 46 09 +T 42 09 R 00 00 00 00 -T 46 09 DD 7E F4 B7 28 50 DD CB D5 46 28 23 DD 6E +T 42 09 DD 7E F5 B7 28 50 DD CB DD 46 28 23 DD 6E R 00 00 00 00 -T 54 09 06 DD 66 07 E5 3E 2B F5 33 DD 6E 04 DD 66 +T 50 09 06 DD 66 07 E5 3E 2B F5 33 DD 6E 04 DD 66 R 00 00 00 00 -T 62 09 05 CD 00 00 F1 33 DD 34 EB 20 03 DD 34 EC +T 5E 09 05 CD 00 00 F1 33 DD 34 E1 20 03 DD 34 E2 R 00 00 00 00 02 04 01 00 -T 70 09 +T 6C 09 R 00 00 00 00 -T 70 09 DD 35 ED 18 27 +T 6C 09 DD 35 E0 18 27 R 00 00 00 00 -T 75 09 +T 71 09 R 00 00 00 00 -T 75 09 DD CB E1 46 28 21 DD 6E 06 DD 66 07 E5 3E +T 71 09 DD CB D0 46 28 21 DD 6E 06 DD 66 07 E5 3E R 00 00 00 00 -T 83 09 20 F5 33 DD 6E 04 DD 66 05 CD 00 00 F1 33 +T 7F 09 20 F5 33 DD 6E 04 DD 66 05 CD 00 00 F1 33 R 00 00 00 00 02 0C 01 00 -T 91 09 DD 34 EB 20 03 DD 34 EC +T 8D 09 DD 34 E1 20 03 DD 34 E2 R 00 00 00 00 -T 99 09 +T 95 09 R 00 00 00 00 -T 99 09 DD 35 ED +T 95 09 DD 35 E0 R 00 00 00 00 -T 9C 09 +T 98 09 R 00 00 00 00 -T 9C 09 DD CB DD 46 20 4F DD 7E EB DD 77 EE DD 7E +T 98 09 DD CB CF 46 20 57 DD 7E E1 DD 77 F1 DD 7E R 00 00 00 00 -T AA 09 EC DD 77 EF DD 7E ED DD 77 E7 +T A6 09 E2 DD 77 F2 DD 7E E0 DD 77 EF R 00 00 00 00 -T B4 09 +T B0 09 R 00 00 00 00 -T B4 09 DD 66 E7 DD 35 E7 DD 7E F4 94 30 4A DD CB +T B0 09 DD 4E EF DD 35 EF DD 7E F5 91 30 52 DD CB R 00 00 00 00 -T C2 09 D6 46 28 06 DD 36 FF 30 18 04 +T BE 09 DC 46 28 0A DD 36 E6 30 DD 36 E7 00 18 08 R 00 00 00 00 T CC 09 R 00 00 00 00 -T CC 09 DD 36 FF 20 +T CC 09 DD 36 E6 20 DD 36 E7 00 R 00 00 00 00 -T D0 09 +T D4 09 R 00 00 00 00 -T D0 09 DD 6E 06 DD 66 07 E5 DD 7E FF F5 33 DD 6E +T D4 09 DD 46 E6 DD 6E 06 DD 66 07 E5 C5 33 DD 6E R 00 00 00 00 -T DE 09 04 DD 66 05 CD 00 00 F1 33 DD 34 EE 20 C8 +T E2 09 04 DD 66 05 CD 00 00 F1 33 DD 34 F1 20 C0 R 00 00 00 00 02 07 01 00 -T EC 09 DD 34 EF 18 C3 +T F0 09 DD 34 F2 18 BB R 00 00 00 00 -T F1 09 +T F5 09 R 00 00 00 00 -T F1 09 DD 7E F4 DD 96 ED 30 0B DD 7E ED DD 96 F4 +T F5 09 DD 7E F5 DD 96 E0 30 0B DD 7E E0 DD 96 F5 R 00 00 00 00 -T FF 09 DD 77 FF 18 18 +T 03 0A DD 77 EA 18 18 R 00 00 00 00 -T 04 0A +T 08 0A R 00 00 00 00 -T 04 0A DD 36 FF 00 18 12 +T 08 0A DD 36 EA 00 18 12 R 00 00 00 00 -T 0A 0A +T 0E 0A R 00 00 00 00 -T 0A 0A DD 7E EE DD 77 EB DD 7E EF DD 77 EC DD 7E +T 0E 0A DD 7E F1 DD 77 E1 DD 7E F2 DD 77 E2 DD 7E R 00 00 00 00 -T 18 0A E7 DD 77 FF +T 1C 0A EF DD 77 EA R 00 00 00 00 -T 1C 0A +T 20 0A R 00 00 00 00 -T 1C 0A DD 7E F8 DD 77 F8 DD 7E F9 DD 77 F9 DD 7E +T 20 0A DD 7E FB DD 77 FB DD 7E FC DD 77 FC DD 7E R 00 00 00 00 -T 2A 0A EB DD 77 EE DD 7E EC DD 77 EF DD 7E F4 DD +T 2E 0A E1 DD 77 F1 DD 7E E2 DD 77 F2 DD 7E F5 DD R 00 00 00 00 -T 38 0A 77 F4 +T 3C 0A 77 F5 R 00 00 00 00 -T 3A 0A +T 3E 0A R 00 00 00 00 -T 3A 0A DD 66 F4 DD 35 F4 7C B7 28 6A DD 7E E0 EE +T 3E 0A DD 4E F5 DD 35 F5 79 B7 28 6A DD 7E CA EE R 00 00 00 00 -T 48 0A 01 DD 77 E0 DD CB E0 46 20 1E DD 34 F8 20 +T 4C 0A 01 DD 77 CA DD CB CA 46 20 1E DD 34 FB 20 R 00 00 00 00 -T 56 0A 03 DD 34 F9 +T 5A 0A 03 DD 34 FC R 00 00 00 00 -T 5A 0A +T 5E 0A R 00 00 00 00 -T 5A 0A DD 6E F8 DD 66 F9 7E 07 07 07 07 E6 0F DD +T 5E 0A DD 6E FB DD 66 FC 7E 07 07 07 07 E6 0F DD R 00 00 00 00 -T 68 0A 6E E5 DD 66 E6 77 18 10 +T 6C 0A 6E E8 DD 66 E9 77 18 10 R 00 00 00 00 -T 70 0A +T 74 0A R 00 00 00 00 -T 70 0A DD 6E F8 DD 66 F9 7E E6 0F DD 6E E5 DD 66 +T 74 0A DD 6E FB DD 66 FC 7E E6 0F DD 6E E8 DD 66 R 00 00 00 00 -T 7E 0A E6 77 +T 82 0A E9 77 R 00 00 00 00 -T 80 0A +T 84 0A R 00 00 00 00 -T 80 0A DD 6E E5 DD 66 E6 56 DD 6E 06 DD 66 07 E5 +T 84 0A DD 6E E3 DD 66 E4 46 DD 6E 06 DD 66 07 E5 R 00 00 00 00 -T 8E 0A DD 6E 04 DD 66 05 E5 DD 7E DC F5 33 D5 33 +T 92 0A DD 6E 04 DD 66 05 E5 DD 7E D8 F5 33 C5 33 R 00 00 00 00 -T 9C 0A CD 00 00 21 06 00 39 F9 DD 34 EE 20 91 DD +T A0 0A CD 00 00 21 06 00 39 F9 DD 34 F1 20 91 DD R 00 00 00 00 00 03 00 00 -T AA 0A 34 EF 18 8C +T AE 0A 34 F2 18 8C R 00 00 00 00 -T AE 0A +T B2 0A R 00 00 00 00 -T AE 0A DD 7E EE DD 77 EB DD 7E EF DD 77 EC DD CB +T B2 0A DD 7E F1 DD 77 E1 DD 7E F2 DD 77 E2 DD CB R 00 00 00 00 -T BC 0A DD 46 CA 54 01 DD 5E EE DD 56 EF DD 7E FF +T C0 0A CF 46 CA 5A 01 DD 7E F1 DD 77 CB DD 7E F2 R 00 00 00 00 00 05 00 00 -T CA 0A DD 77 F8 +T CE 0A DD 77 CC DD 7E EA DD 77 FB R 00 00 00 00 -T CD 0A +T D7 0A R 00 00 00 00 -T CD 0A DD 66 F8 DD 35 F8 7C B7 CA 54 01 D5 DD 6E +T D7 0A DD 4E FB DD 35 FB 79 B7 CA 5A 01 DD 6E 06 R 00 00 00 00 00 0B 00 00 -T DB 0A 06 DD 66 07 E5 3E 20 F5 33 DD 6E 04 DD 66 +T E5 0A DD 66 07 E5 3E 20 F5 33 DD 6E 04 DD 66 05 R 00 00 00 00 -T E9 0A 05 CD 00 00 F1 33 D1 13 DD 73 EB DD 72 EC -R 00 00 00 00 02 04 01 00 -T F7 0A 18 D4 +T F3 0A CD 00 00 F1 33 DD 34 CB 20 03 DD 34 CC +R 00 00 00 00 02 03 01 00 +T 00 0B R 00 00 00 00 -T F9 0A +T 00 0B DD 7E CB DD 77 E1 DD 7E CC DD 77 E2 18 C9 R 00 00 00 00 -T F9 0A DD 6E 06 DD 66 07 E5 DD 7E E4 F5 33 DD 6E +T 0E 0B R 00 00 00 00 -T 07 0B 04 DD 66 05 CD 00 00 F1 33 DD 34 EB C2 +T 0E 0B DD 6E 06 DD 66 07 E5 DD 7E E5 F5 33 DD 6E +R 00 00 00 00 +T 1C 0B 04 DD 66 05 CD 00 00 F1 33 DD 34 E1 C2 R 00 00 00 00 02 07 01 00 -T 14 0B 54 01 DD 34 EC C3 54 01 +T 29 0B 5A 01 DD 34 E2 C3 5A 01 R 00 00 00 00 00 02 00 00 00 08 00 00 -T 1C 0B +T 31 0B R 00 00 00 00 -T 1C 0B DD 6E EB DD 66 EC DD F9 DD E1 C9 +T 31 0B DD 6E E1 DD 66 E2 DD F9 DD E1 C9 R 00 00 00 00 -T 27 0B +T 3C 0B R 00 00 00 00 -T 27 0B 3C 4E 4F 20 46 4C 4F 41 54 3E 00 +T 3C 0B 3C 4E 4F 20 46 4C 4F 41 54 3E 00 R 00 00 00 00 - -puts.rel/ 1458795433 2001 2501 100664 737 ` +puts.rel/ 0 0 0 644 682 ` XL2 H 9 areas 3 global symbols M puts O -mz80 S _putchar Ref0000 S .__.ABS. Def0000 -A _CODE size 31 flags 0 addr 0 +A _CODE size 26 flags 0 addr 0 S _puts Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -41239,22 +57172,19 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 DD E5 DD 21 00 00 DD 39 DD 6E 04 DD 66 05 +T 00 00 D1 C1 C5 D5 R 00 00 00 00 -T 0E 00 11 00 00 +T 04 00 R 00 00 00 00 -T 11 00 +T 04 00 0A B7 28 15 5F 03 16 00 C5 D5 CD 00 00 F1 +R 00 00 00 00 02 0D 00 00 +T 12 00 C1 2C 20 EE 24 20 EB 21 FF FF C9 R 00 00 00 00 -T 11 00 46 13 78 B7 28 0D 23 E5 D5 C5 33 CD 00 00 -R 00 00 00 00 02 0E 00 00 -T 1F 00 33 D1 E1 18 ED +T 1D 00 R 00 00 00 00 -T 24 00 -R 00 00 00 00 -T 24 00 D5 3E 0A F5 33 CD 00 00 33 E1 DD E1 C9 -R 00 00 00 00 02 08 00 00 - -gets.rel/ 1458795433 2001 2501 100664 1489 ` +T 1D 00 21 0A 00 E5 CD 00 00 F1 C9 +R 00 00 00 00 02 07 00 00 +gets.rel/ 0 0 0 644 1483 ` XL2 H 9 areas 4 global symbols M gets @@ -41262,7 +57192,7 @@ O -mz80 S _putchar Ref0000 S .__.ABS. Def0000 S _getchar Ref0000 -A _CODE size AE flags 0 addr 0 +A _CODE size AC flags 0 addr 0 S _gets Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -41274,55 +57204,55 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 3B 11 00 00 +T 00 00 3B 01 00 00 R 00 00 00 00 T 04 00 R 00 00 00 00 -T 04 00 D5 CD 00 00 D1 FD 21 00 00 FD 39 FD 75 00 +T 04 00 C5 CD 00 00 C1 FD 21 00 00 FD 39 FD 75 00 R 00 00 00 00 02 04 02 00 -T 12 00 FD 7E 00 D6 08 28 1D 21 03 00 39 46 23 4E +T 12 00 FD 7E 00 D6 08 28 1D 21 03 00 39 56 23 5E R 00 00 00 00 -T 20 00 FD 21 00 00 FD 39 FD 7E 00 D6 0A 28 3D FD +T 20 00 FD 21 00 00 FD 39 FD 7E 00 D6 0A 28 3B FD R 00 00 00 00 -T 2E 00 7E 00 D6 0D 28 36 18 4E +T 2E 00 7E 00 D6 0D 28 34 18 4B R 00 00 00 00 T 36 00 R 00 00 00 00 -T 36 00 7A B3 28 CA D5 3E 08 F5 33 CD 00 00 33 3E +T 36 00 78 B1 28 CA C5 21 08 00 E5 CD 00 00 21 R 00 00 00 00 02 0C 00 00 -T 44 00 20 F5 33 CD 00 00 33 3E 08 F5 33 CD 00 00 -R 00 00 00 00 02 06 00 00 02 0E 00 00 -T 52 00 33 D1 FD 21 03 00 FD 39 FD 6E 00 FD 66 01 +T 43 00 20 00 E3 CD 00 00 21 08 00 E3 CD 00 00 F1 +R 00 00 00 00 02 06 00 00 02 0D 00 00 +T 51 00 C1 FD 21 03 00 FD 39 FD 6E 00 FD 66 01 2B R 00 00 00 00 -T 60 00 2B FD 75 00 FD 74 01 1B 18 9A +T 5F 00 FD 75 00 FD 74 01 0B 18 9C R 00 00 00 00 -T 6A 00 +T 68 00 R 00 00 00 00 -T 6A 00 C5 3E 0D F5 33 CD 00 00 33 3E 0A F5 33 CD +T 68 00 D5 21 0D 00 E5 CD 00 00 21 0A 00 E3 CD R 00 00 00 00 02 08 00 00 -T 78 00 00 00 33 C1 68 61 36 00 68 61 18 28 +T 75 00 00 00 F1 D1 6A 63 36 00 6A 63 18 29 R 00 00 00 00 02 02 00 00 -T 84 00 +T 81 00 R 00 00 00 00 -T 84 00 68 61 FD 21 00 00 FD 39 FD 7E 00 77 78 21 +T 81 00 6A 63 FD 21 00 00 FD 39 FD 7E 00 77 7A 21 R 00 00 00 00 -T 92 00 03 00 39 C6 01 77 79 CE 00 23 77 13 D5 FD +T 8F 00 03 00 39 C6 01 77 7B CE 00 23 77 03 FD 5E R 00 00 00 00 -T A0 00 7E 00 F5 33 CD 00 00 33 D1 C3 04 00 -R 00 00 00 00 02 07 00 00 00 0C 00 00 -T AC 00 +T 9D 00 00 16 00 C5 D5 CD 00 00 F1 C1 C3 04 00 +R 00 00 00 00 02 08 00 00 00 0D 00 00 +T AA 00 R 00 00 00 00 -T AC 00 33 C9 +T AA 00 33 C9 R 00 00 00 00 -assert.rel/ 1458795433 2001 2501 100664 945 ` +assert.rel/ 0 0 0 644 878 ` XL2 H 9 areas 3 global symbols M assert O -mz80 S .__.ABS. Def0000 S _printf Ref0000 -A _CODE size 5F flags 0 addr 0 +A _CODE size 50 flags 0 addr 0 S __assert Def0000 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 @@ -41334,28 +57264,25 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 21 35 00 FD 21 04 00 FD 39 FD 4E 00 FD 46 -R 00 00 00 00 00 03 00 00 -T 0E 00 01 C5 FD 21 08 00 FD 39 FD 4E 00 FD 46 01 +T 00 00 21 04 00 39 4E 23 46 C5 21 08 00 39 4E 23 R 00 00 00 00 -T 1C 00 C5 FD 21 06 00 FD 39 FD 4E 00 FD 46 01 C5 +T 0E 00 46 C5 21 06 00 39 4E 23 46 C5 21 26 00 E5 +R 00 00 00 00 00 0D 00 00 +T 1C 00 CD 00 00 21 08 00 39 F9 +R 00 00 00 00 02 03 01 00 +T 24 00 R 00 00 00 00 -T 2A 00 E5 CD 00 00 21 08 00 39 F9 -R 00 00 00 00 02 04 01 00 -T 33 00 +T 24 00 18 FE R 00 00 00 00 -T 33 00 18 FE +T 26 00 R 00 00 00 00 -T 35 00 +T 26 00 41 73 73 65 72 74 28 25 73 29 20 66 61 69 R 00 00 00 00 -T 35 00 41 73 73 65 72 74 28 25 73 29 20 66 61 69 +T 34 00 6C 65 64 20 61 74 20 6C 69 6E 65 20 25 75 R 00 00 00 00 -T 43 00 6C 65 64 20 61 74 20 6C 69 6E 65 20 25 75 +T 42 00 20 69 6E 20 66 69 6C 65 20 25 73 2E 0A 00 R 00 00 00 00 -T 51 00 20 69 6E 20 66 69 6C 65 20 25 73 2E 0A 00 -R 00 00 00 00 - -time.rel/ 1458795435 2001 2501 100664 11925 ` +time.rel/ 0 0 0 644 11959 ` XL2 H 9 areas F global symbols M time @@ -41366,14 +57293,14 @@ S _sprintf Ref0000 S __divulong Ref0000 S __modsint Ref0000 S __mullong Ref0000 -A _CODE size 6CF flags 0 addr 0 +A _CODE size 6D3 flags 0 addr 0 S _RtcRead Def0000 S _asctime Def00B2 S _time Def0003 -S _localtime Def0191 -S _gmtime Def019B -S _mktime Def043C -S _ctime Def0183 +S _localtime Def019B +S _gmtime Def01A5 +S _mktime Def0447 +S _ctime Def018D A _DATA size 2C flags 0 addr 0 A _INITIALIZED size 32 flags 0 addr 0 S ___month Def000C @@ -41416,7 +57343,7 @@ T 11 00 FF FF 11 FF FF 21 00 00 39 E5 FD E1 E5 C5 R 00 00 00 00 T 1F 00 D5 FD E5 CD 00 00 F1 7D D1 C1 E1 B7 28 07 R 00 00 00 00 00 06 00 00 -T 2D 00 E5 CD 3C 04 F1 4D 44 +T 2D 00 E5 CD 47 04 F1 4D 44 R 00 00 00 00 00 04 00 00 T 34 00 R 00 00 00 00 @@ -41430,37 +57357,37 @@ T 49 00 69 60 DD F9 DD E1 C9 R 00 00 00 00 T 50 00 R 00 00 00 00 -T 50 00 C1 D1 D5 C5 1A 67 3E 3B BC 30 01 12 +T 50 00 D1 C1 C5 D5 0A 5F 3E 3B BB 30 01 02 R 00 00 00 00 T 5C 00 R 00 00 00 00 -T 5C 00 6B 62 23 46 3E 3B 90 30 02 36 3B +T 5C 00 69 60 23 5E 3E 3B 93 30 02 36 3B R 00 00 00 00 T 67 00 R 00 00 00 00 -T 67 00 6B 62 23 23 46 3E 17 90 30 02 36 17 +T 67 00 69 60 23 23 5E 3E 17 93 30 02 36 17 R 00 00 00 00 T 73 00 R 00 00 00 00 -T 73 00 21 07 00 19 46 3E 06 90 30 02 36 06 +T 73 00 21 07 00 09 5E 3E 06 93 30 02 36 06 R 00 00 00 00 T 7F 00 R 00 00 00 00 -T 7F 00 6B 62 23 23 23 46 78 D6 01 30 04 36 01 18 +T 7F 00 69 60 23 23 23 5E 7B D6 01 30 04 36 01 18 R 00 00 00 00 T 8D 00 07 R 00 00 00 00 T 8E 00 R 00 00 00 00 -T 8E 00 3E 1F 90 30 02 36 1F +T 8E 00 3E 1F 93 30 02 36 1F R 00 00 00 00 T 95 00 R 00 00 00 00 -T 95 00 21 04 00 19 46 3E 0B 90 30 02 36 0B +T 95 00 21 04 00 09 5E 3E 0B 93 30 02 36 0B R 00 00 00 00 T A1 00 R 00 00 00 00 -T A1 00 21 05 00 19 E5 56 23 5E E1 CB 7B C8 AF 77 +T A1 00 21 05 00 09 E5 4E 23 46 E1 CB 78 C8 AF 77 R 00 00 00 00 T AF 00 23 77 C9 R 00 00 00 00 @@ -41468,367 +57395,369 @@ T B2 00 R 00 00 00 00 T B2 00 DD E5 DD 21 00 00 DD 39 21 F6 FF 39 F9 DD R 00 00 00 00 -T C0 00 6E 04 DD 66 05 E5 CD 50 00 F1 DD 5E 04 DD +T C0 00 6E 04 DD 66 05 E5 CD 50 00 F1 DD 4E 04 DD R 00 00 00 00 00 09 00 00 -T CE 00 56 05 D5 FD E1 FD 4E 05 FD 46 06 21 6C 07 +T CE 00 46 05 69 60 11 05 00 19 5E 23 56 21 6C 07 R 00 00 00 00 -T DC 00 09 E3 1A DD 77 F8 DD 36 F9 00 6B 62 23 7E +T DC 00 19 DD 75 FC DD 74 FD 0A DD 77 FA DD 36 FB R 00 00 00 00 -T EA 00 DD 77 FC DD 36 FD 00 6B 62 23 23 7E DD 77 +T EA 00 00 69 60 23 5E DD 73 F6 DD 36 F7 00 69 60 R 00 00 00 00 -T F8 00 FE DD 36 FF 00 6B 62 23 23 23 7E DD 77 FA +T F8 00 23 23 5E DD 73 F8 DD 36 F9 00 69 60 23 23 R 00 00 00 00 -T 06 01 DD 36 FB 00 6B 62 01 04 00 09 6E 26 00 29 +T 06 01 23 5E DD 73 FE DD 36 FF 00 11 0C 00 69 60 +R 00 00 00 00 00 0C 02 00 +T 14 01 23 23 23 23 6E 26 00 29 19 5E 23 56 69 60 R 00 00 00 00 -T 14 01 01 0C 00 09 4E 23 46 EB 11 07 00 19 6E 26 -R 00 00 00 00 00 03 02 00 -T 22 01 00 29 11 24 00 19 5E 23 56 E1 E5 E5 DD 6E -R 00 00 00 00 00 05 02 00 -T 30 01 F8 DD 66 F9 E5 DD 6E FC DD 66 FD E5 DD 6E +T 22 01 01 07 00 09 6E 26 00 29 01 24 00 09 4E 23 +R 00 00 00 00 00 0B 02 00 +T 30 01 46 DD 6E FC DD 66 FD E5 DD 6E FA DD 66 FB R 00 00 00 00 -T 3E 01 FE DD 66 FF E5 DD 6E FA DD 66 FB E5 C5 D5 +T 3E 01 E5 DD 6E F6 DD 66 F7 E5 DD 6E F8 DD 66 F9 R 00 00 00 00 -T 4C 01 21 64 01 E5 21 00 00 E5 CD 00 00 21 12 00 -R 00 00 00 00 00 03 00 00 00 07 01 00 02 0B 02 00 -T 5A 01 39 F9 21 00 00 DD F9 DD E1 C9 -R 00 00 00 00 00 05 01 00 -T 64 01 +T 4C 01 E5 DD 6E FE DD 66 FF E5 D5 C5 21 6E 01 E5 +R 00 00 00 00 00 0D 00 00 +T 5A 01 21 00 00 E5 CD 00 00 21 12 00 39 F9 21 +R 00 00 00 00 00 03 01 00 02 07 02 00 +T 67 01 00 00 DD F9 DD E1 C9 +R 00 00 00 00 00 02 01 00 +T 6E 01 R 00 00 00 00 -T 64 01 25 73 20 25 73 20 25 32 64 20 25 30 32 64 +T 6E 01 25 73 20 25 73 20 25 32 64 20 25 30 32 64 R 00 00 00 00 -T 72 01 3A 25 30 32 64 3A 25 30 32 64 20 25 30 34 +T 7C 01 3A 25 30 32 64 3A 25 30 32 64 20 25 30 34 R 00 00 00 00 -T 80 01 64 0A 00 +T 8A 01 64 0A 00 R 00 00 00 00 -T 83 01 +T 8D 01 R 00 00 00 00 -T 83 01 C1 E1 E5 C5 E5 CD 91 01 E3 CD B2 00 F1 C9 +T 8D 01 C1 E1 E5 C5 E5 CD 9B 01 E3 CD B2 00 F1 C9 R 00 00 00 00 00 08 00 00 00 0C 00 00 -T 91 01 -R 00 00 00 00 -T 91 01 C1 E1 E5 C5 E5 CD 9B 01 F1 C9 -R 00 00 00 00 00 08 00 00 T 9B 01 R 00 00 00 00 -T 9B 01 DD E5 DD 21 00 00 DD 39 21 EF FF 39 F9 DD +T 9B 01 C1 E1 E5 C5 E5 CD A5 01 F1 C9 +R 00 00 00 00 00 08 00 00 +T A5 01 R 00 00 00 00 -T A9 01 6E 04 DD 66 05 5E 23 56 23 4E 23 46 C5 D5 +T A5 01 DD E5 DD 21 00 00 DD 39 21 EF FF 39 F9 DD R 00 00 00 00 -T B7 01 21 00 00 E5 21 3C 00 E5 C5 D5 CD 00 00 F1 +T B3 01 6E 04 DD 66 05 4E 23 46 23 5E 23 56 C5 D5 +R 00 00 00 00 +T C1 01 21 00 00 E5 21 3C 00 E5 D5 C5 CD 00 00 F1 R 00 00 00 00 02 0D 01 00 -T C5 01 F1 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5F 7A DD 9E F5 57 DD 7E F6 91 DD 77 F2 R 00 00 00 00 -T 79 03 DD 7E F3 9C DD 77 FD DD 7E F4 9B DD 77 FE +T 84 03 DD 7E F7 98 DD 77 F3 DD 7E F8 9B DD 77 F4 R 00 00 00 00 -T 87 03 DD 7E F5 9A DD 77 FF DD 5E FC DD 56 FD ED +T 92 03 DD 7E F9 9A DD 77 F5 DD 4E F2 DD 46 F3 ED R 00 00 00 00 -T 95 03 53 28 00 DD 36 EF 00 +T A0 03 43 28 00 DD 36 EF 00 R 00 00 00 00 00 03 01 00 -T 9C 03 +T A7 03 R 00 00 00 00 -T 9C 03 DD 7E EF 3D 20 10 DD 7E F7 DD B6 F6 20 04 +T A7 03 DD 7E EF 3D 20 10 DD 7E FD DD B6 FC 20 04 R 00 00 00 00 -T AA 03 0E 1D 18 1A +T B5 03 0E 1D 18 1A R 00 00 00 00 -T AE 03 +T B9 03 R 00 00 00 00 -T AE 03 0E 1C 18 16 +T B9 03 0E 1C 18 16 R 00 00 00 00 -T B2 03 +T BD 03 R 00 00 00 00 -T B2 03 3E 00 00 DD 86 EF DD 77 FA 3E 00 00 CE 00 +T BD 03 3E 00 00 DD 86 EF DD 77 FA 3E 00 00 CE 00 R 00 00 00 00 09 03 02 00 89 0C 02 00 -T BE 03 DD 77 FB DD 6E FA DD 66 FB 4E +T C9 03 DD 77 FB DD 6E FA DD 66 FB 4E R 00 00 00 00 -T C8 03 +T D3 03 R 00 00 00 00 -T C8 03 DD 71 F2 DD 36 F3 00 DD 36 F4 00 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2A 00 36 00 21 20 00 DD F9 DD E1 C9 R 00 00 00 00 00 04 01 00 00 09 01 00 -T 3C 04 +T 47 04 R 00 00 00 00 -T 3C 04 DD E5 DD 21 00 00 DD 39 21 F2 FF 39 F9 DD +T 47 04 DD E5 DD 21 00 00 DD 39 21 F2 FF 39 F9 DD R 00 00 00 00 -T 4A 04 7E 04 DD 77 F8 DD 7E 05 DD 77 F9 DD 6E F8 +T 55 04 7E 04 DD 77 F8 DD 7E 05 DD 77 F9 DD 6E F8 R 00 00 00 00 -T 58 04 DD 66 F9 11 05 00 19 5E 23 56 21 6C 07 19 +T 63 04 DD 66 F9 11 05 00 19 4E 23 46 21 6C 07 09 R 00 00 00 00 -T 66 04 DD 75 F4 DD 74 F5 DD 6E F8 DD 66 F9 11 +T 71 04 DD 75 F6 DD 74 F7 DD 6E F8 DD 66 F9 11 R 00 00 00 00 -T 73 04 04 00 19 7E DD 77 F2 DD 36 F3 00 DD 6E F8 +T 7E 04 04 00 19 4E DD 71 F4 DD 36 F5 00 DD 6E F8 R 00 00 00 00 -T 81 04 DD 66 F9 E5 CD 50 00 F1 DD 7E F4 C6 4E 5F +T 8C 04 DD 66 F9 E5 CD 50 00 F1 DD 7E F6 C6 4E 4F R 00 00 00 00 00 07 00 00 -T 8F 04 DD 7E F5 CE F8 57 17 9F 6F 67 E5 D5 21 +T 9A 04 DD 7E F7 CE F8 47 17 9F 5F 57 D5 C5 21 R 00 00 00 00 -T 9C 04 E1 01 E5 21 80 33 E5 CD 00 00 F1 F1 F1 F1 +T A7 04 E1 01 E5 21 80 33 E5 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-T CB 06 53 61 74 00 +T CB 06 46 72 69 00 +R 00 00 00 00 +T CF 06 +R 00 00 00 00 +T CF 06 53 61 74 00 R 00 00 00 00 T 00 00 R 00 00 07 00 @@ -41836,24 +57765,24 @@ T 00 00 1F 1C 1F 1E 1F 1E 1F 1F 1E 1F 1E 1F R 00 00 07 00 T 0C 00 R 00 00 07 00 -T 0C 00 83 06 87 06 8B 06 +T 0C 00 87 06 8B 06 8F 06 R 00 00 07 00 00 02 00 00 00 04 00 00 00 06 00 00 -T 12 00 8F 06 93 06 97 06 +T 12 00 93 06 97 06 9B 06 R 00 00 07 00 00 02 00 00 00 04 00 00 00 06 00 00 -T 18 00 9B 06 9F 06 A3 06 +T 18 00 9F 06 A3 06 A7 06 R 00 00 07 00 00 02 00 00 00 04 00 00 00 06 00 00 -T 1E 00 A7 06 AB 06 AF 06 +T 1E 00 AB 06 AF 06 B3 06 R 00 00 07 00 00 02 00 00 00 04 00 00 00 06 00 00 T 24 00 R 00 00 07 00 -T 24 00 B3 06 B7 06 BB 06 +T 24 00 B7 06 BB 06 BF 06 R 00 00 07 00 00 02 00 00 00 04 00 00 00 06 00 00 -T 2A 00 BF 06 C3 06 C7 06 +T 2A 00 C3 06 C7 06 CB 06 R 00 00 07 00 00 02 00 00 00 04 00 00 00 06 00 00 -T 30 00 CB 06 +T 30 00 CF 06 R 00 00 07 00 00 02 00 00 -_itoa.rel/ 1458795435 2001 2501 100664 2054 ` +_itoa.rel/ 0 0 0 644 1974 ` XL2 H 9 areas 5 global symbols M _itoa @@ -41861,9 +57790,9 @@ O -mz80 S __divuint Ref0000 S .__.ABS. Def0000 S __moduint Ref0000 -A _CODE size 116 flags 0 addr 0 +A _CODE size 112 flags 0 addr 0 S __uitoa Def0000 -S __itoa Def00C7 +S __itoa Def00C3 A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 A _DABS size 0 flags 8 addr 0 @@ -41874,7 +57803,7 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 DD E5 DD 21 00 00 DD 39 F5 3B 0E 00 +T 00 00 DD E5 DD 21 00 00 DD 39 F5 F5 0E 00 R 00 00 00 00 T 0C 00 R 00 00 00 00 @@ -41882,61 +57811,57 @@ T 0C 00 DD 7E 06 81 DD 77 FE DD 7E 07 CE 00 DD 77 R 00 00 00 00 T 1A 00 FF DD 5E 08 16 00 C5 D5 D5 DD 6E 04 DD 66 R 00 00 00 00 -T 28 00 05 E5 CD 00 00 F1 F1 D1 C1 7D C6 30 47 DD +T 28 00 05 E5 CD 00 00 F1 F1 D1 C1 7D C6 30 DD 6E R 00 00 00 00 02 05 02 00 -T 36 00 6E FE DD 66 FF 70 3E 39 90 E2 44 00 EE 80 -R 00 00 00 00 00 0C 00 00 -T 44 00 +T 36 00 FE DD 66 FF 77 DD 6E FE DD 66 FF 46 3E 39 R 00 00 00 00 -T 44 00 F2 57 00 DD 6E FE DD 66 FF 7E C6 07 DD 6E -R 00 00 00 00 00 03 00 00 -T 52 00 FE DD 66 FF 77 +T 44 00 90 30 0A 78 C6 07 DD 6E FE DD 66 FF 77 R 00 00 00 00 -T 57 00 +T 51 00 R 00 00 00 00 -T 57 00 C5 D5 DD 6E 04 DD 66 05 E5 CD 00 00 F1 F1 +T 51 00 C5 D5 DD 6E 04 DD 66 05 E5 CD 00 00 F1 F1 R 00 00 00 00 02 0C 00 00 -T 65 00 C1 DD 75 04 DD 74 05 0C DD 7E 05 DD B6 04 +T 5F 00 C1 DD 75 04 DD 74 05 0C DD 7E 05 DD B6 04 R 00 00 00 00 -T 73 00 20 97 51 15 DD 6E 06 DD 66 07 06 00 09 36 +T 6D 00 20 9D 59 1D DD 6E 06 DD 66 07 06 00 09 36 R 00 00 00 00 -T 81 00 00 1E 00 +T 7B 00 00 DD 36 FD 00 R 00 00 00 00 -T 84 00 +T 80 00 R 00 00 00 00 -T 84 00 7B 92 E2 8B 00 EE 80 -R 00 00 00 00 00 05 00 00 -T 8B 00 +T 80 00 DD 7E FD 93 E2 89 00 EE 80 +R 00 00 00 00 00 07 00 00 +T 89 00 R 00 00 00 00 -T 8B 00 F2 C2 00 DD 7E 06 83 4F DD 7E 07 CE 00 47 +T 89 00 F2 BE 00 DD 7E 06 DD 86 FD 4F DD 7E 07 CE R 00 00 00 00 00 03 00 00 -T 99 00 0A DD 77 FD DD 7E 06 82 DD 77 FE DD 7E 07 +T 97 00 00 47 0A DD 77 FC E5 DD 6E 06 DD 66 07 E5 R 00 00 00 00 -T A7 00 CE 00 DD 77 FF DD 6E FE DD 66 FF 7E 02 DD +T A5 00 FD E1 E1 D5 16 00 FD 19 D1 FD 7E 00 02 DD R 00 00 00 00 -T B5 00 6E FE DD 66 FF DD 7E FD 77 1C 15 18 C2 +T B3 00 7E FC FD 77 00 DD 34 FD 1D 18 C2 R 00 00 00 00 -T C2 00 +T BE 00 R 00 00 00 00 -T C2 00 DD F9 DD E1 C9 +T BE 00 DD F9 DD E1 C9 R 00 00 00 00 -T C7 00 +T C3 00 R 00 00 00 00 -T C7 00 DD E5 DD 21 00 00 DD 39 DD CB 05 7E 28 25 +T C3 00 DD E5 DD 21 00 00 DD 39 DD CB 05 7E 28 25 R 00 00 00 00 -T D5 00 DD 7E 08 D6 0A 20 1E DD 6E 06 DD 66 07 36 +T D1 00 DD 7E 08 D6 0A 20 1E DD 6E 06 DD 66 07 36 R 00 00 00 00 -T E3 00 2D 23 DD 75 06 DD 74 07 AF DD 96 04 DD 77 +T DF 00 2D 23 DD 75 06 DD 74 07 AF DD 96 04 DD 77 R 00 00 00 00 -T F1 00 04 3E 00 DD 9E 05 DD 77 05 +T ED 00 04 3E 00 DD 9E 05 DD 77 05 R 00 00 00 00 -T FA 00 +T F6 00 R 00 00 00 00 -T FA 00 DD 7E 08 F5 33 DD 6E 06 DD 66 07 E5 DD 6E +T F6 00 DD 7E 08 F5 33 DD 6E 06 DD 66 07 E5 DD 6E R 00 00 00 00 -T 08 01 04 DD 66 05 E5 CD 00 00 F1 F1 33 DD E1 C9 +T 04 01 04 DD 66 05 E5 CD 00 00 F1 F1 33 DD E1 C9 R 00 00 00 00 00 08 00 00 -_ltoa.rel/ 1458795435 2001 2501 100664 2032 ` +_ltoa.rel/ 0 0 0 644 2032 ` XL2 H 9 areas 5 global symbols M _ltoa @@ -41971,11 +57896,11 @@ T 33 00 FC DD 66 FD E5 DD 6E 06 DD 66 07 E5 DD 6E R 00 00 00 00 T 41 00 04 DD 66 05 E5 CD 00 00 F1 F1 F1 F1 C1 7D R 00 00 00 00 02 08 01 00 -T 4F 00 C6 30 57 3E 39 92 30 04 7A C6 07 57 +T 4F 00 C6 30 5F 3E 39 93 30 04 7B C6 07 5F R 00 00 00 00 T 5B 00 R 00 00 00 00 -T 5B 00 DD 35 DB DD 6E DB 26 00 09 72 C5 DD 6E FE +T 5B 00 DD 35 DB DD 6E DB 26 00 09 73 C5 DD 6E FE R 00 00 00 00 T 69 00 DD 66 FF E5 DD 6E FC DD 66 FD E5 DD 6E 06 R 00 00 00 00 @@ -41985,11 +57910,11 @@ T 85 00 F1 F1 F1 F1 C1 DD 75 04 DD 74 05 DD 73 06 R 00 00 00 00 T 93 00 DD 72 07 7A DD B6 06 DD B6 05 DD B6 04 C2 R 00 00 00 00 -T A1 00 17 00 DD 5E 08 DD 56 09 D5 FD E1 DD 56 DB +T A1 00 17 00 DD 5E 08 DD 56 09 D5 FD E1 DD 5E DB R 00 00 00 00 00 02 00 00 T AF 00 R 00 00 00 00 -T AF 00 6A 26 00 09 7E FD 77 00 FD 23 14 7A D6 20 +T AF 00 6B 26 00 09 56 FD 72 00 FD 23 1C 7B D6 20 R 00 00 00 00 T BD 00 20 F0 FD 36 00 00 DD F9 DD E1 C9 R 00 00 00 00 @@ -42013,7 +57938,7 @@ T 19 01 06 DD 66 07 E5 DD 6E 04 DD 66 05 E5 CD R 00 00 00 00 T 26 01 00 00 21 07 00 39 F9 DD E1 C9 R 00 00 00 00 00 02 00 00 -_startup.rel/ 1458795435 2001 2501 100664 445 ` +_startup.rel/ 0 0 0 644 445 ` XL2 H 9 areas 2 global symbols M _startup @@ -42034,14 +57959,14 @@ R 00 00 04 00 T 00 00 2E 00 C9 R 00 00 04 00 -sprintf.rel/ 1458795435 2001 2501 100664 1198 ` +sprintf.rel/ 0 0 0 644 1192 ` XL2 H 9 areas 4 global symbols M sprintf O -mz80 S __print_format Ref0000 S .__.ABS. Def0000 -A _CODE size 8C flags 0 addr 0 +A _CODE size 8A flags 0 addr 0 S _vsprintf Def0020 S _sprintf Def0055 A _DATA size 0 flags 0 addr 0 @@ -42056,9 +57981,9 @@ T 00 00 R 00 00 00 00 T 00 00 DD E5 DD 21 00 00 DD 39 DD 6E 05 DD 66 06 R 00 00 00 00 -T 0E 00 E5 5E 23 56 E1 4B 42 03 71 23 70 DD 7E 04 +T 0E 00 E5 4E 23 46 E1 59 50 13 73 23 72 DD 7E 04 R 00 00 00 00 -T 1C 00 12 DD E1 C9 +T 1C 00 02 DD E1 C9 R 00 00 00 00 T 20 00 R 00 00 00 00 @@ -42068,19 +57993,19 @@ T 2E 00 46 01 C5 FD 21 06 00 FD 39 FD 4E 00 FD 46 R 00 00 00 00 T 3C 00 01 C5 E5 21 00 00 E5 CD 00 00 F1 F1 F1 F1 R 00 00 00 00 00 06 00 00 02 0A 00 00 -T 4A 00 55 5C C1 E1 E5 C5 36 00 6A 63 C9 +T 4A 00 4D 44 D1 E1 E5 D5 36 00 69 60 C9 R 00 00 00 00 T 55 00 R 00 00 00 00 -T 55 00 DD E5 DD 21 00 00 DD 39 21 08 00 39 55 5C +T 55 00 DD E5 DD 21 00 00 DD 39 21 08 00 39 4D 44 R 00 00 00 00 -T 63 00 21 04 00 39 4A 43 C5 DD 4E 06 DD 46 07 C5 +T 63 00 21 04 00 39 C5 DD 4E 06 DD 46 07 C5 E5 21 R 00 00 00 00 -T 71 00 E5 21 00 00 E5 CD 00 00 F1 F1 F1 F1 55 5C -R 00 00 00 00 00 04 00 00 02 08 00 00 -T 7F 00 DD 6E 04 DD 66 05 36 00 6A 63 DD E1 C9 +T 71 00 00 00 E5 CD 00 00 F1 F1 F1 F1 4D 44 DD 5E +R 00 00 00 00 00 02 00 00 02 06 00 00 +T 7F 00 04 DD 56 05 AF 12 69 60 DD E1 C9 R 00 00 00 00 -vprintf.rel/ 1458795436 2001 2501 100664 938 ` +vprintf.rel/ 0 0 0 644 941 ` XL2 H 9 areas 5 global symbols M vprintf @@ -42088,9 +58013,9 @@ O -mz80 S __print_format Ref0000 S _putchar Ref0000 S .__.ABS. Def0000 -A _CODE size 49 flags 0 addr 0 -S _vprintf Def000C -S _printf Def002C +A _CODE size 4A flags 0 addr 0 +S _vprintf Def000D +S _printf Def002D A _DATA size 0 flags 0 addr 0 A _INITIALIZED size 0 flags 0 addr 0 A _DABS size 0 flags 8 addr 0 @@ -42101,24 +58026,101 @@ A _INITIALIZER size 0 flags 0 addr 0 A _CABS size 0 flags 8 addr 0 T 00 00 R 00 00 00 00 -T 00 00 21 02 00 39 7E F5 33 CD 00 00 33 C9 -R 00 00 00 00 02 0A 01 00 -T 0C 00 +T 00 00 21 02 00 39 4E 06 00 C5 CD 00 00 F1 C9 +R 00 00 00 00 02 0B 01 00 +T 0D 00 R 00 00 00 00 -T 0C 00 21 04 00 39 4E 23 46 C5 21 04 00 39 4E 23 +T 0D 00 21 04 00 39 4E 23 46 C5 21 04 00 39 4E 23 R 00 00 00 00 -T 1A 00 46 C5 21 00 00 E5 21 00 00 E5 CD 00 00 F1 +T 1B 00 46 C5 21 00 00 E5 21 00 00 E5 CD 00 00 F1 R 00 00 00 00 00 09 00 00 02 0D 00 00 -T 28 00 F1 F1 F1 C9 +T 29 00 F1 F1 F1 C9 R 00 00 00 00 -T 2C 00 +T 2D 00 R 00 00 00 00 -T 2C 00 21 04 00 39 E5 21 04 00 39 4E 23 46 C5 21 +T 2D 00 21 04 00 39 E5 21 04 00 39 4E 23 46 C5 21 R 00 00 00 00 -T 3A 00 00 00 E5 21 00 00 E5 CD 00 00 F1 F1 F1 F1 +T 3B 00 00 00 E5 21 00 00 E5 CD 00 00 F1 F1 F1 F1 R 00 00 00 00 00 06 00 00 02 0A 00 00 -T 48 00 C9 +T 49 00 C9 R 00 00 00 00 + +_strcmp.rel/ 0 0 0 644 757 ` +XL2 +H 9 areas 2 global symbols +M _strcmp +O -mz80 +S .__.ABS. Def0000 +A _CODE size 3D flags 0 addr 0 +S _strcmp Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 DD E5 DD 21 00 00 DD 39 3B DD 4E 04 DD 46 +R 00 00 00 00 +T 0E 00 05 DD 5E 06 DD 56 07 D5 FD E1 +R 00 00 00 00 +T 18 00 +R 00 00 00 00 +T 18 00 0A 5F 16 00 FD 7E 00 DD 77 FF 6F 26 00 7B +R 00 00 00 00 +T 26 00 95 6F 7A 9C 67 B5 20 0B DD 7E FF B7 28 05 +R 00 00 00 00 +T 34 00 03 FD 23 18 DF +R 00 00 00 00 +T 39 00 +R 00 00 00 00 +T 39 00 33 DD E1 C9 +R 00 00 00 00 + +_memcpy.rel/ 0 0 0 644 877 ` +XL2 +H 9 areas 2 global symbols +M _memcpy +O -mz80 +S .__.ABS. Def0000 +A _CODE size 4F flags 0 addr 0 +S _memcpy Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 DD E5 DD 21 00 00 DD 39 F5 F5 DD 7E 04 DD +R 00 00 00 00 +T 0E 00 77 FC DD 7E 05 DD 77 FD DD 5E 04 DD 56 05 +R 00 00 00 00 +T 1C 00 DD 7E 06 DD 77 FE DD 7E 07 DD 77 FF DD 4E +R 00 00 00 00 +T 2A 00 08 DD 46 09 +R 00 00 00 00 +T 2E 00 +R 00 00 00 00 +T 2E 00 69 60 0B 7C B5 28 13 DD 6E FE DD 66 FF 7E +R 00 00 00 00 +T 3C 00 DD 34 FE 20 03 DD 34 FF +R 00 00 00 00 +T 44 00 +R 00 00 00 00 +T 44 00 12 13 18 E6 +R 00 00 00 00 +T 48 00 +R 00 00 00 00 +T 48 00 E1 E5 DD F9 DD E1 C9 +R 00 00 00 00 + XL2 H 14 areas 8 global symbols M crt0 @@ -42210,3 +58212,4170 @@ T 0F 00 R 00 00 0D 00 T 00 00 C9 R 00 00 0E 00 + + + + 3020 + +cv_init 9 +.__.ABS. +_cv_init +_cv_spint_handler +_cv_vdpstat +_cv_vdpreg +_cv_vint_indicator +_cv_vint_handler + + + +cv_vint 1116 +.__.ABS. +_cv_vint + + + +cv_vdpout 1857 +.__.ABS. +_cv_vdpout + + + +cv_get_vint_handler 2258 +.__.ABS. +_cv_get_vint_handler + + + +cv_set_vint_handler 2815 +.__.ABS. +_cv_set_vint_handler + + + +cv_get_vint_frequency 3427 +.__.ABS. +_cv_get_vint_frequency + + + +cv_get_controller_state 3684 +.__.ABS. +_cv_get_controller_state + + + +cv_set_spint_handler 5183 +.__.ABS. +_cv_set_spint_handler + + + +cv_get_external_video 5774 +.__.ABS. +_cv_get_external_video + + + +cv_set_external_video 6352 +.__.ABS. +_cv_set_external_video + + + +cv_get_screen_active 7034 +.__.ABS. +_cv_get_screen_active + + + +cv_set_screen_active 7609 +.__.ABS. +_cv_set_screen_active + + + +cv_get_screen_mode 8400 +.__.ABS. +_cv_get_screen_mode + + + +cv_set_screen_mode 8978 +.__.ABS. +_cv_set_screen_mode + + + +cv_get_sprite_big 9776 +.__.ABS. +_cv_get_sprite_big + + + +cv_set_sprite_big 10342 +.__.ABS. +_cv_set_sprite_big + + + +cv_get_sprite_collission 11124 +.__.ABS. +_cv_get_sprite_collission + + + +cv_get_sprite_invalid 11712 +.__.ABS. +_cv_get_sprite_invalid + + + +cv_get_sprite_magnification 12427 +.__.ABS. +_cv_get_sprite_magnification + + + +cv_set_sprite_magnification 13011 +.__.ABS. +_cv_set_sprite_magnification + + + +cv_set_character_pattern_table 13708 +.__.ABS. +_cv_set_character_pattern_t + + + +cv_set_color_table 14371 +.__.ABS. +_cv_set_color_table + + + +cv_set_colors 15046 +.__.ABS. +_cv_set_colors + + + +cv_set_image_table 15665 +.__.ABS. +_cv_set_image_table + + + +cv_set_sprite_attribute_table 16293 +.__.ABS. +_cv_set_sprite_attribute_table + + + +cv_set_sprite_pattern_table 17001 +.__.ABS. +_cv_set_sprite_pattern_table + + + +cv_set_read_vram_address 17659 +.__.ABS. +_cv_set_read_vram_address + + + +cv_set_write_vram_address 18105 +.__.ABS. +_cv_set_write_vram_address + + + +cv_memtovmemcpy_slow 18575 +.__.ABS. +_cv_memtovmemcpy_slow + + + +cv_vmemtomemcpy_slow 19039 +.__.ABS. +_cv_vmemtomemcpy_slow + + + +cv_vmemset_slow 19521 +.__.ABS. +_cv_vmemset_slow + + + +cv_memtovmemcpy_fast 19946 +.__.ABS. +_cv_memtovmemcpy_fast + + + +cv_vmemtomemcpy_fast 20401 +.__.ABS. +_cv_vmemtomemcpy_fast + + + +cv_vmemset_fast 20856 +.__.ABS. +_cv_vmemset_fast + + + +cv_voutb 21275 +.__.ABS. + + + +cv_vinb 21684 +.__.ABS. + + + +cv_set_attenuation 22091 +.__.ABS. +_cv_set_attenuation + + + +cv_set_frequency 22854 +.__.ABS. +_cv_set_frequency + + + +cv_set_noise 23740 +.__.ABS. +_cv_set_noise + + + + + + + +cv_init + +XL2 +H 9 areas 8 global symbols +M cv_init +O -mz80 +S .__.ABS. Def0000 +S _cv_set_attenuation Ref0000 +A _CODE size 23 flags 0 addr 0 +S _cv_init Def0000 +A _DATA size 6 flags 0 addr 0 +S _cv_spint_handler Def0000 +S _cv_vdpstat Def0002 +S _cv_vdpreg Def0004 +S _cv_vint_indicator Def0003 +A _INITIALIZED size 2 flags 0 addr 0 +S _cv_vint_handler Def0000 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 2 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 01 00 +T 00 00 +R 00 00 01 00 +T 02 00 +R 00 00 01 00 +T 02 00 +R 00 00 01 00 +T 03 00 +R 00 00 01 00 +T 03 00 +R 00 00 01 00 +T 04 00 +R 00 00 01 00 +T 04 00 +R 00 00 01 00 +T 00 00 +R 00 00 02 00 +T 00 00 +R 00 00 02 00 +T 00 00 +R 00 00 00 00 +T 00 00 21 05 00 36 A0 21 00 00 E5 CD 00 00 21 +R 00 00 00 00 00 03 01 00 02 0C 01 00 +T 0D 00 02 00 E3 CD 00 00 21 04 00 E3 CD 00 00 21 +R 00 00 00 00 02 06 01 00 02 0D 01 00 +T 1B 00 06 00 E3 CD 00 00 F1 C9 +R 00 00 00 00 02 06 01 00 +T 00 00 +R 00 00 07 00 +T 00 00 00 00 +R 00 00 07 00 + + + + + + +cv_vint + +XL2 +H 9 areas 6 global symbols +M cv_vint +O -mz80 +S _cv_vint_handler Ref0000 +S _cv_vdpstat Ref0000 +S .__.ABS. Def0000 +S ___sdcc_call_hl Ref0000 +S _cv_vint_indicator Ref0000 +A _CODE size 18 flags 0 addr 0 +S _cv_vint Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 21 00 00 36 FF DB BF 32 00 00 3A 01 00 21 +R 00 00 00 00 02 03 04 00 02 0A 01 00 02 0D 00 00 +T 0E 00 00 00 B6 C8 2A 00 00 C3 00 00 +R 00 00 00 00 02 02 00 00 02 07 00 00 02 0A 03 00 + + + + + + +cv_vdpout + +XL2 +H 1 areas 3 global symbols +M cv_vdpout +S .__.ABS. Def0000 +S _cv_vint_indicator Ref0000 +A _CODE size 18 flags 0 addr 0 +S _cv_vdpout Def0000 +T 00 00 +R 00 00 00 00 +T 00 00 E1 C1 C5 +R 00 00 00 00 +T 03 00 +R 00 00 00 00 +T 03 00 DB BF AF 32 00 00 78 D3 BF 3E 80 B1 D3 BF +R 00 00 00 00 02 06 01 00 +T 11 00 3A 00 00 B7 20 EC E9 +R 00 00 00 00 02 03 01 00 + + + + + + +cv_get_vint_handler + +XL2 +H 9 areas 3 global symbols +M cv_get_vint_handler +O -mz80 +S _cv_vint_handler Ref0000 +S .__.ABS. Def0000 +A _CODE size 4 flags 0 addr 0 +S _cv_get_vint_handler Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 2A 00 00 C9 +R 00 00 00 00 02 03 00 00 + + + + + + +cv_set_vint_handler + +XL2 +H 9 areas 3 global symbols +M cv_set_vint_handler +O -mz80 +S _cv_vint_handler Ref0000 +S .__.ABS. Def0000 +A _CODE size F flags 0 addr 0 +S _cv_set_vint_handler Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 F3 11 00 00 21 02 00 39 01 02 00 ED B0 FB +R 00 00 00 00 02 04 00 00 +T 0E 00 C9 +R 00 00 00 00 + + + + + + +cv_get_vint_frequency + +XL2 +H 1 areas 2 global symbols +M cv_get_vint_frequency +S .__.ABS. Def0000 +A _CODE size 4 flags 0 addr 0 +S _cv_get_vint_frequency Def0000 +T 00 00 +R 00 00 00 00 +T 00 00 2A 69 00 C9 +R 00 00 00 00 + + + + + + +cv_get_controller_state + +XL2 +H 9 areas 3 global symbols +M cv_get_controller_state +O -mz80 +S .__.ABS. Def0000 +S ___sdcc_enter_ix Ref0000 +A _CODE size 77 flags 0 addr 0 +S _cv_get_controller_state Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 CD 00 00 3B 3E 2A D3 80 DD 7E 06 B7 28 04 +R 00 00 00 00 02 03 01 00 +T 0E 00 DB FF 18 02 +R 00 00 00 00 +T 12 00 +R 00 00 00 00 +T 12 00 DB FC +R 00 00 00 00 +T 14 00 +R 00 00 00 00 +T 14 00 DD 77 FF DD 4E 04 DD 46 05 DD 7E FF E6 0F +R 00 00 00 00 +T 22 00 5F 21 67 00 16 00 19 7E 02 3E 2A D3 C0 DD +R 00 00 00 00 00 04 00 00 +T 30 00 7E 06 B7 28 04 DB FF 18 02 +R 00 00 00 00 +T 39 00 +R 00 00 00 00 +T 39 00 DB FC +R 00 00 00 00 +T 3B 00 +R 00 00 00 00 +T 3B 00 2F 57 DD CB FF 76 20 04 CB FA 18 02 +R 00 00 00 00 +T 47 00 +R 00 00 00 00 +T 47 00 CB BA +R 00 00 00 00 +T 49 00 +R 00 00 00 00 +T 49 00 7B D6 08 20 04 CB E2 18 02 +R 00 00 00 00 +T 52 00 +R 00 00 00 00 +T 52 00 CB A2 +R 00 00 00 00 +T 54 00 +R 00 00 00 00 +T 54 00 7B D6 04 20 04 CB EA 18 02 +R 00 00 00 00 +T 5D 00 +R 00 00 00 00 +T 5D 00 CB AA +R 00 00 00 00 +T 5F 00 +R 00 00 00 00 +T 5F 00 69 60 23 72 33 DD E1 C9 +R 00 00 00 00 +T 67 00 +R 00 00 00 00 +T 67 00 0F 08 04 05 0F 07 0B 02 0F 0A 00 09 03 01 +R 00 00 00 00 +T 75 00 06 0F +R 00 00 00 00 + + + + + + +cv_set_spint_handler + +XL2 +H 9 areas 3 global symbols +M cv_set_spint_handler +O -mz80 +S _cv_spint_handler Ref0000 +S .__.ABS. Def0000 +A _CODE size E flags 0 addr 0 +S _cv_set_spint_handler Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 F3 C1 D1 D5 C5 ED 53 00 00 7A B3 C8 FB C9 +R 00 00 00 00 02 09 00 00 + + + + + + +cv_get_external_video + +XL2 +H 9 areas 3 global symbols +M cv_get_external_video +O -mz80 +S .__.ABS. Def0000 +S _cv_vdpreg Ref0000 +A _CODE size B flags 0 addr 0 +S _cv_get_external_video Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 3A 00 00 E6 02 67 AF BC 17 6F C9 +R 00 00 00 00 02 03 01 00 + + + + + + +cv_set_external_video + +XL2 +H 9 areas 4 global symbols +M cv_set_external_video +O -mz80 +S .__.ABS. Def0000 +S _cv_vdpreg Ref0000 +S _cv_vdpout Ref0000 +A _CODE size 1B flags 0 addr 0 +S _cv_set_external_video Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 21 00 00 56 CB 82 FD 21 02 00 FD 39 FD 7E +R 00 00 00 00 02 03 01 00 +T 0E 00 00 B2 77 F5 33 AF F5 33 CD 00 00 F1 C9 +R 00 00 00 00 02 0B 02 00 + + + + + + +cv_get_screen_active + +XL2 +H 9 areas 3 global symbols +M cv_get_screen_active +O -mz80 +S .__.ABS. Def0000 +S _cv_vdpreg Ref0000 +A _CODE size B flags 0 addr 0 +S _cv_get_screen_active Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 3A 01 00 E6 40 67 AF BC 17 6F C9 +R 00 00 00 00 02 03 01 00 + + + + + + +cv_set_screen_active + +XL2 +H 9 areas 4 global symbols +M cv_set_screen_active +O -mz80 +S .__.ABS. Def0000 +S _cv_vdpreg Ref0000 +S _cv_vdpout Ref0000 +A _CODE size 23 flags 0 addr 0 +S _cv_set_screen_active Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 21 01 00 FD 21 02 00 FD 39 FD CB 00 46 28 +R 00 00 00 00 02 03 01 00 +T 0E 00 04 16 40 18 02 +R 00 00 00 00 +T 13 00 +R 00 00 00 00 +T 13 00 16 00 +R 00 00 00 00 +T 15 00 +R 00 00 00 00 +T 15 00 7E E6 BF B2 77 57 1E 01 D5 CD 00 00 F1 C9 +R 00 00 00 00 02 0C 02 00 + + + + + + +cv_get_screen_mode + +XL2 +H 9 areas 3 global symbols +M cv_get_screen_mode +O -mz80 +S .__.ABS. Def0000 +S _cv_vdpreg Ref0000 +A _CODE size E flags 0 addr 0 +S _cv_get_screen_mode Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 21 00 00 7E E6 02 57 23 7E E6 18 B2 6F C9 +R 00 00 00 00 02 03 01 00 + + + + + + +cv_set_screen_mode + +XL2 +H 9 areas 4 global symbols +M cv_set_screen_mode +O -mz80 +S .__.ABS. Def0000 +S _cv_vdpreg Ref0000 +S _cv_vdpout Ref0000 +A _CODE size 32 flags 0 addr 0 +S _cv_set_screen_mode Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 11 00 00 21 02 00 39 7E E6 02 47 1A E6 FD +R 00 00 00 00 02 03 01 00 +T 0E 00 B0 12 D5 F5 33 AF F5 33 CD 00 00 F1 D1 13 +R 00 00 00 00 02 0B 02 00 +T 1C 00 21 02 00 39 7E E6 18 47 1A E6 E7 B0 12 57 +R 00 00 00 00 +T 2A 00 1E 01 D5 CD 00 00 F1 C9 +R 00 00 00 00 02 06 02 00 + + + + + + +cv_get_sprite_big + +XL2 +H 9 areas 3 global symbols +M cv_get_sprite_big +O -mz80 +S .__.ABS. Def0000 +S _cv_vdpreg Ref0000 +A _CODE size B flags 0 addr 0 +S _cv_get_sprite_big Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 3A 01 00 E6 02 67 AF BC 17 6F C9 +R 00 00 00 00 02 03 01 00 + + + + + + +cv_set_sprite_big + +XL2 +H 9 areas 4 global symbols +M cv_set_sprite_big +O -mz80 +S .__.ABS. Def0000 +S _cv_vdpreg Ref0000 +S _cv_vdpout Ref0000 +A _CODE size 23 flags 0 addr 0 +S _cv_set_sprite_big Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 21 01 00 FD 21 02 00 FD 39 FD CB 00 46 28 +R 00 00 00 00 02 03 01 00 +T 0E 00 04 16 02 18 02 +R 00 00 00 00 +T 13 00 +R 00 00 00 00 +T 13 00 16 00 +R 00 00 00 00 +T 15 00 +R 00 00 00 00 +T 15 00 7E E6 FD B2 77 57 1E 01 D5 CD 00 00 F1 C9 +R 00 00 00 00 02 0C 02 00 + + + + + + +cv_get_sprite_collission + +XL2 +H 9 areas 3 global symbols +M cv_get_sprite_collission +O -mz80 +S _cv_vdpstat Ref0000 +S .__.ABS. Def0000 +A _CODE size B flags 0 addr 0 +S _cv_get_sprite_collission Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 3A 00 00 E6 20 67 AF BC 17 6F C9 +R 00 00 00 00 02 03 00 00 + + + + + + +cv_get_sprite_invalid + +XL2 +H 9 areas 3 global symbols +M cv_get_sprite_invalid +O -mz80 +S _cv_vdpstat Ref0000 +S .__.ABS. Def0000 +A _CODE size 1E flags 0 addr 0 +S _cv_get_sprite_invalid Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 21 03 00 39 7E 2B B6 28 0A C1 D1 D5 C5 3A +R 00 00 00 00 +T 0E 00 00 00 E6 1F 12 +R 00 00 00 00 02 02 00 00 +T 13 00 +R 00 00 00 00 +T 13 00 3A 00 00 E6 40 67 AF BC 17 6F C9 +R 00 00 00 00 02 03 00 00 + + + + + + +cv_get_sprite_magnification + +XL2 +H 9 areas 3 global symbols +M cv_get_sprite_magnification +O -mz80 +S .__.ABS. Def0000 +S _cv_vdpreg Ref0000 +A _CODE size 7 flags 0 addr 0 +S _cv_get_sprite_magnification Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 3A 01 00 E6 01 6F C9 +R 00 00 00 00 02 03 01 00 + + + + + + +cv_set_sprite_magnification + +XL2 +H 9 areas 4 global symbols +M cv_set_sprite_magnification +O -mz80 +S .__.ABS. Def0000 +S _cv_vdpreg Ref0000 +S _cv_vdpout Ref0000 +A _CODE size 1A flags 0 addr 0 +S _cv_set_sprite_magnification Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 21 01 00 56 CB 82 FD 21 02 00 FD 39 FD 7E +R 00 00 00 00 02 03 01 00 +T 0E 00 00 B2 77 57 1E 01 D5 CD 00 00 F1 C9 +R 00 00 00 00 02 0A 02 00 + + + + + + +cv_set_character_pattern_table + +XL2 +H 9 areas 3 global symbols +M cv_set_character_pattern_table +O -mz80 +S .__.ABS. Def0000 +S _cv_vdpout Ref0000 +A _CODE size 18 flags 0 addr 0 +S _cv_set_character_pattern_t Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 21 03 00 39 7E 0F 0F 0F E6 1F 67 2E 00 E5 +R 00 00 00 00 +T 0E 00 33 3E 04 F5 33 CD 00 00 F1 C9 +R 00 00 00 00 02 08 01 00 + + + + + + +cv_set_color_table + +XL2 +H 9 areas 3 global symbols +M cv_set_color_table +O -mz80 +S .__.ABS. Def0000 +S _cv_vdpout Ref0000 +A _CODE size 18 flags 0 addr 0 +S _cv_set_color_table Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 C1 E1 E5 C5 06 06 +R 00 00 00 00 +T 06 00 +R 00 00 00 00 +T 06 00 CB 3C CB 1D 10 FA 65 E5 33 3E 03 F5 33 CD +R 00 00 00 00 +T 14 00 00 00 F1 C9 +R 00 00 00 00 02 02 01 00 + + + + + + +cv_set_colors + +XL2 +H 9 areas 3 global symbols +M cv_set_colors +O -mz80 +S .__.ABS. Def0000 +S _cv_vdpout Ref0000 +A _CODE size 19 flags 0 addr 0 +S _cv_set_colors Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 21 02 00 39 7E 07 07 07 07 E6 F0 21 03 00 +R 00 00 00 00 +T 0E 00 39 B6 57 1E 07 D5 CD 00 00 F1 C9 +R 00 00 00 00 02 09 01 00 + + + + + + +cv_set_image_table + +XL2 +H 9 areas 3 global symbols +M cv_set_image_table +O -mz80 +S .__.ABS. Def0000 +S _cv_vdpout Ref0000 +A _CODE size 17 flags 0 addr 0 +S _cv_set_image_table Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 21 03 00 39 7E 0F 0F E6 3F 67 2E 00 E5 33 +R 00 00 00 00 +T 0E 00 3E 02 F5 33 CD 00 00 F1 C9 +R 00 00 00 00 02 07 01 00 + + + + + + +cv_set_sprite_attribute_table + +XL2 +H 9 areas 3 global symbols +M cv_set_sprite_attribute_table +O -mz80 +S .__.ABS. Def0000 +S _cv_vdpout Ref0000 +A _CODE size 18 flags 0 addr 0 +S _cv_set_sprite_attribute_table Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 C1 E1 E5 C5 06 07 +R 00 00 00 00 +T 06 00 +R 00 00 00 00 +T 06 00 CB 3C CB 1D 10 FA 65 E5 33 3E 05 F5 33 CD +R 00 00 00 00 +T 14 00 00 00 F1 C9 +R 00 00 00 00 02 02 01 00 + + + + + + +cv_set_sprite_pattern_table + +XL2 +H 9 areas 3 global symbols +M cv_set_sprite_pattern_table +O -mz80 +S .__.ABS. Def0000 +S _cv_vdpout Ref0000 +A _CODE size 18 flags 0 addr 0 +S _cv_set_sprite_pattern_table Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 21 03 00 39 7E 0F 0F 0F E6 1F 67 2E 00 E5 +R 00 00 00 00 +T 0E 00 33 3E 06 F5 33 CD 00 00 F1 C9 +R 00 00 00 00 02 08 01 00 + + + + + + +cv_set_read_vram_address + +XL2 +H 1 areas 3 global symbols +M cv_set_read_vram_address +S .__.ABS. Def0000 +S _cv_vint_indicator Ref0000 +A _CODE size 18 flags 0 addr 0 +S _cv_set_read_vram_address Def0000 +T 00 00 +R 00 00 00 00 +T 00 00 FD E1 E1 E5 +R 00 00 00 00 +T 04 00 +R 00 00 00 00 +T 04 00 DB BF AF 32 00 00 7D D3 BF 7C D3 BF 3A +R 00 00 00 00 02 06 01 00 +T 11 00 00 00 B7 20 EE FD E9 +R 00 00 00 00 02 02 01 00 + + + + + + +cv_set_write_vram_address + +XL2 +H 1 areas 3 global symbols +M cv_set_write_vram_address +S .__.ABS. Def0000 +S _cv_vint_indicator Ref0000 +A _CODE size 1B flags 0 addr 0 +S _cv_set_write_vram_address Def0000 +T 00 00 +R 00 00 00 00 +T 00 00 FD E1 E1 E5 +R 00 00 00 00 +T 04 00 +R 00 00 00 00 +T 04 00 DB BF AF 32 00 00 7D D3 BF 7C F6 40 D3 BF +R 00 00 00 00 02 06 01 00 +T 12 00 3A 00 00 B7 C2 04 00 FD E9 +R 00 00 00 00 02 03 01 00 00 07 00 00 + + + + + + +cv_memtovmemcpy_slow + +XL2 +H 1 areas 2 global symbols +M cv_memtovmemcpy_slow +S .__.ABS. Def0000 +A _CODE size 21 flags 0 addr 0 +S _cv_memtovmemcpy_slow Def0000 +T 00 00 +R 00 00 00 00 +T 00 00 21 02 00 39 5E 23 56 23 46 23 7E EB 57 B0 +R 00 00 00 00 +T 0E 00 28 10 0E BE 78 B7 28 01 14 +R 00 00 00 00 +T 17 00 +R 00 00 00 00 +T 17 00 ED A3 00 C2 17 00 15 20 F7 +R 00 00 00 00 00 06 00 00 +T 20 00 +R 00 00 00 00 +T 20 00 C9 +R 00 00 00 00 + + + + + + +cv_vmemtomemcpy_slow + +XL2 +H 1 areas 2 global symbols +M cv_vmemtomemcpy_slow +S .__.ABS. Def0000 +A _CODE size 23 flags 0 addr 0 +S _cv_vmemtomemcpy_slow Def0000 +T 00 00 +R 00 00 00 00 +T 00 00 21 02 00 39 5E 23 56 23 46 23 7E EB 57 B0 +R 00 00 00 00 +T 0E 00 28 12 0E BE 78 B7 28 01 14 +R 00 00 00 00 +T 17 00 +R 00 00 00 00 +T 17 00 ED A2 00 00 C2 17 00 15 C2 17 00 +R 00 00 00 00 00 07 00 00 00 0B 00 00 +T 22 00 +R 00 00 00 00 +T 22 00 C9 +R 00 00 00 00 + + + + + + +cv_vmemset_slow + +XL2 +H 1 areas 2 global symbols +M cv_vmemset_slow +S .__.ABS. Def0000 +A _CODE size 1D flags 0 addr 0 +S _cv_vmemset_slow Def0000 +T 00 00 +R 00 00 00 00 +T 00 00 FD E1 D1 C1 C5 D5 78 41 4F B0 28 0F 78 B7 +R 00 00 00 00 +T 0E 00 7B 28 01 0C +R 00 00 00 00 +T 12 00 +R 00 00 00 00 +T 12 00 D3 BE 00 00 10 FA 0D 20 F7 +R 00 00 00 00 +T 1B 00 +R 00 00 00 00 +T 1B 00 FD E9 +R 00 00 00 00 + + + + + + +cv_memtovmemcpy_fast + +XL2 +H 1 areas 2 global symbols +M cv_memtovmemcpy_fast +S .__.ABS. Def0000 +A _CODE size 1E flags 0 addr 0 +S _cv_memtovmemcpy_fast Def0000 +T 00 00 +R 00 00 00 00 +T 00 00 21 02 00 39 5E 23 56 23 46 23 7E EB 57 B0 +R 00 00 00 00 +T 0E 00 28 0D 0E BE 78 B7 28 01 14 +R 00 00 00 00 +T 17 00 +R 00 00 00 00 +T 17 00 ED B3 15 C2 17 00 +R 00 00 00 00 00 06 00 00 +T 1D 00 +R 00 00 00 00 +T 1D 00 C9 +R 00 00 00 00 + + + + + + +cv_vmemtomemcpy_fast + +XL2 +H 1 areas 2 global symbols +M cv_vmemtomemcpy_fast +S .__.ABS. Def0000 +A _CODE size 1E flags 0 addr 0 +S _cv_vmemtomemcpy_fast Def0000 +T 00 00 +R 00 00 00 00 +T 00 00 21 02 00 39 5E 23 56 23 46 23 7E EB 57 B0 +R 00 00 00 00 +T 0E 00 28 0D 0E BE 78 B7 28 01 14 +R 00 00 00 00 +T 17 00 +R 00 00 00 00 +T 17 00 ED B2 15 C2 17 00 +R 00 00 00 00 00 06 00 00 +T 1D 00 +R 00 00 00 00 +T 1D 00 C9 +R 00 00 00 00 + + + + + + +cv_vmemset_fast + +XL2 +H 1 areas 2 global symbols +M cv_vmemset_fast +S .__.ABS. Def0000 +A _CODE size 1B flags 0 addr 0 +S _cv_vmemset_fast Def0000 +T 00 00 +R 00 00 00 00 +T 00 00 FD E1 D1 C1 C5 D5 78 41 4F B0 28 0D 78 B7 +R 00 00 00 00 +T 0E 00 7B 28 01 0C +R 00 00 00 00 +T 12 00 +R 00 00 00 00 +T 12 00 D3 BE 10 FC 0D 20 F9 +R 00 00 00 00 +T 19 00 +R 00 00 00 00 +T 19 00 FD E9 +R 00 00 00 00 + + + + + + +cv_voutb + +XL2 +H 9 areas 1 global symbols +M cv_voutb +O -mz80 +S .__.ABS. Def0000 +A _CODE size 0 flags 0 addr 0 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 + + + + + + +cv_vinb + +XL2 +H 9 areas 1 global symbols +M cv_vinb +O -mz80 +S .__.ABS. Def0000 +A _CODE size 0 flags 0 addr 0 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 + + + + + + +cv_set_attenuation + +XL2 +H 9 areas 3 global symbols +M cv_set_attenuation +O -mz80 +S .__.ABS. Def0000 +S ___sdcc_enter_ix Ref0000 +A _CODE size 2C flags 0 addr 0 +S _cv_set_attenuation Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 CD 00 00 DD 34 04 DD CB 05 3E DD 7E 05 E6 +R 00 00 00 00 02 03 01 00 +T 0E 00 0F DD 77 05 B7 20 04 DD 36 05 0F +R 00 00 00 00 +T 19 00 +R 00 00 00 00 +T 19 00 DD 7E 04 07 07 07 07 E6 F0 CB FF DD B6 05 +R 00 00 00 00 +T 27 00 D3 FF DD E1 C9 +R 00 00 00 00 + + + + + + +cv_set_frequency + +XL2 +H 9 areas 3 global symbols +M cv_set_frequency +O -mz80 +S .__.ABS. Def0000 +S ___sdcc_enter_ix Ref0000 +A _CODE size 41 flags 0 addr 0 +S _cv_set_frequency Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 CD 00 00 06 05 +R 00 00 00 00 02 03 01 00 +T 05 00 +R 00 00 00 00 +T 05 00 DD CB 06 3E DD CB 05 1E 10 F6 DD 7E 04 07 +R 00 00 00 00 +T 13 00 07 07 07 E6 F0 CB FF 4F DD 7E 05 E6 0F 5F +R 00 00 00 00 +T 21 00 16 00 06 00 79 B3 67 78 B2 7C D3 FF DD 66 +R 00 00 00 00 +T 2F 00 05 DD 6E 06 06 04 +R 00 00 00 00 +T 35 00 +R 00 00 00 00 +T 35 00 CB 3D CB 1C 10 FA 7C D3 FF DD E1 C9 +R 00 00 00 00 + + + + + + +cv_set_noise + +XL2 +H 9 areas 2 global symbols +M cv_set_noise +O -mz80 +S .__.ABS. Def0000 +A _CODE size 15 flags 0 addr 0 +S _cv_set_noise Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 16 E0 21 02 00 39 CB 46 28 02 16 E4 +R 00 00 00 00 +T 0C 00 +R 00 00 00 00 +T 0C 00 7A 21 03 00 39 B6 D3 FF C9 +R 00 00 00 00 + + + + + + + + +XL2 +H C areas B global symbols +M crt0 +S _cv_spint_handler Ref0000 +S _main Ref0000 +S _cv_init Ref0000 +S _cv_vint Ref0000 +S .__.ABS. Def0000 +S s__INITIALIZED Ref0000 +S ___sdcc_call_hl Ref0000 +S l__INITIALIZER Ref0000 +S s__INITIALIZER Ref0000 +A _CODE size 47 flags 0 addr 0 +S _cv_start Def0000 +A _HEADER size 0 flags 8 addr 0 +A _HEADER0 size 2C flags 8 addr 8000 +A _INITIALIZER size 0 flags 0 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size F flags 0 addr 0 +S gsinit Def0000 +A _GSFINAL size 1 flags 0 addr 0 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _BSEG size 0 flags 0 addr 0 +A _BSS size 0 flags 0 addr 0 +A _HEAP size 0 flags 0 addr 0 +T 00 80 +R 00 00 02 00 +T 00 80 55 AA 00 00 00 00 00 00 00 00 00 00 C3 +R 00 00 02 00 00 0C 00 00 +T 0D 80 00 00 C3 00 00 C3 00 00 C3 00 00 C3 00 00 +R 00 00 02 00 +T 1B 80 C3 00 00 C3 2B 00 C3 1A 00 20 2F 20 2F 20 +R 00 00 02 00 00 06 00 00 00 09 00 00 +T 29 80 4E 4F 54 +R 00 00 02 00 +T 00 00 +R 00 00 00 00 +T 00 00 31 00 74 01 FF 03 21 00 70 36 00 5D 54 13 +R 00 00 00 00 +T 0E 00 ED B0 CD 00 00 CD 00 00 CD 00 00 C7 +R 00 00 00 00 00 05 05 00 02 08 02 00 02 0B 01 00 +T 1A 00 +R 00 00 00 00 +T 1A 00 F5 C5 D5 E5 FD E5 CD 00 00 FD E1 E1 D1 C1 +R 00 00 00 00 02 09 03 00 +T 28 00 F1 ED 45 +R 00 00 00 00 +T 2B 00 +R 00 00 00 00 +T 2B 00 F5 C5 D5 E5 FD E5 DB FC 47 DB FF 4F C5 2A +R 00 00 00 00 +T 39 00 00 00 CD 00 00 F1 FD E1 E1 D1 C1 FB ED 4D +R 00 00 00 00 02 02 00 00 02 05 06 00 +T 00 00 +R 00 00 05 00 +T 00 00 01 00 00 78 B1 28 08 11 00 00 21 00 00 ED +R 00 00 05 00 02 03 07 00 02 0A 05 00 02 0D 08 00 +T 0E 00 B0 +R 00 00 05 00 +T 0F 00 +R 00 00 05 00 +T 00 00 C9 +R 00 00 06 00 + + + + 2451 + +cvu_get_spinner 9 +.__.ABS. +_cvu_get_spinner +_cvu_spint_handler +_cvu_spinners + + + +cvu_set_sprite_x 1305 +.__.ABS. +_cvu_set_sprite_x + + + +cvu_get_sprite_x 1972 +.__.ABS. +_cvu_get_sprite_x + + + +cvu_set_sprite_y 2300 +.__.ABS. +_cvu_set_sprite_y + + + +cvu_get_sprite_y 2770 +.__.ABS. +_cvu_get_sprite_y + + + +cvu_set_sprite_xy 3071 +.__.ABS. +_cvu_set_sprite_xy + + + +cvu_get_sprite_color 3847 +.__.ABS. +_cvu_get_sprite_color + + + +cvu_memtovmemcpy 4392 +.__.ABS. +_cvu_memtovmemcpy + + + +cvu_vmemtomemcpy 5526 +.__.ABS. +_cvu_vmemtomemcpy + + + +cvu_vmemset 6668 +.__.ABS. +_cvu_vmemset + + + +cvu_voutb 7777 +.__.ABS. +_cvu_voutb + + + +cvu_vinb 8385 +.__.ABS. +_cvu_vinb + + + +cvu_play_music 8945 +.__.ABS. +_cvu_play_music + + + +cvu_init_music 14519 +.__.ABS. +_cvu_init_music +_CVU_EMPTY_MUSIC +_CVU_VOLUME_DEFAULT + + + +cvu_tuning_iso16_equal 15569 +.__.ABS. +_CVU_TUNING_ISO16_EQUAL + + + +cvu_tuning_scientific_equal 16219 +.__.ABS. +_CVU_TUNING_SCIENTIFIC_EQUAL + + + +cvu_init_huffman 16884 +.__.ABS. +_cvu_init_huffman + + + +cvu_init_rle 17753 +.__.ABS. +_cvu_init_rle + + + +cvu_get_rle 18431 +.__.ABS. +_cvu_get_rle + + + +cvu_init_lzk 19165 +.__.ABS. +_cvu_init_lzk + + + +cvu_get_lzk 19941 +.__.ABS. +_cvu_get_lzk + + + +cvu_get_huffman 22225 +.__.ABS. +_cvu_get_huffman + + + +cvu_compression 23142 +.__.ABS. +_cvu_memtovmemcpy_compression +_cvu_init_compression +_cvu_get_compression +__common_state + + + +cvu_memcpy_compression 25090 +.__.ABS. +_cvu_memcpy_compression + + + +_read_from_array 26146 +.__.ABS. +__read_from_array + + + +cvu_fmul2 26487 +.__.ABS. +_cvu_fmul2 +_cvu_s_16_16_mul + + + +cvu_fdiv2 27789 +.__.ABS. +_cvu_fdiv2 + + + +cvu_fsincos 28802 +.__.ABS. +_cvu_fsintable +_cvu_fcos +_cvu_fsin + + + +cvu_fatan 30739 +.__.ABS. +_cvu_fatan2 + + + +_u_16_16_mul 32681 +.__.ABS. +__u_16_16_mul + + + +cvu_c 33485 +.__.ABS. +_cvu_cfmul +_cvu_cdot + + + +cvu_cmul 34524 +.__.ABS. +_cvu_cmul + + + +cvu_cabs 35379 +.__.ABS. +_cvu_cabs + + + +cvu_c_from_polar 36083 +.__.ABS. +_cvu_c_from_polar + + + + + + + +cvu_get_spinner + +XL2 +H 9 areas 5 global symbols +M cvu_get_spinner +O -mz80 +S .__.ABS. Def0000 +S _cv_set_spint_handler Ref0000 +A _CODE size 62 flags 0 addr 0 +S _cvu_get_spinner Def003D +S _cvu_spint_handler Def0000 +A _DATA size 2 flags 0 addr 0 +S _cvu_spinners Def0000 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 01 00 +T 00 00 +R 00 00 01 00 +T 00 00 +R 00 00 00 00 +T 00 00 21 02 00 39 7E E6 10 28 16 21 02 00 39 7E +R 00 00 00 00 +T 0E 00 E6 20 28 09 11 00 00 1A C6 FF 12 18 04 +R 00 00 00 00 00 07 01 00 +T 1B 00 +R 00 00 00 00 +T 1B 00 21 00 00 34 +R 00 00 00 00 00 03 01 00 +T 1F 00 +R 00 00 00 00 +T 1F 00 21 03 00 39 7E E6 10 C8 21 03 00 39 7E E6 +R 00 00 00 00 +T 2D 00 20 28 08 11 01 00 1A C6 FF 12 C9 +R 00 00 00 00 00 06 01 00 +T 38 00 +R 00 00 00 00 +T 38 00 21 01 00 34 C9 +R 00 00 00 00 00 03 01 00 +T 3D 00 +R 00 00 00 00 +T 3D 00 21 00 00 E5 CD 00 00 F1 3E 00 00 21 02 00 +R 00 00 00 00 02 07 01 00 09 0B 01 00 +T 4A 00 39 86 5F 3E 00 00 CE 00 57 1A 47 AF 12 C5 +R 00 00 00 00 89 06 01 00 +T 57 00 21 00 00 E5 CD 00 00 F1 C1 68 C9 +R 00 00 00 00 00 03 00 00 02 07 01 00 + + + + + + +cvu_set_sprite_x + +XL2 +H 1 areas 2 global symbols +M cvu_set_sprite_x +S .__.ABS. Def0000 +A _CODE size 3C flags 0 addr 0 +S _cvu_set_sprite_x Def0000 +T 00 00 +R 00 00 00 00 +T 00 00 E1 FD E1 C1 C5 FD E5 79 D6 E0 78 DE FF F2 +R 00 00 00 00 +T 0E 00 14 00 06 FF 0E E0 +R 00 00 00 00 00 02 00 00 +T 14 00 +R 00 00 00 00 +T 14 00 3E FF 91 3E 00 98 F2 21 00 06 00 0E FF +R 00 00 00 00 00 09 00 00 +T 21 00 +R 00 00 00 00 +T 21 00 CB 78 CA 30 00 FD CB 03 FE 79 C6 20 4F 18 +R 00 00 00 00 00 05 00 00 +T 2F 00 08 +R 00 00 00 00 +T 30 00 +R 00 00 00 00 +T 30 00 3E 0F FD A6 03 FD 77 03 +R 00 00 00 00 +T 38 00 +R 00 00 00 00 +T 38 00 FD 71 01 E9 +R 00 00 00 00 + + + + + + +cvu_get_sprite_x + +XL2 +H 1 areas 2 global symbols +M cvu_get_sprite_x +S .__.ABS. Def0000 +A _CODE size 19 flags 0 addr 0 +S _cvu_get_sprite_x Def0000 +T 00 00 +R 00 00 00 00 +T 00 00 E1 FD E1 FD E5 E5 26 00 FD 6E 01 FD CB 03 +R 00 00 00 00 +T 0E 00 7E C8 7D C6 E0 6F 7C CE FF 67 C9 +R 00 00 00 00 + + + + + + +cvu_set_sprite_y + +XL2 +H 1 areas 2 global symbols +M cvu_set_sprite_y +S .__.ABS. Def0000 +A _CODE size 23 flags 0 addr 0 +S _cvu_set_sprite_y Def0000 +T 00 00 +R 00 00 00 00 +T 00 00 FD E1 E1 C1 C5 E5 3E CF 91 3E 00 98 F2 +R 00 00 00 00 +T 0D 00 13 00 06 00 0E CF +R 00 00 00 00 00 02 00 00 +T 13 00 +R 00 00 00 00 +T 13 00 79 D6 E0 78 DE FF F2 20 00 06 FF 0E E0 +R 00 00 00 00 00 09 00 00 +T 20 00 +R 00 00 00 00 +T 20 00 71 FD E9 +R 00 00 00 00 + + + + + + +cvu_get_sprite_y + +XL2 +H 1 areas 2 global symbols +M cvu_get_sprite_y +S .__.ABS. Def0000 +A _CODE size 10 flags 0 addr 0 +S _cvu_get_sprite_y Def0000 +T 00 00 +R 00 00 00 00 +T 00 00 C1 E1 E5 C5 6E 26 00 7D D6 DF D8 01 01 FF +R 00 00 00 00 +T 0E 00 09 C9 +R 00 00 00 00 + + + + + + +cvu_set_sprite_xy + +XL2 +H 9 areas 4 global symbols +M cvu_set_sprite_xy +O -mz80 +S .__.ABS. Def0000 +S _cvu_set_sprite_x Ref0000 +S _cvu_set_sprite_y Ref0000 +A _CODE size 2B flags 0 addr 0 +S _cvu_set_sprite_xy Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 21 04 00 39 4E 23 46 C5 21 04 00 39 4E 23 +R 00 00 00 00 +T 0E 00 46 C5 CD 00 00 F1 F1 21 06 00 39 4E 23 46 +R 00 00 00 00 02 05 01 00 +T 1C 00 C5 21 04 00 39 4E 23 46 C5 CD 00 00 F1 F1 +R 00 00 00 00 02 0C 02 00 +T 2A 00 C9 +R 00 00 00 00 + + + + + + +cvu_get_sprite_color + +XL2 +H 9 areas 2 global symbols +M cvu_get_sprite_color +O -mz80 +S .__.ABS. Def0000 +A _CODE size C flags 0 addr 0 +S _cvu_get_sprite_color Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 C1 E1 E5 C5 23 23 23 7E E6 0F 6F C9 +R 00 00 00 00 + + + + + + +cvu_memtovmemcpy + +XL2 +H 9 areas 7 global symbols +M cvu_memtovmemcpy +O -mz80 +S _cv_set_write_vram_address Ref0000 +S _cv_memtovmemcpy_fast Ref0000 +S _cv_get_screen_active Ref0000 +S _cv_memtovmemcpy_slow Ref0000 +S .__.ABS. Def0000 +S _cv_get_screen_mode Ref0000 +A _CODE size 4B flags 0 addr 0 +S _cvu_memtovmemcpy Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 C1 E1 E5 C5 E5 CD 00 00 F1 CD 00 00 CB 45 +R 00 00 00 00 02 08 00 00 02 0C 02 00 +T 0E 00 28 25 CD 00 00 7D B7 28 08 CD 00 00 7D D6 +R 00 00 00 00 02 05 05 00 02 0C 05 00 +T 1C 00 02 20 16 +R 00 00 00 00 +T 1F 00 +R 00 00 00 00 +T 1F 00 21 06 00 39 4E 23 46 C5 21 06 00 39 4E 23 +R 00 00 00 00 +T 2D 00 46 C5 CD 00 00 F1 F1 C9 +R 00 00 00 00 02 05 03 00 +T 35 00 +R 00 00 00 00 +T 35 00 21 06 00 39 4E 23 46 C5 21 06 00 39 4E 23 +R 00 00 00 00 +T 43 00 46 C5 CD 00 00 F1 F1 C9 +R 00 00 00 00 02 05 01 00 + + + + + + +cvu_vmemtomemcpy + +XL2 +H 9 areas 7 global symbols +M cvu_vmemtomemcpy +O -mz80 +S _cv_vmemtomemcpy_fast Ref0000 +S _cv_get_screen_active Ref0000 +S _cv_vmemtomemcpy_slow Ref0000 +S .__.ABS. Def0000 +S _cv_set_read_vram_address Ref0000 +S _cv_get_screen_mode Ref0000 +A _CODE size 4E flags 0 addr 0 +S _cvu_vmemtomemcpy Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 21 04 00 39 4E 23 46 C5 CD 00 00 F1 CD +R 00 00 00 00 02 0B 04 00 +T 0D 00 00 00 CB 45 28 25 CD 00 00 7D B7 28 08 CD +R 00 00 00 00 02 02 01 00 02 09 05 00 +T 1B 00 00 00 7D D6 02 20 16 +R 00 00 00 00 02 02 05 00 +T 22 00 +R 00 00 00 00 +T 22 00 21 06 00 39 4E 23 46 C5 21 04 00 39 4E 23 +R 00 00 00 00 +T 30 00 46 C5 CD 00 00 F1 F1 C9 +R 00 00 00 00 02 05 02 00 +T 38 00 +R 00 00 00 00 +T 38 00 21 06 00 39 4E 23 46 C5 21 04 00 39 4E 23 +R 00 00 00 00 +T 46 00 46 C5 CD 00 00 F1 F1 C9 +R 00 00 00 00 02 05 00 00 + + + + + + +cvu_vmemset + +XL2 +H 9 areas 7 global symbols +M cvu_vmemset +O -mz80 +S _cv_set_write_vram_address Ref0000 +S _cv_get_screen_active Ref0000 +S .__.ABS. Def0000 +S _cv_vmemset_fast Ref0000 +S _cv_get_screen_mode Ref0000 +S _cv_vmemset_slow Ref0000 +A _CODE size 4B flags 0 addr 0 +S _cvu_vmemset Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 C1 E1 E5 C5 E5 CD 00 00 F1 CD 00 00 CB 45 +R 00 00 00 00 02 08 00 00 02 0C 01 00 +T 0E 00 28 25 CD 00 00 7D B7 28 08 CD 00 00 7D D6 +R 00 00 00 00 02 05 04 00 02 0C 04 00 +T 1C 00 02 20 16 +R 00 00 00 00 +T 1F 00 +R 00 00 00 00 +T 1F 00 21 06 00 39 4E 23 46 C5 21 06 00 39 4E 23 +R 00 00 00 00 +T 2D 00 46 C5 CD 00 00 F1 F1 C9 +R 00 00 00 00 02 05 05 00 +T 35 00 +R 00 00 00 00 +T 35 00 21 06 00 39 4E 23 46 C5 21 06 00 39 4E 23 +R 00 00 00 00 +T 43 00 46 C5 CD 00 00 F1 F1 C9 +R 00 00 00 00 02 05 03 00 + + + + + + +cvu_voutb + +XL2 +H 9 areas 3 global symbols +M cvu_voutb +O -mz80 +S _cv_set_write_vram_address Ref0000 +S .__.ABS. Def0000 +A _CODE size 14 flags 0 addr 0 +S _cvu_voutb Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 21 03 00 39 4E 23 46 C5 CD 00 00 F1 21 +R 00 00 00 00 02 0B 00 00 +T 0D 00 02 00 39 7E D3 BE C9 +R 00 00 00 00 + + + + + + +cvu_vinb + +XL2 +H 9 areas 3 global symbols +M cvu_vinb +O -mz80 +S .__.ABS. Def0000 +S _cv_set_read_vram_address Ref0000 +A _CODE size D flags 0 addr 0 +S _cvu_vinb Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 C1 E1 E5 C5 E5 CD 00 00 F1 DB BE 6F C9 +R 00 00 00 00 02 08 01 00 + + + + + + +cvu_play_music + +XL2 +H 9 areas 6 global symbols +M cvu_play_music +O -mz80 +S _cv_set_frequency Ref0000 +S .__.ABS. Def0000 +S _cv_get_vint_frequency Ref0000 +S _cv_set_attenuation Ref0000 +S ___sdcc_enter_ix Ref0000 +A _CODE size 359 flags 0 addr 0 +S _cvu_play_music Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 CD 00 00 21 EF FF 39 F9 DD 7E 04 DD 77 F6 +R 00 00 00 00 02 03 04 00 +T 0E 00 DD 7E 05 DD 77 F7 DD 7E F6 C6 08 DD 77 FA +R 00 00 00 00 +T 1C 00 DD 7E F7 CE 00 DD 77 FB DD 6E FA DD 66 FB +R 00 00 00 00 +T 2A 00 7E DD 77 FE 23 7E DD 77 FF DD 7E F6 C6 05 +R 00 00 00 00 +T 38 00 DD 77 F8 DD 7E F7 CE 00 DD 77 F9 DD 6E F8 +R 00 00 00 00 +T 46 00 DD 66 F9 7E DD 77 F5 DD 77 FC DD 36 FD 00 +R 00 00 00 00 +T 54 00 DD 7E FE DD 96 FC DD 7E FF DD 9E FD 38 1B +R 00 00 00 00 +T 62 00 DD 6E F5 26 00 DD 7E FE 95 57 DD 7E FF 9C +R 00 00 00 00 +T 70 00 5F DD 6E FA DD 66 FB 72 23 73 C3 52 03 +R 00 00 00 00 00 0D 00 00 +T 7D 00 +R 00 00 00 00 +T 7D 00 DD 7E F6 C6 0A DD 77 FE DD 7E F7 CE 00 DD +R 00 00 00 00 +T 8B 00 77 FF DD 6E FE DD 66 FF 5E 23 46 DD 6E F6 +R 00 00 00 00 +T 99 00 DD 66 F7 56 7B DD 96 FC 78 DD 9E FD 38 2D +R 00 00 00 00 +T A7 00 AF F5 33 D5 33 CD 00 00 F1 DD 6E FE DD 66 +R 00 00 00 00 02 08 03 00 +T B5 00 FF 4E 23 46 DD 6E F8 DD 66 F9 6E 26 00 79 +R 00 00 00 00 +T C3 00 95 57 78 9C 5F DD 6E FE DD 66 FF 72 23 73 +R 00 00 00 00 +T D1 00 C3 52 03 +R 00 00 00 00 00 03 00 00 +T D4 00 +R 00 00 00 00 +T D4 00 DD 7E F6 C6 06 DD 77 FC DD 7E F7 CE 00 DD +R 00 00 00 00 +T E2 00 77 FD DD 6E FC DD 66 FD 4E 23 46 0A DD 77 +R 00 00 00 00 +T F0 00 F3 03 0A DD 77 F4 AF F5 33 D5 33 CD 00 00 +R 00 00 00 00 02 0E 03 00 +T FE 00 F1 DD 7E F3 3C 20 0A DD 7E F4 3C 20 04 6F +R 00 00 00 00 +T 0C 01 C3 54 03 +R 00 00 00 00 00 03 00 00 +T 0F 01 +R 00 00 00 00 +T 0F 01 DD 6E FA DD 66 FB 5E 23 56 DD 6E FE DD 66 +R 00 00 00 00 +T 1D 01 FF 7E 23 66 6F 19 4D 44 DD 66 F3 DD 6E F4 +R 00 00 00 00 +T 2B 01 3E 04 +R 00 00 00 00 +T 2D 01 +R 00 00 00 00 +T 2D 01 CB 3D CB 1C 3D 20 F9 7C E6 0F 67 2E 00 7C +R 00 00 00 00 +T 3B 01 B7 20 02 26 10 +R 00 00 00 00 +T 40 01 +R 00 00 00 00 +T 40 01 E5 C5 CD 00 00 5D C1 E1 C5 2E 00 55 06 08 +R 00 00 00 00 02 05 02 00 +T 4E 01 +R 00 00 00 00 +T 4E 01 29 30 01 19 +R 00 00 00 00 +T 52 01 +R 00 00 00 00 +T 52 01 10 FA C1 EB DD 6E FA DD 66 FB 73 23 72 DD +R 00 00 00 00 +T 60 01 6E FA DD 66 FB 7E 23 66 6F 09 EB DD 6E FA +R 00 00 00 00 +T 6E 01 DD 66 FB 73 23 72 DD 6E F8 DD 66 F9 6E 26 +R 00 00 00 00 +T 7C 01 00 7B 95 5F 7A 9C 57 DD 6E FA DD 66 FB 73 +R 00 00 00 00 +T 8A 01 23 72 DD 66 F3 DD 6E F4 CB 3D CB 1C CB 3D +R 00 00 00 00 +T 98 01 CB 1C 7C E6 03 DD 77 F2 3E 02 DD 96 F2 DA +R 00 00 00 00 +T A6 01 2D 02 DD 5E F2 16 00 21 B4 01 19 19 19 E9 +R 00 00 00 00 00 02 00 00 00 0A 00 00 +T B4 01 +R 00 00 00 00 +T B4 01 C3 5F 02 C3 C0 01 C3 FD 01 C3 +R 00 00 00 00 00 03 00 00 00 06 00 00 00 09 00 00 +T BE 01 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18 01 +R 00 00 00 00 +T 71 02 +R 00 00 00 00 +T 71 02 AF +R 00 00 00 00 +T 72 02 +R 00 00 00 00 +T 72 02 4F DD 71 F5 CB 41 C2 10 03 DD 6E F6 DD 66 +R 00 00 00 00 00 09 00 00 +T 80 02 F7 23 23 23 5E 23 56 DD 6E F1 26 00 29 19 +R 00 00 00 00 +T 8E 02 7E DD 77 EF 23 7E DD 77 F0 DD 7E F4 07 07 +R 00 00 00 00 +T 9C 02 07 07 E6 0F DD 77 F2 47 F5 DD 7E EF DD 77 +R 00 00 00 00 +T AA 02 F8 DD 7E F0 DD 77 F9 F1 04 18 08 +R 00 00 00 00 +T B5 02 +R 00 00 00 00 +T B5 02 DD CB F9 3E DD CB F8 1E +R 00 00 00 00 +T BD 02 +R 00 00 00 00 +T BD 02 10 F6 3E E0 DD BE F8 3E 7F DD 9E F9 30 30 +R 00 00 00 00 +T CB 02 DD 7E F2 DD 77 FE DD 36 FF 00 DD 34 FE 20 +R 00 00 00 00 +T D9 02 03 DD 34 FF +R 00 00 00 00 +T DD 02 +R 00 00 00 00 +T DD 02 DD 46 FE F5 DD 7E EF DD 77 F8 DD 7E F0 DD +R 00 00 00 00 +T EB 02 77 F9 F1 04 18 08 +R 00 00 00 00 +T F1 02 +R 00 00 00 00 +T F1 02 DD CB F9 3E DD CB F8 1E +R 00 00 00 00 +T F9 02 +R 00 00 00 00 +T F9 02 10 F6 +R 00 00 00 00 +T FB 02 +R 00 00 00 00 +T FB 02 DD 6E F6 DD 66 F7 66 DD 4E F8 DD 46 F9 C5 +R 00 00 00 00 +T 09 03 E5 33 CD 00 00 F1 33 +R 00 00 00 00 02 05 00 00 +T 10 03 +R 00 00 00 00 +T 10 03 DD CB F5 46 28 04 16 00 18 14 +R 00 00 00 00 +T 1A 03 +R 00 00 00 00 +T 1A 03 DD 6E F6 DD 66 F7 23 5E 23 66 DD 7E F3 E6 +R 00 00 00 00 +T 28 03 03 6F 16 00 19 56 +R 00 00 00 00 +T 2E 03 +R 00 00 00 00 +T 2E 03 DD 6E F6 DD 66 F7 46 D5 33 C5 33 CD 00 00 +R 00 00 00 00 02 0E 03 00 +T 3C 03 F1 DD 6E FC DD 66 FD 5E 23 56 13 13 42 DD +R 00 00 00 00 +T 4A 03 6E FC DD 66 FD 73 23 70 +R 00 00 00 00 +T 52 03 +R 00 00 00 00 +T 52 03 2E 01 +R 00 00 00 00 +T 54 03 +R 00 00 00 00 +T 54 03 DD F9 DD E1 C9 +R 00 00 00 00 + + + + + + +cvu_init_music + +XL2 +H 9 areas 6 global symbols +M cvu_init_music +O -mz80 +S _CVU_TUNING_ISO16_EQUAL Ref0000 +S .__.ABS. Def0000 +S ___sdcc_enter_ix Ref0000 +A _CODE size 48 flags 0 addr 0 +S _cvu_init_music Def0000 +S _CVU_EMPTY_MUSIC Def0046 +S _CVU_VOLUME_DEFAULT Def0042 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 CD 00 00 DD 5E 04 DD 56 05 AF 12 6B 62 23 +R 00 00 00 00 02 03 02 00 +T 0E 00 01 42 00 71 23 70 6B 62 23 23 23 01 00 00 +R 00 00 00 00 00 03 00 00 02 0E 00 00 +T 1C 00 71 23 70 21 05 00 19 36 0A 21 08 00 19 AF +R 00 00 00 00 +T 2A 00 77 23 77 21 0A 00 19 AF 77 23 77 21 06 00 +R 00 00 00 00 +T 38 00 19 11 46 00 73 23 72 DD E1 C9 +R 00 00 00 00 00 04 00 00 +T 42 00 +R 00 00 00 00 +T 42 00 14 10 0C 08 +R 00 00 00 00 +T 46 00 +R 00 00 00 00 +T 46 00 FF FF +R 00 00 00 00 + + + + + + +cvu_tuning_iso16_equal + +XL2 +H 9 areas 2 global symbols +M cvu_tuning_iso16_equal +O -mz80 +S .__.ABS. Def0000 +A _CODE size 1E flags 0 addr 0 +S _CVU_TUNING_ISO16_EQUAL Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 BF D5 C0 C9 6D BE BD B3 A7 A9 21 A0 24 97 +R 00 00 00 00 +T 0E 00 A9 8E A7 86 18 7F F6 77 3B 71 00 00 00 00 +R 00 00 00 00 +T 1C 00 00 00 +R 00 00 00 00 + + + + + + +cvu_tuning_scientific_equal + +XL2 +H 9 areas 2 global symbols +M cvu_tuning_scientific_equal +O -mz80 +S .__.ABS. Def0000 +A _CODE size 1E flags 0 addr 0 +S _CVU_TUNING_SCIENTIFIC_EQUAL Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 72 DA 2F CE 9D C2 B1 B7 61 AD A6 A3 77 9A +R 00 00 00 00 +T 0E 00 CB 91 9D 89 E3 81 99 7A B8 73 00 00 00 00 +R 00 00 00 00 +T 1C 00 00 00 +R 00 00 00 00 + + + + + + +cvu_init_huffman + +XL2 +H 9 areas 3 global symbols +M cvu_init_huffman +O -mz80 +S .__.ABS. Def0000 +S ___sdcc_enter_ix Ref0000 +A _CODE size 4A flags 0 addr 0 +S _cvu_init_huffman Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 CD 00 00 DD 5E 04 DD 56 05 6B 62 DD 7E 06 +R 00 00 00 00 02 03 01 00 +T 0E 00 77 23 DD 7E 07 77 6B 62 23 23 DD 7E 08 77 +R 00 00 00 00 +T 1C 00 23 DD 7E 09 77 21 04 00 19 DD 7E 0A 77 21 +R 00 00 00 00 +T 2A 00 05 00 19 DD 7E 0B 77 21 06 00 19 DD 7E 0C +R 00 00 00 00 +T 38 00 77 21 07 00 19 DD 7E 0D 77 21 08 00 19 36 +R 00 00 00 00 +T 46 00 08 DD E1 C9 +R 00 00 00 00 + + + + + + +cvu_init_rle + +XL2 +H 9 areas 2 global symbols +M cvu_init_rle +O -mz80 +S .__.ABS. Def0000 +A _CODE size 2A flags 0 addr 0 +S _cvu_init_rle Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 C1 D1 D5 C5 6B 62 FD 21 04 00 FD 39 FD 7E +R 00 00 00 00 +T 0E 00 00 77 23 FD 7E 01 77 6B 62 23 23 FD 21 +R 00 00 00 00 +T 1B 00 06 00 FD 39 FD 7E 00 77 EB 23 23 23 36 00 +R 00 00 00 00 +T 29 00 C9 +R 00 00 00 00 + + + + + + +cvu_get_rle + +XL2 +H 1 areas 2 global symbols +M cvu_get_rle +S .__.ABS. Def0000 +A _CODE size 4C flags 0 addr 0 +S _cvu_get_rle Def0000 +T 00 00 +R 00 00 00 00 +T 00 00 E1 FD E1 FD E5 E5 FD 7E 03 B7 C2 45 00 FD +R 00 00 00 00 00 0D 00 00 +T 0E 00 E5 21 1A 00 E5 FD 6E 00 FD 66 01 E9 +R 00 00 00 00 00 04 00 00 +T 1A 00 +R 00 00 00 00 +T 1A 00 FD E1 FD 7E 02 BD C0 FD E5 21 2E 00 E5 FD +R 00 00 00 00 00 0C 00 00 +T 28 00 6E 00 FD 66 01 E9 +R 00 00 00 00 +T 2E 00 +R 00 00 00 00 +T 2E 00 FD E1 FD 75 03 FD E5 21 40 00 E5 FD 6E 00 +R 00 00 00 00 00 0A 00 00 +T 3C 00 FD 66 01 E9 +R 00 00 00 00 +T 40 00 +R 00 00 00 00 +T 40 00 FD E1 FD 75 04 +R 00 00 00 00 +T 45 00 +R 00 00 00 00 +T 45 00 FD 35 03 FD 6E 04 C9 +R 00 00 00 00 + + + + + + +cvu_init_lzk + +XL2 +H 9 areas 2 global symbols +M cvu_init_lzk +O -mz80 +S .__.ABS. Def0000 +A _CODE size 3C flags 0 addr 0 +S _cvu_init_lzk Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 C1 D1 D5 C5 6B 62 FD 21 04 00 FD 39 FD 7E +R 00 00 00 00 +T 0E 00 00 77 23 FD 7E 01 77 6B 62 23 23 FD 21 +R 00 00 00 00 +T 1B 00 06 00 FD 39 FD 7E 00 77 6B 62 23 23 23 36 +R 00 00 00 00 +T 29 00 00 21 05 00 19 36 00 21 06 00 19 06 40 +R 00 00 00 00 +T 36 00 +R 00 00 00 00 +T 36 00 36 00 23 10 FB C9 +R 00 00 00 00 + + + + + + +cvu_get_lzk + +XL2 +H 9 areas 4 global symbols +M cvu_get_lzk +O -mz80 +S .__.ABS. Def0000 +S ___sdcc_call_hl Ref0000 +S ___sdcc_enter_ix Ref0000 +A _CODE size 137 flags 0 addr 0 +S _cvu_get_lzk Def0068 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 CD 00 00 DD 5E 04 DD 56 05 FD 21 06 00 FD +R 00 00 00 00 02 03 02 00 +T 0E 00 19 21 05 00 19 56 14 72 4A 06 00 FD 09 DD +R 00 00 00 00 +T 1C 00 7E 06 FD 77 00 7A E6 3F 77 DD E1 C9 +R 00 00 00 00 +T 28 00 +R 00 00 00 00 +T 28 00 CD 00 00 3B DD 5E 04 DD 56 05 FD 21 05 00 +R 00 00 00 00 02 03 02 00 +T 36 00 FD 19 FD 66 00 4C 0C FD 71 00 7C C6 40 DD +R 00 00 00 00 +T 44 00 77 FF 6B 62 23 23 23 23 DD 7E FF 96 6F 79 +R 00 00 00 00 +T 52 00 E6 3F FD 77 00 7D E6 3F 47 21 06 00 19 58 +R 00 00 00 00 +T 60 00 16 00 19 6E 33 DD E1 C9 +R 00 00 00 00 +T 68 00 +R 00 00 00 00 +T 68 00 CD 00 00 F5 F5 DD 4E 04 DD 46 05 21 03 00 +R 00 00 00 00 02 03 02 00 +T 76 00 09 E3 E1 E5 7E B7 C2 26 01 69 60 7E 23 66 +R 00 00 00 00 00 09 00 00 +T 84 00 6F C5 CD 00 00 C1 55 21 02 00 09 DD 75 FE +R 00 00 00 00 02 05 01 00 +T 92 00 DD 74 FF DD 6E FE DD 66 FF 5E 7A 93 28 0E +R 00 00 00 00 +T A0 00 D5 D5 33 C5 CD 00 00 F1 33 D1 6A C3 32 01 +R 00 00 00 00 00 07 00 00 00 0E 00 00 +T AE 00 +R 00 00 00 00 +T AE 00 69 60 7E 23 66 6F C5 CD 00 00 C1 55 7A B7 +R 00 00 00 00 02 0A 01 00 +T BC 00 20 18 DD 6E FE DD 66 FF 66 E5 33 C5 CD +R 00 00 00 00 +T C9 00 00 00 F1 33 DD 6E FE DD 66 FF 6E 18 5C +R 00 00 00 00 00 02 00 00 +T D6 00 +R 00 00 00 00 +T D6 00 FD 21 04 00 FD 09 FD 36 00 00 7A E6 0F 20 +R 00 00 00 00 +T E4 00 24 7A 07 07 07 07 E6 0F E6 03 E1 E5 77 7A +R 00 00 00 00 +T F2 00 07 07 E6 03 FD 77 00 69 60 7E 23 66 6F C5 +R 00 00 00 00 +T 00 01 FD E5 CD 00 00 FD E1 C1 55 +R 00 00 00 00 02 05 01 00 +T 09 01 +R 00 00 00 00 +T 09 01 E1 E5 66 7A E6 0F 84 E1 E5 77 3C E1 E5 77 +R 00 00 00 00 +T 17 01 FD 6E 00 7A 07 07 07 07 E6 0F 5F 19 FD 75 +R 00 00 00 00 +T 25 01 00 +R 00 00 00 00 +T 26 01 +R 00 00 00 00 +T 26 01 E1 E5 56 15 E1 E5 72 C5 CD 28 00 F1 +R 00 00 00 00 00 0B 00 00 +T 32 01 +R 00 00 00 00 +T 32 01 DD F9 DD E1 C9 +R 00 00 00 00 + + + + + + +cvu_get_huffman + +XL2 +H 1 areas 2 global symbols +M cvu_get_huffman +S .__.ABS. Def0000 +A _CODE size 59 flags 0 addr 0 +S _cvu_get_huffman Def0000 +T 00 00 +R 00 00 00 00 +T 00 00 E1 FD E1 FD E5 E5 06 00 FD 4E 04 FD 5E 08 +R 00 00 00 00 +T 0E 00 FD 56 09 +R 00 00 00 00 +T 11 00 +R 00 00 00 00 +T 11 00 CB 3A 3E 08 BB C2 2D 00 FD E5 C5 21 27 00 +R 00 00 00 00 00 08 00 00 00 0E 00 00 +T 1F 00 E5 FD 6E 00 FD 66 01 E9 +R 00 00 00 00 +T 27 00 +R 00 00 00 00 +T 27 00 C1 FD E1 55 1E 00 +R 00 00 00 00 +T 2D 00 +R 00 00 00 00 +T 2D 00 1C FD 6E 02 FD 66 03 09 09 3E 01 A2 79 20 +R 00 00 00 00 +T 3B 00 0E +R 00 00 00 00 +T 3C 00 +R 00 00 00 00 +T 3C 00 FD BE 05 38 05 FD BE 07 38 0B +R 00 00 00 00 +T 46 00 +R 00 00 00 00 +T 46 00 4E C3 11 00 +R 00 00 00 00 00 04 00 00 +T 4A 00 +R 00 00 00 00 +T 4A 00 23 FD BE 06 DA 46 00 +R 00 00 00 00 00 07 00 00 +T 51 00 +R 00 00 00 00 +T 51 00 FD 73 08 FD 72 09 6E C9 +R 00 00 00 00 + + + + + + +cvu_compression + +XL2 +H 9 areas C global symbols +M cvu_compression +O -mz80 +S _cvu_init_huffman Ref0000 +S _cv_set_write_vram_address Ref0000 +S _cvu_get_huffman Ref0000 +S .__.ABS. Def0000 +S _cvu_init_rle Ref0000 +S __read_from_array Ref0000 +S _cvu_get_rle Ref0000 +S ___sdcc_enter_ix Ref0000 +A _CODE size AC flags 0 addr 0 +S _cvu_memtovmemcpy_compression Def0074 +S _cvu_init_compression Def0009 +S _cvu_get_compression Def005B +A _DATA size 2 flags 0 addr 0 +S __common_state Def0000 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 01 00 +T 00 00 +R 00 00 01 00 +T 00 00 +R 00 00 00 00 +T 00 00 2A 00 00 E5 CD 00 00 F1 C9 +R 00 00 00 00 00 03 01 00 02 07 02 00 +T 09 00 +R 00 00 00 00 +T 09 00 CD 00 00 DD 5E 06 DD 56 07 21 0F 00 19 DD +R 00 00 00 00 02 03 07 00 +T 17 00 7E 04 77 23 DD 7E 05 77 D5 DD 66 0D DD 6E +R 00 00 00 00 +T 25 00 0C E5 DD 66 0B DD 6E 0A E5 DD 6E 08 DD 66 +R 00 00 00 00 +T 33 00 09 E5 21 00 00 E5 D5 CD 00 00 21 0A 00 39 +R 00 00 00 00 02 05 05 00 02 0A 00 00 +T 41 00 F9 D1 21 0A 00 19 EB DD 7E 0E F5 33 21 +R 00 00 00 00 +T 4E 00 00 00 E5 D5 CD 00 00 F1 F1 33 DD E1 C9 +R 00 00 00 00 00 02 00 00 02 07 04 00 +T 5B 00 +R 00 00 00 00 +T 5B 00 11 00 00 21 02 00 39 01 02 00 ED B0 2A +R 00 00 00 00 00 03 01 00 +T 68 00 00 00 01 0A 00 09 E5 CD 00 00 F1 C9 +R 00 00 00 00 00 02 01 00 02 0A 06 00 +T 74 00 +R 00 00 00 00 +T 74 00 CD 00 00 DD 6E 06 DD 66 07 22 00 00 DD 6E +R 00 00 00 00 02 03 07 00 00 0C 01 00 +T 82 00 04 DD 66 05 E5 CD 00 00 F1 DD 5E 08 DD 56 +R 00 00 00 00 02 08 01 00 +T 90 00 09 +R 00 00 00 00 +T 91 00 +R 00 00 00 00 +T 91 00 7A B3 28 14 2A 00 00 01 0A 00 09 D5 E5 CD +R 00 00 00 00 00 07 01 00 +T 9F 00 00 00 F1 7D D1 D3 BE 1B 18 E8 +R 00 00 00 00 02 02 06 00 +T A9 00 +R 00 00 00 00 +T A9 00 DD E1 C9 +R 00 00 00 00 + + + + + + +cvu_memcpy_compression + +XL2 +H 9 areas 5 global symbols +M cvu_memcpy_compression +O -mz80 +S __common_state Ref0000 +S .__.ABS. Def0000 +S _cvu_get_rle Ref0000 +S ___sdcc_enter_ix Ref0000 +A _CODE size 49 flags 0 addr 0 +S _cvu_memcpy_compression Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 CD 00 00 F5 DD 6E 06 DD 66 07 22 00 00 21 +R 00 00 00 00 02 03 03 00 02 0D 00 00 +T 0E 00 00 00 E3 DD 5E 08 DD 56 09 +R 00 00 00 00 +T 17 00 +R 00 00 00 00 +T 17 00 7A B3 28 2A DD 6E 04 DD 66 05 C1 C5 DD 34 +R 00 00 00 00 +T 25 00 FE 20 03 DD 34 FF +R 00 00 00 00 +T 2B 00 +R 00 00 00 00 +T 2B 00 09 4D 44 2A 00 00 D5 11 0A 00 19 D1 C5 D5 +R 00 00 00 00 02 06 00 00 +T 39 00 E5 CD 00 00 F1 7D D1 C1 02 1B 18 D2 +R 00 00 00 00 02 04 02 00 +T 45 00 +R 00 00 00 00 +T 45 00 F1 DD E1 C9 +R 00 00 00 00 + + + + + + +_read_from_array + +XL2 +H 1 areas 3 global symbols +M _read_from_array +S __common_state Ref0000 +S .__.ABS. Def0000 +A _CODE size 11 flags 0 addr 0 +S __read_from_array Def0000 +T 00 00 +R 00 00 00 00 +T 00 00 2A 00 00 01 0F 00 09 5E 23 56 1A 13 72 2B +R 00 00 00 00 02 03 00 00 +T 0E 00 73 6F C9 +R 00 00 00 00 + + + + + + +cvu_fmul2 + +XL2 +H 9 areas 5 global symbols +M cvu_fmul2 +O -mz80 +S .__.ABS. Def0000 +S __u_16_16_mul Ref0000 +S ___sdcc_enter_ix Ref0000 +A _CODE size 7B flags 0 addr 0 +S _cvu_fmul2 Def0056 +S _cvu_s_16_16_mul Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 CD 00 00 3B DD 36 FF 00 DD 5E 04 DD 56 05 +R 00 00 00 00 02 03 02 00 +T 0E 00 DD 4E 06 DD 46 07 CB 7A 28 0B DD 36 FF 01 +R 00 00 00 00 +T 1C 00 AF 93 5F 3E 00 9A 57 +R 00 00 00 00 +T 23 00 +R 00 00 00 00 +T 23 00 CB 78 28 0F DD 7E FF EE 01 DD 77 FF AF 91 +R 00 00 00 00 +T 31 00 4F 3E 00 98 47 +R 00 00 00 00 +T 36 00 +R 00 00 00 00 +T 36 00 C5 D5 CD 00 00 F1 F1 DD CB FF 46 28 0F AF +R 00 00 00 00 02 05 01 00 +T 44 00 95 6F 3E 00 9C 67 3E 00 9B 5F 3E 00 9A 57 +R 00 00 00 00 +T 52 00 +R 00 00 00 00 +T 52 00 33 DD E1 C9 +R 00 00 00 00 +T 56 00 +R 00 00 00 00 +T 56 00 CD 00 00 DD 6E 06 DD 66 07 E5 DD 6E 04 DD +R 00 00 00 00 02 03 02 00 +T 64 00 66 05 E5 CD 00 00 F1 F1 06 06 +R 00 00 00 00 00 06 00 00 +T 6E 00 +R 00 00 00 00 +T 6E 00 CB 2A CB 1B CB 1C CB 1D 10 F6 DD E1 C9 +R 00 00 00 00 + + + + + + +cvu_fdiv2 + +XL2 +H 9 areas 4 global symbols +M cvu_fdiv2 +O -mz80 +S _abs Ref0000 +S .__.ABS. Def0000 +S __divsint Ref0000 +A _CODE size 3F flags 0 addr 0 +S _cvu_fdiv2 Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 C1 D1 D5 C5 06 06 +R 00 00 00 00 +T 06 00 +R 00 00 00 00 +T 06 00 78 B7 28 1E C5 D5 D5 CD 00 00 F1 D1 C1 3E +R 00 00 00 00 02 0A 00 00 +T 14 00 FF BD 3E 3F 9C E2 1E 00 EE 80 +R 00 00 00 00 00 08 00 00 +T 1E 00 +R 00 00 00 00 +T 1E 00 FA 28 00 CB 23 CB 12 05 18 DE +R 00 00 00 00 00 03 00 00 +T 28 00 +R 00 00 00 00 +T 28 00 C5 21 06 00 39 4E 23 46 C5 D5 CD 00 00 F1 +R 00 00 00 00 02 0D 02 00 +T 36 00 F1 C1 04 18 01 +R 00 00 00 00 +T 3B 00 +R 00 00 00 00 +T 3B 00 29 +R 00 00 00 00 +T 3C 00 +R 00 00 00 00 +T 3C 00 10 FD C9 +R 00 00 00 00 + + + + + + +cvu_fsincos + +XL2 +H 9 areas 5 global symbols +M cvu_fsincos +O -mz80 +S .__.ABS. Def0000 +S ___sdcc_enter_ix Ref0000 +A _CODE size E9 flags 0 addr 0 +S _cvu_fsintable Def006C +S _cvu_fcos Def00D1 +S _cvu_fsin Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 CD 00 00 DD CB 05 7E 28 13 AF DD 96 04 DD +R 00 00 00 00 02 03 01 00 +T 0E 00 77 04 3E 00 DD 9E 05 DD 77 05 06 01 18 02 +R 00 00 00 00 +T 1C 00 +R 00 00 00 00 +T 1C 00 06 00 +R 00 00 00 00 +T 1E 00 +R 00 00 00 00 +T 1E 00 DD 5E 04 DD 56 05 +R 00 00 00 00 +T 24 00 +R 00 00 00 00 +T 24 00 7B D6 C9 7A 17 3F 1F DE 80 38 0E 7B C6 37 +R 00 00 00 00 +T 32 00 5F 7A CE FF 57 78 EE 01 47 18 E7 +R 00 00 00 00 +T 3D 00 +R 00 00 00 00 +T 3D 00 7B D6 64 7A 17 3F 1F DE 80 30 09 21 6C 00 +R 00 00 00 00 00 0E 00 00 +T 4B 00 19 6E 26 00 18 0D +R 00 00 00 00 +T 51 00 +R 00 00 00 00 +T 51 00 21 6C 00 3E C8 93 5F 16 00 19 6E 26 00 +R 00 00 00 00 00 03 00 00 +T 5E 00 +R 00 00 00 00 +T 5E 00 CB 40 28 07 AF 95 6F 3E 00 9C 67 +R 00 00 00 00 +T 69 00 +R 00 00 00 00 +T 69 00 DD E1 C9 +R 00 00 00 00 +T 6C 00 +R 00 00 00 00 +T 6C 00 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D +R 00 00 00 00 +T 7A 00 0E 0F 10 11 12 13 14 15 16 17 17 18 19 1A +R 00 00 00 00 +T 88 00 1B 1C 1D 1E 1F 20 20 21 22 23 24 25 25 26 +R 00 00 00 00 +T 96 00 27 28 29 29 2A 2B 2C 2C 2D 2E 2E 2F 30 30 +R 00 00 00 00 +T A4 00 31 32 32 33 34 34 35 35 36 36 37 37 38 38 +R 00 00 00 00 +T B2 00 39 39 3A 3A 3B 3B 3B 3C 3C 3C 3D 3D 3D 3E +R 00 00 00 00 +T C0 00 3E 3E 3E 3F 3F 3F 3F 3F 3F 40 40 40 40 40 +R 00 00 00 00 +T CE 00 40 40 40 +R 00 00 00 00 +T D1 00 +R 00 00 00 00 +T D1 00 FD 21 02 00 FD 39 FD 7E 00 C6 64 5F FD 7E +R 00 00 00 00 +T DF 00 01 CE 00 57 D5 CD 00 00 F1 C9 +R 00 00 00 00 00 08 00 00 + + + + + + +cvu_fatan + +XL2 +H 9 areas 6 global symbols +M cvu_fatan +O -mz80 +S _abs Ref0000 +S .__.ABS. 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Def0000 +S ___sdcc_enter_ix Ref0000 +A _CODE size 24 flags 0 addr 0 +S _cvu_cabs Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 CD 00 00 DD 6E 04 DD 66 05 E5 5E 23 56 D5 +R 00 00 00 00 02 03 02 00 +T 0E 00 CD 00 00 F1 EB E1 23 23 4E 23 46 D5 C5 CD +R 00 00 00 00 02 03 00 00 +T 1C 00 00 00 F1 D1 19 DD E1 C9 +R 00 00 00 00 02 02 00 00 + + + + + + +cvu_c_from_polar + +XL2 +H 9 areas 6 global symbols +M cvu_c_from_polar +O -mz80 +S .__.ABS. Def0000 +S _cvu_cfmul Ref0000 +S ___sdcc_enter_ix Ref0000 +S _cvu_fcos Ref0000 +S _cvu_fsin Ref0000 +A _CODE size 52 flags 0 addr 0 +S _cvu_c_from_polar Def0000 +A _DATA size 0 flags 0 addr 0 +A _INITIALIZED size 0 flags 0 addr 0 +A _DABS size 0 flags 8 addr 0 +A _HOME size 0 flags 0 addr 0 +A _GSINIT size 0 flags 0 addr 0 +A _GSFINAL size 0 flags 0 addr 0 +A _INITIALIZER size 0 flags 0 addr 0 +A _CABS size 0 flags 8 addr 0 +T 00 00 +R 00 00 00 00 +T 00 00 CD 00 00 DD 5E 04 DD 56 05 D5 DD 6E 06 DD +R 00 00 00 00 02 03 02 00 +T 0E 00 66 07 E5 CD 00 00 F1 45 4C D1 6B 62 70 23 +R 00 00 00 00 02 06 03 00 +T 1C 00 71 6B 62 23 23 E5 D5 DD 4E 06 DD 46 07 C5 +R 00 00 00 00 +T 2A 00 CD 00 00 F1 45 4C D1 E1 70 23 71 DD 7E 08 +R 00 00 00 00 02 03 04 00 +T 38 00 D6 40 20 06 DD 7E 09 B7 28 0D +R 00 00 00 00 +T 42 00 +R 00 00 00 00 +T 42 00 DD 6E 08 DD 66 09 E5 D5 CD 00 00 F1 F1 +R 00 00 00 00 02 0B 01 00 +T 4F 00 +R 00 00 00 00 +T 4F 00 DD E1 C9 +R 00 00 00 00 + + + + + + + + +#ifndef CV_GRAPHICS_H +#define CV_GRAPHICS_H 1 + +#include +#include +#include + +/* + These are the functions for controlling the graphics chip. + While a function marked as not reentrant is called no other + such function from this file may be called at the same time. +*/ + +typedef uint16_t cv_vmemp; // 14-Bit Video memory address type + +/* + Activate / deactivate screen + + This function is not reentrant! +*/ +extern void cv_set_screen_active(bool status); + +/* + Get screen status +*/ +extern bool cv_get_screen_active(void); + +/* + Enable / disable external video source. + + This function is not reentrant! +*/ +extern void cv_set_external_video(bool status); + +/* + Get external video source enabled. +*/ +extern bool cv_get_external_video(void); + +// TMS99xxA screen modes +enum cv_screenmode { + CV_SCREENMODE_STANDARD = 0x00, // Standard screen modes + CV_SCREENMODE_TEXT = 0x10, + CV_SCREENMODE_MULTICOLOR = 0x08, + CV_SCREENMODE_BITMAP = 0x02, + CV_SCREENMODE_BITMAP_TEXT = 0x12, // Usefull undocumented screen modes + CV_SCREENMODE_BITMAP_MULTICOLOR = 0x0a, + CV_SCREENMODE_TEXT_MULTICOLOR = 0x18, // Useless undocumented screen modes + CV_SCREENMODE_BITMAP_TEXT_MULTICOLOR = 0x1a +}; + +/* + Set screen mode. + + This function is not reentrant! +*/ +extern void cv_set_screen_mode(enum cv_screenmode mode); + +/* + Get screen mode. +*/ +extern enum cv_screenmode cv_get_screen_mode(void); + +// TMS99xxA colors +enum cv_color { + CV_COLOR_TRANSPARENT = 0x0, + CV_COLOR_BLACK = 0x1, + CV_COLOR_GREEN = 0x2, + CV_COLOR_LIGHT_GREEN = 0x3, + CV_COLOR_BLUE = 0x4, + CV_COLOR_LIGHT_BLUE = 0x5, + CV_COLOR_DARK_RED = 0x6, + CV_COLOR_CYAN = 0x7, + CV_COLOR_RED = 0x8, + CV_COLOR_LIGHT_RED = 0x9, + CV_COLOR_YELLOW = 0xa, + CV_COLOR_LIGHT_YELLOW = 0xb, + CV_COLOR_DARK_GREEN = 0xc, + CV_COLOR_MAGENTA = 0xd, + CV_COLOR_GRAY = 0xe, + CV_COLOR_WHITE = 0xf +}; + +/* + Set colors. The foreground color is the text color in text mode, + in other modes it is unused. + The background color is used in all modes for the backdrop plane + (screen outside display area) and as the color that appears under + transparent characters. In text mode it is used for character + background. If the background color is the to cv_transparent, + the externeal video source is used as background image. +*/ +extern void cv_set_colors(enum cv_color foreground, enum cv_color background); + +/* + Set the location of the screen image table. + Must be a multiple of 0x400. Valid range: [0; 15360]. +*/ +extern void cv_set_image_table(cv_vmemp loc); + +/* + Set the location of the color table. Must be a multiple of 0x40. + Valid range: [0; 16320]. + When the screen mode ist CV_SCREENMODE_BITMAP, + CV_SCREENMODE_BITMAP_TEXT or CV_SCREENMODE_BITMAP_MULTICOLOR + this has a different meaning: The location of the character pattern table is + either 0 or 8192. The bits 4096 downto 128 are an and mask to the location. + This masking functionality is undocumented. To use only the documented + graphics chip functionality always set bits 4096 downto 128. +*/ +void cv_set_color_table(cv_vmemp loc); + +/* + Set the location of the character pattern table. Must be a multiple + of 0x800. Valid range: [0; 14336]. + When the screen mode ist CV_SCREENMODE_BITMAP, + CV_SCREENMODE_BITMAP_TEXT or CV_SCREENMODE_BITMAP_MULTICOLOR + this has a different meaning: The location of the character pattern table is + either 0 or 8192. If you add 4096 to the location the first third of the table + is used for the last third of the screen. If you add 2048 to the location the + first third of the table is used for the middle part of the screen. + Thus the bits 4096 and 2048 are and and mask to the highest bits of the + address. This masking functionality is undocumented. To use only the + documented graphics chip functionality always set bits 4096 and 2048. +*/ +// sdcc doesn't accept long function names. +extern void cv_set_character_pattern_t(cv_vmemp loc); + +/* + Set the location of the sprite pattern table. + Must be a multiple of 0x800. Valid range: [0; 14336]. +*/ +extern void cv_set_sprite_pattern_table(cv_vmemp loc); + +/* + Set the location of the sprite attribute table. + Must be a multiple of 0x80. Valid range: [0; 16256]. +*/ +extern void cv_set_sprite_attribute_table(cv_vmemp loc); + +/* + Set sprite size; When active, sprites are 16x16 pixels instead of 8x8. + + This function is not reentrant! +*/ +extern void cv_set_sprite_big(bool status); + +/* + Get sprite size. +*/ +extern bool cv_get_sprite_big(void); + +/* + Set sprite magnification. When active, all sprites are displayed twice as big. + + This function is not reentrant! +*/ +extern void cv_set_sprite_magnification(bool status); + +/* + Get sprite magnification. +*/ +extern bool cv_get_sprite_magnification(void); + +/* + Get sprite collission. +*/ +extern bool cv_get_sprite_collission(void); + +/* + Get invalid sprite. Returns true if there was an invalid sprite. + If sprite is not 0 it will point to the number of the invalid sprite. +*/ +extern bool cv_get_sprite_invalid(uint8_t *sprite); + +extern void cv_set_write_vram_address(cv_vmemp address); + +extern void cv_set_read_vram_address(cv_vmemp address); + +extern void cv_memtovmemcpy_slow(const void *src, size_t n); + +extern void cv_memtovmemcpy_fast(const void *src, size_t n); + +extern void cv_vmemtomemcpy_slow(void *dest, size_t n); + +extern void cv_vmemtomemcpy_fast(void *dest, size_t n); + +extern void cv_vmemset_slow(int c, size_t n); + +extern void cv_vmemset_fast(int c, size_t n); + +static volatile __sfr __at 0xbe cv_graphics_port; + +inline void cv_voutb(const uint8_t value) +{ + cv_graphics_port = value; +} + +inline uint8_t cv_vinb(void) +{ + return(cv_graphics_port); +} + +#endif + +#ifndef CV_SOUND_H +#define CV_SOUND_H 1 + +#include +#include + +enum cv_soundchannel { + CV_SOUNDCHANNEL_0 = 0x0, + CV_SOUNDCHANNEL_1 = 0x2, + CV_SOUNDCHANNEL_2 = 0x4, + CV_SOUNDCHANNEL_NOISE = 0x6 +}; + +enum cv_shift { + CV_NOISE_SHIFT_512 = 0, + CV_NOISE_SHIFT_1024 = 1, + CV_NOISE_SHIFT_2048 = 2, + CV_NOISE_SHIFT_CHAN2 = 3 +}; + +/* + Set attenuation for given sound channel in dezibel. Maximum attenuation is 28 db, + granularity is 2 db. +*/ +extern void cv_set_attenuation(enum cv_soundchannel channel, uint8_t dezibel); + +/* + Set frequency of a tone generator. The frequency is 3.579/frequency_divider Mhz. + This function is not reentrant. While it is called neither cv_set_attenuation() nor + cv_set_noise() may be called. n should be a multiple of 32. The valid range is [0, 32736]. +*/ + +extern void cv_set_frequency(enum cv_soundchannel channel, uint16_t frequency_divider); + +extern void cv_set_noise(bool white, enum cv_shift shift); + +#endif +#ifndef __CV_SUPPORT_H +#define __CV_SUPPORT_H 1 + +#include + +#include "cv_graphics.h" + +extern void cv_init(void); // Initialize Colecovision library. + +extern void cv_vdpout(const uint8_t reg, const uint8_t data); // Write data to VDP control register reg. + +extern void cv_enable_nmi(void); + +extern void cv_disable_nmi(void); + +#endif +#ifndef CV_INPUT_H +#define CV_INPUT_H 1 + +#include + +#define CV_FIRE_0 0x40 +#define CV_FIRE_1 0x80 +#define CV_FIRE_2 0x10 +#define CV_FIRE_3 0x20 +#define CV_LEFT 0x08 +#define CV_DOWN 0x04 +#define CV_RIGHT 0x02 +#define CV_UP 0x01 + +struct cv_controller_state +{ + uint8_t keypad; // Keypad: 0 - 9 as on keypad, * as 0xa, # as 0xb, 0xf for no key pressed or error. + uint8_t joystick;// Joystick: lowest 4 bit for joystick, higher 4 bit for fire buttons. +}; + +// Get keypad and joystick values. +void cv_get_controller_state(struct cv_controller_state *state, uint_fast8_t controller); + +#define CV_SPIN_ACTIVE 0x10 +#define CV_SPIN_RIGHT 0x20 + +// Set the handler for the spinner interrupt. +// This handler will be called when the wheel on the super action controller or the ball in the roller controller spin. +// The parameters passed to the handler correspond to the two super action controllers or +// the two axis in the roller controller. They can be anded with the above masks to test if they spinned, and which direction. +void cv_set_spint_handler(void (* handler)(uint_fast8_t, uint_fast8_t)); + +#endif + +// (c) 2013 Philipp Klaus Krause + +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. + +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. + +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +#ifndef CV_H +#define CV_H 1 + +#define CV_LIBVERSION_MAJOR 0 +#define CV_LIBVERSION_MINOR 23 +#define CV_LIBVERSION_STRING "0.23" + +#include "cv_input.h" +#include "cv_graphics.h" +#include "cv_sound.h" + +// Set the handler for the vertical retrace interrupt. +extern void cv_set_vint_handler(void (* handler)(void)); + +// Get the handler for the vertical retrace interrupt. +extern void *cv_get_vint_handler(void); + +// Get the vertical retrace frequency in Hz. 50 for PAL, 60 for NTSC. +unsigned char cv_get_vint_frequency(void); + +#endif + +#ifndef CVU_GRAPHICS_H +#define CVU_GRAPHICS_H 1 + +#include + +#include "cv_graphics.h" + +struct cvu_sprite +{ + uint8_t y; + uint8_t x; + uint8_t name; + uint8_t tag; +}; + +// Write sprite to display memory. Use the location of the sprite table as base. number should be in [0, 31]. +//extern void cvu_set_sprite(const cv_vmemp base, const unsigned int number, const struct cvu_sprite *sprite); +#define cvu_set_sprite(base, number, sprite) {cv_set_write_vram_address((base) + (number) * 0x4); cv_memtovmemcpy_slow((sprite), 4);} +/*inline void cvu_set_sprite(const cv_vmemp base, const unsigned int number, const struct cvu_sprite *sprite) +{ + cv_set_write_vram_address(base + number * 0x4); + cv_memtovmemcpy_slow(sprite, 4); +}*/ + +// Todo: is cvu_get_sprite needed? + +// Set the x coordinate of the sprite's upper left corner. x will be clamped to [-32, 255] +extern void cvu_set_sprite_x(struct cvu_sprite *sprite, int x); + +extern int cvu_get_sprite_x(const struct cvu_sprite *sprite); + +// Set the y coordinate of the sprite's upper left corner. y will be clamped to [-32, 207] +extern void cvu_set_sprite_y(struct cvu_sprite *sprite, int y); + +extern int cvu_get_sprite_y(const struct cvu_sprite *sprite); + +// Set them both at once. +extern void cvu_set_sprite_xy(struct cvu_sprite *sprite, int x, int y); + +// Set the sprite's color. +//extern void cvu_set_sprite_color(struct cvu_sprite *sprite, enum cv_color color); +#define cvu_set_sprite_color(sprite, color) (sprite)->tag = ((sprite)->tag & 0x80) | (color) +/*inline void cvu_set_sprite_color(struct cvu_sprite *sprite, enum cv_color color) +{ + sprite->tag = (sprite->tag & 0x80) | color; +}*/ + +extern enum cv_color cvu_get_sprite_color(struct cvu_sprite *sprite); + +/* + Copy n bytes of data from RAM at src to VRAM at dest. + + This function is not reentrant! + + The speed of this function depends on the active video mode + and if the screen is active. +*/ +extern void cvu_memtovmemcpy(cv_vmemp dest, const void * src, size_t n); + +/* + Copy n bytes of data from VRAM at src to RAM at dest. + + This function is not reentrant! + + The speed of this function depends on the active video mode + and if the screen is active. +*/ +extern void cvu_vmemtomemcpy(void *dest, cv_vmemp src, size_t n); + +/* + Set n bytes of VRAM at dest to c. + + This function is not reentrant! + + The speed of this function depends on the active video mode + and if the screen is active. +*/ +extern void cvu_vmemset(cv_vmemp dest, int c, size_t n); + +/* + Write an octet to graphics memory at dest. + + This function is not reentrant! +*/ +extern void cvu_voutb(const uint8_t value, const cv_vmemp dest); + +/* + Read an octet from graphics memory at src. + + This function is not reentrant! +*/ +extern uint8_t cvu_vinb(const cv_vmemp src); + +#endif +#ifndef CVU_INPUT_H +#define CVU_INPUT_H 1 + +#include + +#include "cv_input.h" + +// For the super action controllers this gives the spinner movement (total relative movement since last call, negative for left, positive for right) +// For the roller controller this gives the ball movement (total relative as above). +// Using this function will set a libvu-specific spint handler, so it is incompatible with using a custom spint handler. + +int_fast8_t cvu_get_spinner(uint_fast8_t controller); + +#endif + +#ifndef CVU_C_H +#define CVU_C_H 1 + +#include "cvu_f.h" + +// Complex fixed-point type +struct cvu_c +{ + cvu_f r; + cvu_f i; +}; + +// Addition +//extern void cadd(struct c *l, const struct c *r); +#define cvu_cadd(x, y) {(x)->r += (y)->r; (x)->i += (y)->i;} + +// Subtraction +//extern void csub(struct c *l, const struct c *r); +#define cvu_csub(x, y) {(x)->r -= (y)->r; (x)->i -= (y)->i;} + +// Multiplication +extern void cvu_cmul(struct cvu_c *l, const struct cvu_c *r); + +// Very inaccurate approximation +extern cvu_f cvu_cabs(const struct cvu_c *l); + +// Dot product: Returns l.r^2 + l.i^2 +extern cvu_f cvu_cdot(const struct cvu_c *l); + +// Multiplication by fixed-point number. +extern void cvu_cfmul(struct cvu_c *l, cvu_f r); + +// Convert from polar to coordinate representation +extern void cvu_c_from_polar(struct cvu_c *c, cvu_f phi, cvu_f d); + +#endif + +// These decompression routines are rather complicated to allow customization. +// If you only want to decompress some data into graphics memory, you can use +// the functions at the end of this file instead. + +#ifndef CVU_COMPRESSION_H +#define CVU_COMPRESSION_H 1 + +#include +#include "cvu_graphics.h" + +// Huffman decompression +#undef CVU_HUFFMAN_ITERATIVE +#undef CVU_HUFFMAN_RECURSIVE + +struct cvu_huffman_node // Changing this struct will affect asm implementation of cvu_get_huffman +{ + uint8_t left; // Position of left node in tree or character. + uint8_t right; // Position of right node in tree or character. +}; + +struct cvu_huffman_state // Changing this struct will affect asm implementation of cvu_get_huffman, _read_from_array +{ + uint8_t (*input)(void); + const struct cvu_huffman_node *nodes; // Array of nodes + uint8_t root; // Position of root node among nodes + uint8_t ls, bs, rs; + unsigned char bit; // Position of currently processed bit + uint8_t buffer; // Currently processed input byte +#ifdef CVU_HUFFMAN_RECURSIVE + uint8_t current; // Currently processed node +#endif +}; + +void cvu_init_huffman(struct cvu_huffman_state *restrict state, uint8_t (*restrict input)(void), const struct cvu_huffman_node *restrict tree, uint8_t root, uint8_t ls, uint8_t bs, uint8_t rs); +uint8_t cvu_get_huffman(struct cvu_huffman_state *state); + +// RLE decompression +struct cvu_rle_state // Changing this struct will affect asm implementation of cvu_get_rle, _read_from_array +{ + uint8_t (*input)(void); + uint8_t escape; + uint8_t left; + uint8_t buffer; +}; + +void cvu_init_rle(struct cvu_rle_state *restrict state, uint8_t (*restrict input)(void), uint8_t escape); +uint8_t cvu_get_rle(struct cvu_rle_state *state); + +// LZK decompression +struct cvu_lzk_state +{ + uint8_t (*input)(void); + uint8_t escape; + uint8_t left; + uint8_t offset; + uint8_t start; + uint8_t buffer[64]; +}; + +void cvu_init_lzk(struct cvu_lzk_state *restrict state, uint8_t (*restrict input)(void), uint8_t escape); +uint8_t cvu_get_lzk(struct cvu_lzk_state *state); + +// Decompression routines which will handle all the details for you. +// Just create a cvu_compression_state struct, initialize it and decompress. +struct cvu_compression_state // Changing this struct will affect asm implementation of _read_from_array +{ + struct cvu_huffman_state huffman; + struct cvu_rle_state rle; + const uint8_t *data; +}; + +// Initilization: +// data: compressed data +// state: compression struct to initialize +// tree: huffman tree generated by huffman_analyzer +// root, ls, bs, rs: constants generated by huffman_analyzer +// escape: constant generated by rle_analyzer +void cvu_init_compression(const uint8_t *restrict data, struct cvu_compression_state *restrict state, const struct cvu_huffman_node *restrict tree, uint8_t root, uint8_t ls, uint8_t bs, uint8_t rs, uint8_t escape); + +// The functions below can be mixed: + +// This function will return a decompressed octet on each invocation. +uint8_t cvu_get_compression(struct cvu_compression_state *state); + +// This function will decompress and write n octets to graphics memory at dest. +// It is not reentrant and may not be called why any function from cvu_graphics.h marked as such is called. +void cvu_memtovmemcpy_compression(cv_vmemp dest, struct cvu_compression_state *state, size_t n); + +// This function will decompress and write n octets to memory at dest. +void *cvu_memcpy_compression(void *restrict dest, struct cvu_compression_state *state, size_t n); + +#endif + +#ifndef CVU_SOUND_H +#define CVU_SOUND 1 + +#include + +#include "cv_sound.h" + +extern const uint16_t CVU_TUNING_ISO16_EQUAL[15]; // ISO 16 pitch (A at 440 Hz) with equal tuning. +extern const uint16_t CVU_TUNING_SCIENTIFIC_EQUAL[15]; // Scientific pitch (C at 256 Hz) with equal tuning. + +extern const uint8_t CVU_VOLUME_DEFAULT[4]; + +extern const uint16_t CVU_EMPTY_MUSIC; + +// channel holds the channel that will be used to play the music. +// volume is a pointer to an array of loudnesses in Dezibel for p, mp, mf, f. +// tuning is a pointer to an arrays of frequency dividers for the halftones of oktave 0. +// sixteenth_notes_per_second should explain itself. +// notes is a pointer to the music in the following format: +// Every note cosists of 16 bits. The most significant four mark the octave, the next 4 +// the halftone (0xf means pause) the next 4 bits give the absolute length. The next 2 +// give the relative length. the last 2 bits are the loudness. +// The rest of the structure's members are for internal use by cvu_play_music(). +struct cvu_music +{ + enum cv_soundchannel channel; + const uint8_t *volume; + const uint16_t *tuning; + uint8_t sixteenth_notes_per_second; + const uint16_t *notes; + + uint16_t note_ticks_remaining; + uint16_t pause_ticks_remaining; +}; + +// This will initialize a cvu_music structure with default values for all +// members except notes. +extern void cvu_init_music(struct cvu_music *music); + +// This function should be placed inside the vint handler or triggered by the vint handler. +// It will return false once it is finished playing the music. +extern bool cvu_play_music(struct cvu_music *restrict music); + +#endif + +// (c) 2013 Philipp Klaus Krause + +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. + +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. + +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +#ifndef CVU_H +#define CVU_H 1 + +#define CVU_LIBVERSION_MAJOR 0 +#define CVU_LIBVERSION_MINOR 15 +#define CVU_LIBVERSION_STRING "0.15" + +#include "cvu_input.h" +#include "cvu_graphics.h" +#include "cvu_sound.h" +#include "cvu_compression.h" +#include "cvu_f.h" +#include "cvu_c.h" + +#endif + +// Fixed-point math can be useful where e.g. smooth movement is desired, but +// using float would make the application too slow and big. +// cvu_f is a 10.6 fixed point type. 10.6 has been chosen to ensure that the +// type can represent coordinates on the ColecoVision screen and in some +// "buffer" space surrounding it (to allow calculation of e.g. reflection). + +#ifndef CVU_F_H +#define CVU_F_H 1 + +#include +#include + +typedef int16_t cvu_f; // 10.6 fixed-point type. + +#define CVU_F_R 6 + +#define CVU_F_PI 201 +#define CVU_F_PI_2 100 +#define CVU_F_SQRT2 90 +#define CVU_F_SQRT1_2 45 +#define CVU_F_MIN INT16_MIN +#define CVU_F_MAX INT16_MAX + +// Convert integer to fixed-point +#define CVU_F2I(l) ((l) >> CVU_F_R) + +// Convert fixed-point to integer +#define CVU_I2F(l) ((l) << CVU_F_R) + +// Fixed-point multiplication +extern cvu_f cvu_fmul2(cvu_f l, cvu_f r); + +// Fixed-point division +extern cvu_f cvu_fdiv2(cvu_f l, cvu_f r); + +// Fixed-point sine +extern cvu_f cvu_fsin(cvu_f x); + +// Fixed-point cosine +extern cvu_f cvu_fcos(cvu_f x); + +// Fixed-point arcus tangens of x / y. +extern cvu_f cvu_fatan2(cvu_f y, cvu_f x); + +#endif + diff --git a/src/worker/fssdcc.js b/src/worker/fssdcc.js index 6841d1b6..006dc743 100644 --- a/src/worker/fssdcc.js +++ b/src/worker/fssdcc.js @@ -85,8 +85,10 @@ Module.expectedDataFileDownloads++; console.error('package error:', error); }; - var fetched = null, fetchedCallback = null; - fetchRemotePackage(REMOTE_PACKAGE_NAME, REMOTE_PACKAGE_SIZE, function(data) { + var fetchedCallback = null; + var fetched = Module['getPreloadedPackage'] ? Module['getPreloadedPackage'](REMOTE_PACKAGE_NAME, REMOTE_PACKAGE_SIZE) : null; + + if (!fetched) fetchRemotePackage(REMOTE_PACKAGE_NAME, REMOTE_PACKAGE_SIZE, function(data) { if (fetchedCallback) { fetchedCallback(data); fetchedCallback = null; @@ -101,6 +103,7 @@ Module.expectedDataFileDownloads++; if (!check) throw msg + new Error().stack; } Module['FS_createPath']('/', 'include', true, true); +Module['FS_createPath']('/include', 'pic16', true, true); Module['FS_createPath']('/include', 'ds390', true, true); Module['FS_createPath']('/include', 'asm', true, true); Module['FS_createPath']('/include/asm', 'default', true, true); @@ -115,12 +118,18 @@ Module['FS_createPath']('/include/asm', 'pic14', true, true); Module['FS_createPath']('/include/asm', 'gbz80', true, true); Module['FS_createPath']('/include/asm', 'r2k', true, true); Module['FS_createPath']('/include/asm', 'z80', true, true); +Module['FS_createPath']('/include', 'xa51', true, true); Module['FS_createPath']('/include', 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data_size: 0x2000, stack_end: 0x0, }, 'sound_williams-z80': { code_start: 0x0, - code_size: 0x4000, + rom_size: 0x4000, data_start: 0x4000, data_size: 0x400, stack_end: 0x8000, }, 'base_z80': { code_start: 0x0, - code_size: 0x8000, + rom_size: 0x8000, data_start: 0x8000, data_size: 0x8000, stack_end: 0x0, }, 'coleco': { - code_start: 0x8000, - code_size: 0x8000, - data_start: 0x6000, + rom_start: 0x8000, + code_start: 0x8100, + rom_size: 0x8000, + data_start: 0x7000, data_size: 0x400, stack_end: 0x8000, + extra_preproc_args: ['-I', '/share/include/libcv', '-I', '/share/include/libcvu'], + extra_link_args: ['-k', '/share/lib/libcv', '-l', 'libcv', '-k', '/share/lib/libcvu', '-l', 'libcvu', '/share/lib/libcv/crt0.rel', 'main.rel'], }, }; @@ -631,13 +634,13 @@ function hexToArray(s, ofs) { return arr; } -function parseIHX(ihx, code_start, code_size) { - var output = new Uint8Array(new ArrayBuffer(code_size)); +function parseIHX(ihx, rom_start, rom_size) { + var output = new Uint8Array(new ArrayBuffer(rom_size)); for (var s of ihx.split("\n")) { if (s[0] == ':') { var arr = hexToArray(s, 1); var count = arr[0]; - var address = (arr[1]<<8) + arr[2] - code_start; + var address = (arr[1]<<8) + arr[2] - rom_start; var rectype = arr[3]; if (rectype == 0) { for (var i=0; i:2: error: Can't open include file "foo.h" var errors = []; var match_fn = makeErrorMatcher(errors, /:(\d+): (.+)/, 1, 2); @@ -873,13 +891,17 @@ function preprocessMCPP(code, platform) { var FS = MCPP['FS']; setupFS(FS, 'sdcc'); FS.writeFile("main.c", code, {encoding:'utf8'}); - MCPP.callMain([ + var args = [ "-D", "__8BITWORKSHOP__", "-D", platform.toUpperCase().replace('-','_'), "-D", "__SDCC_z80", "-I", "/share/include", "-Q", - "main.c", "main.i"]); + "main.c", "main.i"]; + if (params.extra_preproc_args) { + args.push.apply(args, params.extra_preproc_args); + } + MCPP.callMain(args); try { var iout = FS.readFile("main.i", {encoding:'utf8'}); iout = iout.replace(/^#line /gm,'\n# ');