diff --git a/presets/verilog/lfsr.v b/presets/verilog/lfsr.v index 6ca74cc1..14f6d8c1 100644 --- a/presets/verilog/lfsr.v +++ b/presets/verilog/lfsr.v @@ -1,19 +1,23 @@ -module LFSR8_11D( - input clk, - output reg [7:0] LFSR = 255 // put here the initial value -); -wire feedback = LFSR[7]; +module LFSR(clk,reset,enable,lfsr); + + parameter NBITS = 8; + parameter TAPS = 8'b11101; + parameter INVERT = 0; + + input clk, reset; + input enable; + output reg [NBITS-1:0] lfsr; + + wire feedback = lfsr[NBITS-1] ^ INVERT; + + always @(posedge clk) + begin + if (reset) // initialize to 1 + lfsr <= {lfsr[NBITS-2:1], 1'b0, 1'b1}; + else if (enable) + lfsr <= {lfsr[NBITS-2:0], 1'b0} ^ (feedback ? TAPS : 0); + end + +endmodule; -always @(posedge clk) -begin - LFSR[0] <= feedback; - LFSR[1] <= LFSR[0]; - LFSR[2] <= LFSR[1] ^ feedback; - LFSR[3] <= LFSR[2] ^ feedback; - LFSR[4] <= LFSR[3] ^ feedback; - LFSR[5] <= LFSR[4]; - LFSR[6] <= LFSR[5]; - LFSR[7] <= LFSR[6]; -end -endmodule diff --git a/presets/verilog/music.v b/presets/verilog/music.v index ff9f05ff..dcd145fc 100644 --- a/presets/verilog/music.v +++ b/presets/verilog/music.v @@ -13,10 +13,11 @@ module sound_psg(clk, reset, out, reg_sel, reg_data, reg_write); reg outputs[NVOICES]; reg [17:0] count[NVOICES]; reg [7:0] register[16]; + integer i; always @(posedge clk) begin out = 0; - for (int i=0; i VL_EXTENDS_II(x,lbits,rhs); } + return 0 | (VL_EXTENDS_II(x,lbits,lhs) > VL_EXTENDS_II(x,lbits,rhs)); } var VL_LTES_III = this.VL_LTES_III = function(x,lbits,y,lhs,rhs) { - return VL_EXTENDS_II(x,lbits,lhs) <= VL_EXTENDS_II(x,lbits,rhs); } + return 0 | (VL_EXTENDS_II(x,lbits,lhs) <= VL_EXTENDS_II(x,lbits,rhs)); } var VL_GTES_III = this.VL_GTES_III = function(x,lbits,y,lhs,rhs) { - return VL_EXTENDS_II(x,lbits,lhs) >= VL_EXTENDS_II(x,lbits,rhs); } + return 0 | (VL_EXTENDS_II(x,lbits,lhs) >= VL_EXTENDS_II(x,lbits,rhs)); } var VL_MODDIV_III = this.VL_MODDIV_III = function(lbits,lhs,rhs) { return (((rhs)==0)?0:(lhs)%(rhs)); } @@ -92,7 +95,7 @@ var vl_stopped = false; vl_stopped = true; } - var VL_RAND_RESET_I = this.VL_RAND_RESET_I = function(bits) { return Math.floor(Math.random() * (1<1: + print seqlen, "#(%d,%d'%s,%d)" % (n,n,bin(i)[1:],invert), seqindex