6502
/
8bitworkshop
mirror of https://github.com/sehugg/8bitworkshop.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

updated package-lock.json, define __MAIN__ and __8BITWORKSHOP__ for ca65

This commit is contained in:
Steven Hugg 2021-07-15 08:41:51 -05:00
parent 9f39f9c531
commit 8d756ff363
7 changed files with 38 additions and 1946 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Makefile
View File

@ -36,7 +36,7 @@ desktop: distro
pushd $(TMP) && npm i && popd $(TMP)
mkdir -p $(TMP)/resources
./node_modules/.bin/electron-builder -mlw --project $(TMP) # --prepackaged $(TMP)
mv $(TMP)/dist/*.* ./release/
mv $(TMP)/dist/*.* ./release/desktop/
meta/electron.diff: index.html electron.html
-diff -u index.html electron.html > $@

2
doc/notes.txt
View File

@ -553,5 +553,3 @@ preprocessor differences (#define FOO 1 so #if works)
extern void do_func(void)
#pragma warnings
CFG files

1808
package-lock.json generated
View File

File diff suppressed because it is too large Load Diff

26
src/common/hdl/vxmlparser.ts
View File

@ -110,6 +110,7 @@ export class VerilogXMLParser implements HDLUnit {
cur_node : XMLNode;
cur_module : HDLModuleDef;
cur_loc : HDLSourceLocation;
cur_loc_str : string;
cur_deferred = [];
constructor() {
@ -153,17 +154,22 @@ export class VerilogXMLParser implements HDLUnit {
parseSourceLocation(node: XMLNode): HDLSourceLocation {
var loc = node.attrs['loc'];
if (loc) {
var [fileid, line, col, end_line, end_col] = loc.split(',');
var $loc = {
hdlfile: this.files[fileid],
path: this.files[fileid].filename,
line: parseInt(line),
start: parseInt(col)-1,
end_line: parseInt(end_line),
end: parseInt(end_col)-1,
if (loc == this.cur_loc_str) {
return this.cur_loc; // cache last parsed $loc object
} else {
var [fileid, line, col, end_line, end_col] = loc.split(',');
var $loc = {
hdlfile: this.files[fileid],
path: this.files[fileid].filename,
line: parseInt(line),
start: parseInt(col)-1,
end_line: parseInt(end_line),
end: parseInt(end_col)-1,
}
this.cur_loc = $loc;
this.cur_loc_str = loc;
return $loc;
}
this.cur_loc = $loc;
return $loc;
} else {
return null;
}

11
src/worker/workermain.ts
View File

@ -1094,7 +1094,12 @@ function assembleCA65(step:BuildStep) {
setupFS(FS, '65-'+getRootBasePlatform(step.platform));
populateFiles(step, FS);
fixParamsWithDefines(step.path, step.params);
execMain(step, CA65, ['-v', '-g', '-I', '/share/asminc', '-o', objpath, '-l', lstpath, step.path]);
var args = ['-v', '-g', '-I', '/share/asminc', '-o', objpath, '-l', lstpath, step.path];
args.unshift.apply(args, ["-D", "__8BITWORKSHOP__=1"]);
if (step.mainfile) {
args.unshift.apply(args, ["-D", "__MAIN__=1"]);
}
execMain(step, CA65, args);
if (errors.length)
return {errors:errors};
objout = FS.readFile(objpath, {encoding:'binary'});
@ -1292,6 +1297,7 @@ function compileCC65(step:BuildStep) {
'-Cl', // static locals
'-I', '/share/include',
'-I', '.',
"-D", "__8BITWORKSHOP__",
];
if (params.define) {
params.define.forEach((x) => args.push('-D'+x));
@ -1810,7 +1816,8 @@ function compileVerilator(step:BuildStep) {
starttime();
var xmlPath = `obj_dir/V${topmod}.xml`;
try {
var args = ["--cc", "-O3"/*abcdefstzsuka*/, "-DEXT_INLINE_ASM", "-DTOPMOD__"+topmod,
var args = ["--cc", "-O3"/*abcdefstzsuka*/,
"-DEXT_INLINE_ASM", "-DTOPMOD__"+topmod, "-D__8BITWORKSHOP__",
"-Wall",
"-Wno-DECLFILENAME", "-Wno-UNUSED", "-Wno-EOFNEWLINE", "-Wno-PROCASSWIRE",
"--x-assign", "fast", "--noassert", "--pins-sc-biguint",

34
test/cli/testworker.js
View File

@ -16,7 +16,7 @@ global.onmessage({data:{preload:'inform6'}});
// TODO: check msg against spec
function compile(tool, code, platform, callback, outlen, nlines, nerrors, options) {
var msgs = [{code:code, platform:platform, tool:tool, path:'src.'+tool}];
var msgs = [{code:code, platform:platform, tool:tool, path:'src.'+tool, mainfile:true}];
doBuild(msgs, callback, outlen, nlines, nerrors, options);
}
@ -87,22 +87,8 @@ describe('Worker', function() {
it('should NOT assemble DASM', function(done) {
compile('dasm', '\tprocessor 6502\n\torg $f000 ; this is a comment\nfoo asl a\n', 'vcs', done, 0, 0, 2);
});
/*
it('should assemble ACME', function(done) {
compile('acme', 'foo: lda #0\n', 'vcs', done, 2, 0); // TODO
});
it('should NOT assemble ACME', function(done) {
compile('acme', 'foo: xxx #0\n', 'vcs', done, 0, 0, 2); // TODO
});
it('should compile PLASMA', function(done) {
compile('plasm', 'word x = 0', 'apple2', done, 5, 0);
});
it('should NOT compile PLASMA', function(done) {
compile('plasm', 'word x = ', 'apple2', done, 0, 0, 1);
});
*/
it('should compile CC65', function(done) {
compile('cc65', 'int main() {\nint x=1;\nreturn x+2;\n}', 'nes.mame', done, 40976, 3);
compile('cc65', '#if defined(__8BITWORKSHOP__) && defined(__MAIN__)\nint main() {\nint x=1;\nreturn x+2;\n}\n#endif', 'nes.mame', done, 40976, 3);
});
it('should NOT compile CC65 (compile error)', function(done) {
compile('cc65', 'int main() {\nint x=1;\nprintf("%d",x);\nreturn x+2;\n}', 'nes', done, 0, 0, 1);
@ -113,14 +99,6 @@ describe('Worker', function() {
it('should NOT compile CC65 (preproc error)', function(done) {
compile('cc65', '#include "NOSUCH.file"\n', 'nes', done, 0, 0, 1, {ignoreErrorPath:true});
});
/*
it('should assemble Z80ASM', function(done) {
compile('z80asm', '\tMODULE test\n\tEXTERN _puts\n\tld hl,$0000\n\tret\n', 'mw8080bw', done, 4, 2, 0);
});
it('should NOT assemble Z80ASM', function(done) {
compile('z80asm', 'ddwiuweq', 'mw8080bw', done, 0, 0, 1);
});
*/
it('should assemble SDASZ80', function(done) {
compile('sdasz80', '\tld hl,#0\n\tret\n', 'mw8080bw', done, 8192, 2);
});
@ -131,7 +109,7 @@ describe('Worker', function() {
compile('sdasz80', '\tcall divxxx\n', 'mw8080bw', done, 0, 0, 1, {ignoreErrorPath:true});
});
it('should compile SDCC', function(done) {
compile('sdcc', 'int foo=0; // comment\nint main(int argc) {\nint x=1;\nint y=2+argc;\nreturn x+y+argc;\n}\n', 'mw8080bw', done, 8192, 3, 0);
compile('sdcc', 'int foo=0; // comment\n#if defined(__8BITWORKSHOP__) && defined(__MAIN__)\nint main(int argc) {\nint x=1;\nint y=2+argc;\nreturn x+y+argc;\n}\n#endif\n', 'mw8080bw', done, 8192, 3, 0);
});
it('should compile SDCC w/ include', function(done) {
compile('sdcc', '#include <string.h>\nvoid main() {\nstrlen(0);\n}\n', 'mw8080bw', done, 8192, 2, 0);
@ -261,18 +239,16 @@ describe('Worker', function() {
compile('cc65', '#define NES_MAPPER 4\nint main() {\nint x=1;\nreturn x+2;\n}', 'nes', done, 131088, 3);
});
it('should assemble CA65', function(done) {
compile('ca65', ';#define LIBARGS ,\n\t.segment "HEADER"\n\t.segment "STARTUP"\n\t.segment "CHARS"\n\t.segment "VECTORS"\n\t.segment "SAMPLES"\n\t.segment "CODE"\n\tlda #0\n\tsta $1\n', 'nes', done, 131088, 2);
compile('ca65', ';#define LIBARGS ,\n\t.segment "HEADER"\n\t.segment "STARTUP"\n\t.segment "CHARS"\n\t.segment "VECTORS"\n\t.segment "SAMPLES"\n\t.segment "CODE"\n.ifdef __MAIN__\n\tlda #0\n\tsta $1\n.endif\n', 'nes', done, 131088, 2);
});
it('should compile C64 cc65 skeleton', function(done) {
var csource = ab2str(fs.readFileSync('presets/c64/skeleton.cc65'));
compile('cc65', csource, 'c64.wasm', done, 2753, 2, 0);
});
/*
it('should compile zmachine inform6 skeleton', function(done) {
var csource = ab2str(fs.readFileSync('presets/zmachine/skeleton.inform6'));
compile('inform6', csource, 'hello.z5', done, 2753, 2, 0);
compile('inform6', csource, 'hello.z5', done, 92672, 0, 0);
});
*/
// TODO: vectrex, x86
it('should compile basic example', function(done) {
var csource = ab2str(fs.readFileSync('presets/basic/wumpus.bas'));

101
test/cli/verilog/t_order_doubleloop.v
View File

@ -1,101 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off LATCH
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
// verilator lint_off MULTIDRIVEN
// verilator lint_off BLKANDNBLK
reg [31:0] comcnt;
reg [31:0] dlycnt; initial dlycnt=0;
reg [31:0] lastdlycnt; initial lastdlycnt = 0;
reg [31:0] comrun; initial comrun = 0;
reg [31:0] comrunm1;
reg [31:0] dlyrun; initial dlyrun = 0;
reg [31:0] dlyrunm1;
always @ (posedge clk) begin
$write("[%0t] cyc %d\n",$time,cyc);
cyc <= cyc + 1;
if (cyc==2) begin
// Test # of iters
lastdlycnt = 0;
comcnt = 0;
dlycnt <= 0;
end
if (cyc==3) begin
dlyrun <= 5;
dlycnt <= 0;
end
if (cyc==4) begin
comrun = 4;
end
end
always @ (negedge clk) begin
if (cyc==5) begin
$display("%d %d\n", dlycnt, comcnt);
if (dlycnt != 32'd5) $stop;
if (comcnt != 32'd19) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
// This forms a "loop" where we keep going through the always till comrun=0
reg runclk; initial runclk = 1'b0;
always @ (/*AS*/comrunm1 or dlycnt) begin
if (lastdlycnt != dlycnt) begin
comrun = 3;
$write ("[%0t] comrun=%0d start\n", $time, comrun);
end
else if (comrun > 0) begin
comrun = comrunm1;
if (comrunm1==1) begin
runclk = 1;
$write ("[%0t] comrun=%0d [trigger clk]\n", $time, comrun);
end
else $write ("[%0t] comrun=%0d\n", $time, comrun);
end
lastdlycnt = dlycnt;
end
always @ (/*AS*/comrun) begin
if (comrun!=0) begin
comrunm1 = comrun - 32'd1;
comcnt = comcnt + 32'd1;
$write("[%0t] comcnt=%0d\n",$time,comcnt);
end
end
// This forms a "loop" where we keep going through the always till dlyrun=0
reg runclkrst;
always @ (posedge runclk) begin
runclkrst <= 1;
$write ("[%0t] runclk\n", $time);
if (dlyrun > 0) begin
dlyrun <= dlyrun - 32'd1;
dlycnt <= dlycnt + 32'd1;
$write ("[%0t] dlyrun<=%0d\n", $time, dlyrun-32'd1);
end
end
always @* begin
if (runclkrst) begin
$write ("[%0t] runclk reset\n", $time);
runclkrst = 0;
runclk = 0;
end
end
endmodule