From bf5248685fbf65f22670e01fec2cc517efe80f23 Mon Sep 17 00:00:00 2001
From: Steven Hugg <hugg@fasterlight.com>
Date: Wed, 23 Sep 2020 12:00:47 -0500
Subject: [PATCH] verilog: hide controls when no crt

---
 src/ide/ui.ts           | 3 ++-
 src/platform/verilog.ts | 5 +++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/ide/ui.ts b/src/ide/ui.ts
index a6fad22f..cdab5c53 100644
--- a/src/ide/ui.ts
+++ b/src/ide/ui.ts
@@ -1686,6 +1686,7 @@ function setupDebugControls() {
     uitoolbar.add('ctrl+alt+l', 'Run To Line', 'glyphicon-save', runToCursor).prop('id','dbg_toline');
   }
   uitoolbar.newGroup();
+  uitoolbar.grp.prop('id','xtra_bar');
   // add menu clicks
   $(".dropdown-menu").collapse({toggle: false});
   $("#item_new_file").click(_createNewFile);
@@ -1898,7 +1899,7 @@ function showWelcomeMessage() {
 
 ///////////////////////////////////////////////////
 
-var qs = (function (a : string[]) {
+export var qs = (function (a : string[]) {
     if (!a || a.length == 0)
         return {};
     var b = {};
diff --git a/src/platform/verilog.ts b/src/platform/verilog.ts
index 02d8c600..77b98b09 100644
--- a/src/platform/verilog.ts
+++ b/src/platform/verilog.ts
@@ -657,8 +657,12 @@ var VerilogPlatform = function(mainElement, options) {
           const IGNORE_SIGNALS = ['clk','reset'];
           trace_signals = trace_signals.filter((v) => { return IGNORE_SIGNALS.indexOf(v.name)<0; }); // remove clk, reset
           $("#speed_bar").show();
+          $("#run_bar").show();
+          $("#xtra_bar").show();
         } else {
           $("#speed_bar").hide();
+          $("#run_bar").hide();
+          $("#xtra_bar").hide();
         }
       }
     }
@@ -834,3 +838,4 @@ var VerilogVGAPlatform = function(mainElement, options) {
 
 PLATFORMS['verilog'] = VerilogPlatform;
 PLATFORMS['verilog-vga'] = VerilogVGAPlatform;
+PLATFORMS['verilog-test'] = VerilogPlatform;