update lsfr preset; filter verilog boring errors

This commit is contained in:
Steven Hugg 2018-07-20 20:04:39 -05:00
parent 9938a17093
commit d5a146bf71
8 changed files with 56 additions and 9 deletions

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@ -11,7 +11,7 @@ TODO:
- debugging inside of bank switching??? relocated segs?
- support 6502 test cases
- DASM: macro forward refs
- asm: support macro expansion (need addr2line map)
- asm: support macro expansion
- support narrow screens
- show other TIA internal values
- case sensisitvity looking for mismatch variables

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@ -3,9 +3,9 @@
module LFSR(clk,reset,enable,lfsr);
parameter NBITS = 8;
parameter TAPS = 8'b11101;
parameter INVERT = 0;
localparam NBITS = $size(TAPS);
input clk, reset;
input enable;

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@ -26,7 +26,7 @@ module sound_generator(clk, reset, spkr,
reg [15:0] lfsr; // LFSR output
LFSR #(16,16'b1000000001011,0) lfsr_gen(
LFSR #(16'b1000000001011,0) lfsr_gen(
.clk(clk),
.reset(reset),
.enable(div16 == 0 && noise_count == 0),

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@ -24,7 +24,7 @@ module starfield_top(clk, reset, hsync, vsync, rgb);
wire star_enable = !hpos[8] & !vpos[8];
// LFSR with period = 2^16-1 = 256*256-1
LFSR #(16,16'b1000000001011,0) lfsr_gen(
LFSR #(16'b1000000001011,0) lfsr_gen(
.clk(clk),
.reset(reset),
.enable(star_enable),

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@ -1189,6 +1189,9 @@ function compileVerilator(step) {
errors.push({line:0,msg:"Compiler internal error: " + e});
}
endtime("compile");
// remove boring errors
errors = errors.filter(function(e) { return !/Exiting due to \d+/.exec(e.msg); }, errors);
errors = errors.filter(function(e) { return !/Use ["][/][*]/.exec(e.msg); }, errors);
if (errors.length) {
return {errors:errors};
}

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@ -162,7 +162,7 @@ describe('Worker', function() {
assert.ok(fn);
done(err, msg);
};
doBuild(msgs, done2, 2782, 0, 0);
doBuild(msgs, done2, 2799, 0, 0);
});
it('should compile verilog inline assembler (JSASM)', function(done) {
var csource = ab2str(fs.readFileSync('presets/verilog/racing_game_cpu.v'));
@ -179,7 +179,7 @@ describe('Worker', function() {
assert.ok(fn);
done(err, msg);
};
doBuild(msgs, done2, 49317, 0, 0);
doBuild(msgs, done2, 49357, 0, 0);
});
it('should compile verilog assembler file (JSASM)', function(done) {
var csource = ab2str(fs.readFileSync('presets/verilog/test2.asm'));

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@ -1,8 +1,10 @@
#!/usr/bin/python
print "Period,nbits,feedback,mask"
MAXBITS=16
for n in range(1,18):
print("Period,nbits,feedback,mask")
for n in range(1,MAXBITS):
mask = (1<<n)-1
hibit = (1<<(n-1))
for i in range(0,1<<n):
@ -25,4 +27,4 @@ for n in range(1,18):
seqindex = seq.index(x)
seqlen = len(seq) - seqindex
if seqlen>1:
print seqlen, "#(%d,%d'%s,%d)" % (n,n,bin(i)[1:],invert), seqindex
print(seqlen, "#(%d,%d'%s,%d)" % (n,n,bin(i)[1:],invert), seqindex)

42
tools/lfsrcalc2.js Executable file
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@ -0,0 +1,42 @@
"use strict";
var BEST={}
var MAXBITS=17
//MAXBITS=12
for (var n=1; n<MAXBITS; n++) {
var mask = (1<<n)-1;
var hibit = (1<<(n-1));
for (var i=0; i < (1<<n); i++) {
for (var invert=0; invert<2; invert++) {
var x = 1;
var seq = [];
var seen = new Map();
while (x && !seen.get(x)) {
seq.push(x);
seen.set(x, true);
var feedback = (x & hibit) != 0;
x = ((x << 1) & mask);
if (invert && !feedback) x ^= i;
if (!invert && feedback) x ^= i;
}
if (x) {
var seqindex = seq.indexOf(x);
var seqlen = seq.length - seqindex;
if (seqlen > 1 && x == 1) {
if (!BEST[seqlen] || n < BEST[seqlen].n) {
BEST[seqlen] = {n:n, i:i, invert:invert};
//console.log(seqlen + "\t" + n + "\t" + i.toString(2) + "\t" + x.toString(2));
}
}
}
}
}
}
for (var seqlen in BEST) {
var b = BEST[seqlen];
console.log(seqlen+" &\t@"+b.n+"'b"+b.i.toString(2)+","+b.invert+"@ \\\\");
}