8 Commits

Author	SHA1	Message	Date
Steven Hugg	495896c43d	updated tests	2018-06-11 10:01:09 -07:00
Steven Hugg	e29bfb5f7e	working on assembler	2018-05-27 11:13:06 -07:00
Steven Hugg	09fb489c2d	assembler: added .string .data .align	2018-04-16 20:16:58 -07:00
Steven Hugg	5b92659b97	"Save As"; command-line assembler; 32-bit limit (so far) in opcodes	2018-03-23 15:05:08 -06:00
Steven Hugg	c14e470778	can load verilog module from .asm file	2018-03-01 23:15:33 -06:00
Steven Hugg	b2beb2670c	more Verilog code; inline asm for depends; fixed tank	2018-02-25 10:34:27 -06:00
Steven Hugg	20ddb8a11f	moved around ALU ops, 16-bit cpu, reg/wire	2018-02-21 11:03:38 -06:00
Steven Hugg	f6d320a05b	new inline verilog assembler	2018-02-18 11:14:04 -06:00