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1,445 Commits 3 Branches 31 Tags 161 MiB
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5 Commits

Author SHA1 Message Date
Steven Hugg
951088dd3b added comments to verilog examples 2018-10-01 12:30:47 -04:00
Steven Hugg
4a82d341bc make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes 2018-08-14 00:05:02 -04:00
Steven Hugg
20ddb8a11f moved around ALU ops, 16-bit cpu, reg/wire 2018-02-21 11:03:38 -06:00
Steven Hugg
1790ca1747 updated verilog presets and test makefile 2018-02-16 23:33:29 -06:00
Steven Hugg
11992645d6 more presets 2018-02-09 00:11:36 -06:00