12 Commits

Author	SHA1	Message	Date
Steven Hugg	716205a2b1	fixed unit tests	2018-10-03 15:06:48 -04:00
Steven Hugg	5c5ee32a66	verilog pixel editor fix (array index must be unsized)	2018-10-02 11:24:29 -04:00
Steven Hugg	1a7480ea65	Merge branch 'master' of github.com:sehugg/8bitworkshop	2018-10-01 13:36:56 -04:00
Steven Hugg	7e00cc898b	verilog preset comments	2018-10-01 13:36:26 -04:00
Steven Hugg	951088dd3b	added comments to verilog examples	2018-10-01 12:30:47 -04:00
Steven Hugg	4a82d341bc	make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes	2018-08-14 00:05:02 -04:00
Steven Hugg	b2beb2670c	more Verilog code; inline asm for depends; fixed tank	2018-02-25 10:34:27 -06:00
Steven Hugg	20ddb8a11f	moved around ALU ops, 16-bit cpu, reg/wire	2018-02-21 11:03:38 -06:00
Steven Hugg	1790ca1747	updated verilog presets and test makefile	2018-02-16 23:33:29 -06:00
Steven Hugg	11992645d6	more presets	2018-02-09 00:11:36 -06:00
Steven Hugg	122e462c9f	work on cpu, sprite	2018-02-05 18:05:49 -06:00
Steven Hugg	f0f6783f6b	more verilog presets	2018-02-03 20:37:12 -06:00