67 Commits

Author	SHA1	Message	Date
Steven Hugg	d8a98989f5	converted src/platform to typescript; stack debug view	2018-08-16 22:30:51 -04:00
Steven Hugg	bb639a0820	link dependencies have depenencies too; coleco uses common.[ch]	2018-08-12 20:48:20 -04:00
Steven Hugg	1a4d088ce2	fixed apple2 code offset	2018-08-06 17:00:14 -04:00
Steven Hugg	2e37e22eb8	WORKERFS performance fix for reads; prepend "__" to store avoid local storage corruption	2018-08-06 11:54:47 -04:00
Steven Hugg	0cb8ea7661	setMainFile() starts 1st build; multiple listing files for DASM includes; updated tests	2018-08-04 11:29:47 -04:00
Steven Hugg	7880602e81	nes runToVsync; debug info changes	2018-08-03 12:18:08 -04:00
Steven Hugg	6e5005f613	look in cache first, fetch local/ verilog includes too; apple2 reset; platform checkmark	2018-07-25 13:02:44 -04:00
Steven Hugg	d5a146bf71	update lsfr preset; filter verilog boring errors	2018-07-21 09:34:06 -05:00
Steven Hugg	12ad4648dc	added checkmarks to window list; fixed test	2018-07-14 15:19:58 -05:00
Steven Hugg	d35a328246	fixed verilog inline asm	2018-07-12 06:50:40 -05:00
Steven Hugg	2759acd958	converted some worker helper files to .ts (loadGen)	2018-07-10 23:04:28 -05:00
Steven Hugg	613277f0e9	trying to fix wasm heap	2018-07-10 22:17:39 -05:00
Steven Hugg	a8c1ead244	more modules to typescript	2018-07-10 19:58:46 -05:00
Steven Hugg	bbe665bb03	fixed verilog tests	2018-07-09 21:00:05 -05:00
Steven Hugg	d6a702b929	fixed test, verilog; updated slip counter preset	2018-07-09 20:46:45 -05:00
Steven Hugg	82f01b3fcd	moved some types to workertypes.ts	2018-07-08 09:07:19 -05:00
Steven Hugg	79e77751ee	fixed verilog test which had nothing to do w/ typescript	2018-07-05 21:46:51 -05:00
Steven Hugg	62f5303107	converting some stuff to TypeScript (make tsweb)	2018-07-05 21:23:08 -05:00
Steven Hugg	1176195149	fixed line #s for errors	2018-07-02 22:39:23 -06:00
Steven Hugg	958fbe747f	error messages for LD65	2018-07-02 21:55:38 -06:00
Steven Hugg	08b32e0102	fixed vicdual skeleton test	2018-07-02 16:48:17 -06:00
Steven Hugg	19a38a3c5e	support multiple workspace windows; //#link "file"	2018-07-02 07:34:20 -06:00
Steven Hugg	4595ab7a31	working on tests :^P	2018-06-30 10:13:29 -06:00
Steven Hugg	d146a7adee	clear error markers when build, error, unchanged; hack for dumpMemory() to work	2018-06-29 23:34:31 -06:00
Steven Hugg	952dc1b312	refactored out loadFile()	2018-06-29 17:47:27 -06:00
Steven Hugg	03bf70041d	refactoring; fixed unchanged targets	2018-06-28 19:21:25 -06:00
Steven Hugg	2f2e469110	return multiple listings files from worker; removed unused worker scripts; fixed verilog	2018-06-27 21:02:04 -06:00
Steven Hugg	58d7dbe155	a little ui.js refactoring; fixed viz.html	2018-06-26 23:15:49 -06:00
Steven Hugg	436a476aff	working on cc65 listing parse	2018-06-25 22:00:00 -06:00
Steven Hugg	95a0eeca44	Merge branch 'master' of github.com:sehugg/8bitworkshop	2018-06-25 17:51:07 -04:00
Steven Hugg	4cff4e75bb	fixed test	2018-06-25 10:35:55 -06:00
Steven Hugg	3c7de544b0	dependency check for compile	2018-06-25 08:58:34 -06:00
Steven Hugg	22570ee4e5	refactoring workermain to support multiple files and build steps	2018-06-24 22:53:06 -06:00
Steven Hugg	2f6f426ecc	fiddling with z80asm/sccz80	2018-06-24 02:24:29 -04:00
Steven Hugg	d808cd0833	fixed tests	2018-06-23 19:25:37 -04:00
Steven Hugg	59fd2a2945	added atari5200 support; fixed NES presets	2018-06-23 18:59:36 -04:00
Steven Hugg	219c59cb5b	removed global msvc_errors variable; support .acme assembler	2018-06-19 21:36:35 -04:00
Steven Hugg	495896c43d	updated tests	2018-06-11 10:01:09 -07:00
Steven Hugg	20ddb8a11f	moved around ALU ops, 16-bit cpu, reg/wire	2018-02-21 11:03:38 -06:00
Steven Hugg	f6d320a05b	new inline verilog assembler	2018-02-18 11:14:04 -06:00
Steven Hugg	80588fcb31	verilog: scope updates, show js code, simple cpu	2017-11-28 20:38:48 -05:00
Steven Hugg	32a65a74e0	redir.html	2017-11-23 21:54:51 -05:00
Steven Hugg	1cace9d35c	more verilog unit tests; updated SDCC js/wasm	2017-11-23 19:16:54 -05:00
Steven Hugg	aad8efcfec	added more verilog test cases	2017-11-22 16:51:21 -05:00
Steven Hugg	73e908256e	started adding verilog regress tests	2017-11-22 09:44:57 -05:00
Steven Hugg	2525d6e585	start yosys profiling	2017-11-20 10:32:34 -05:00
Steven Hugg	4f73cde7cc	support `include statements in verilog; book link changes; paddle/switches; scope transitions	2017-11-16 10:30:47 -05:00
Steven Hugg	6d972bf580	WASM support for SDCC compiler; had to fix some presets	2017-11-07 13:40:45 -05:00
Steven Hugg	21ddfce92a	updated presets for new sdcc lib; remap attribute	2017-05-09 09:04:53 -04:00
Steven Hugg	1675ab628e	support ;;{...};; bitmap header for assembler	2017-05-07 22:47:27 -04:00