224 lines
4.7 KiB
Verilog
224 lines
4.7 KiB
Verilog
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`include "hvsync_generator.v"
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`include "font_cp437_8x8.v"
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`include "ram.v"
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`include "tile_renderer.v"
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`include "sprite_scanline_renderer.v"
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`include "lfsr.v"
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`include "sound_generator.v"
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`include "cpu16.v"
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/*
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A full video game console, with the following components:
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64 kilobytes (32,678 16-bit words) of RAM
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16-bit CPU running at 4.857 MHz
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32x30 tile graphics with 256 x 8 tile ROM
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32 16x16 sprites per frame with sprite ROM
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16 colors (two per tile, one per sprite)
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Two game controllers (four direction switches, two buttons)
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One paddle/analog stick controller
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*/
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module cpu_platform(clk, reset, hsync, vsync,
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hpaddle, vpaddle,
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switches_p1, switches_p2,
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rgb);
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input clk, reset;
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input hpaddle, vpaddle;
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input [7:0] switches_p1;
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input [7:0] switches_p2;
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output hsync, vsync;
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output [3:0] rgb;
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wire display_on;
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wire [8:0] hpos;
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wire [8:0] vpos;
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// video RAM bus
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wire [15:0] ram_read;
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reg [15:0] ram_write;
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reg ram_writeenable;
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// multiplex sprite and tile RAM
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reg [15:0] tile_ram_addr;
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reg [5:0] sprite_ram_addr;
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wire tile_reading;
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wire sprite_reading;
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var [14:0] mux_ram_addr; // 15-bit RAM access
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// multiplexor for sprite/tile/CPU RAM
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always @(*)
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if (cpu_busy) begin
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if (sprite_reading)
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mux_ram_addr = {9'b111111100, sprite_ram_addr};
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else
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mux_ram_addr = tile_ram_addr[14:0];
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end else
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mux_ram_addr = cpu_ram_addr[14:0];
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// tile and sprite ROM
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wire [10:0] tile_rom_addr;
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wire [7:0] tile_rom_data;
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wire [15:0] sprite_rom_addr;
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wire [15:0] sprite_rom_data;
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// gfx outputs
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wire [3:0] tile_rgb;
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wire [3:0] sprite_rgb;
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// video sync generator
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(reset),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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// RAM (32k x 16 bits)
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RAM_sync #(15,16) ram(
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.clk(clk),
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.dout(ram_read),
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.din(ram_write),
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.addr(mux_ram_addr),
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.we(ram_writeenable)
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);
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// tile graphics
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tile_renderer tile_gen(
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.clk(clk),
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.reset(reset),
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.hpos(hpos),
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.vpos(vpos),
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.ram_addr(tile_ram_addr),
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.ram_read(ram_read),
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.ram_busy(tile_reading),
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.rom_addr(tile_rom_addr),
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.rom_data(tile_rom_data),
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.rgb(tile_rgb)
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);
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// sprite scanline renderer
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sprite_scanline_renderer ssr(
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.clk(clk),
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.reset(reset),
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.hpos(hpos),
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.vpos(vpos),
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.ram_addr(sprite_ram_addr),
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.ram_data(ram_read),
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.ram_busy(sprite_reading),
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.rom_addr(sprite_rom_addr),
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.rom_data(sprite_rom_data),
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.rgb(sprite_rgb)
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);
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// tile ROM
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font_cp437_8x8 tile_rom(
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.addr(tile_rom_addr),
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.data(tile_rom_data)
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);
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// sprite ROM
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example_bitmap_rom bitmap_rom(
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.addr(sprite_rom_addr),
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.data(sprite_rom_data)
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);
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// sprites overlay tiles
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assign rgb = display_on
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? (sprite_rgb>0 ? sprite_rgb : tile_rgb)
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: 0;
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// CPU
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reg cpu_hold = 0;
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wire cpu_busy;
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wire [15:0] cpu_ram_addr;
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wire busy;
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var [15:0] cpu_bus;
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wire [15:0] flags = {11'b0, vsync, hsync, vpaddle, hpaddle, display_on};
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wire [15:0] switches = {switches_p2, switches_p1};
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// select ROM, RAM, switches ($FFFE) or flags ($FFFF)
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/* verilator lint_off CASEOVERLAP */
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always @(*)
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casez (cpu_ram_addr)
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16'hfffe: cpu_bus = switches;
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16'hffff: cpu_bus = flags;
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16'b0???????????????: cpu_bus = ram_read;
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16'b1???????????????: cpu_bus = program_rom[cpu_ram_addr[14:0]];
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endcase
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// 16-bit CPU
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CPU16 cpu(
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.clk(clk),
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.reset(reset),
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.hold(tile_reading | sprite_reading), // hold input
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.busy(cpu_busy), // busy output
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.address(cpu_ram_addr),
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.data_in(cpu_bus),
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.data_out(ram_write),
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.write(ram_writeenable));
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// program ROM ($8000-$FFFE)
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reg [15:0] program_rom[0:32767];
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// example ROM program code
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`ifdef EXT_INLINE_ASM
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initial begin
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program_rom = '{
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__asm
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.arch femto16
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.org 0x8000
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.len 32768
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mov sp,@$6fff
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mov dx,@InitPageTable
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jsr dx
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mov ax,@$4ffe
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mov dx,@ClearTiles
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jsr dx
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mov dx,@ClearSprites
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jsr dx
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reset
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InitPageTable:
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mov ax,@$6000 ; screen buffer
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mov bx,@$7e00 ; page table start
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mov cx,#32 ; 32 rows
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InitPTLoop:
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mov [bx],ax
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add ax,#32
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inc bx
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dec cx
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bnz InitPTLoop
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rts
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ClearTiles:
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mov bx,@$6000
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mov cx,@$3c0
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ClearLoop:
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mov [bx],ax
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inc bx
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dec cx
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bnz ClearLoop
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rts
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ClearSprites:
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mov bx,@$7f00
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mov ax,#0
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mov cx,#$40
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ClearSLoop:
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mov ax,[bx]
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add ax,@$101
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mov [bx],ax
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inc bx
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dec cx
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bnz ClearSLoop
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rts
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__endasm
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};
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end
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`endif
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endmodule
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