186 lines
4.0 KiB
Verilog
186 lines
4.0 KiB
Verilog
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`include "hvsync_generator.v"
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`include "sprite_bitmap.v"
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`include "sprite_renderer.v"
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`include "cpu8.v"
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// uncomment to see scope view
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//`define DEBUG
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module frame_buffer_top(clk, reset, hsync, vsync, hpaddle, vpaddle,
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address_bus, to_cpu, from_cpu, write_enable
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`ifdef DEBUG
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, output [7:0] A
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, output [7:0] B
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, output [7:0] IP
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, output carry
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, output zero
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`else
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,rgb
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`endif
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);
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input clk, reset;
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input hpaddle, vpaddle;
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output hsync, vsync;
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wire display_on;
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wire [8:0] hpos;
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wire [8:0] vpos;
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`ifdef DEBUG
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assign IP = cpu.IP;
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assign A = cpu.A;
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assign B = cpu.B;
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assign carry = cpu.carry;
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assign zero = cpu.zero;
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`else
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output [3:0] rgb;
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`endif
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parameter IN_HPOS = 8'b01000000;
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parameter IN_VPOS = 8'b01000001;
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parameter IN_FLAGS = 8'b01000010;
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parameter IN_VPU = 8'b01000011;
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reg [7:0] ram[0:63];
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reg [7:0] rom[0:127];
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output wire [7:0] address_bus;
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output reg [7:0] to_cpu;
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output wire [7:0] from_cpu;
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output wire write_enable;
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CPU cpu(.clk(clk),
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.reset(reset),
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.address(address_bus),
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.data_in(to_cpu),
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.data_out(from_cpu),
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.write(write_enable));
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always @(posedge clk)
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if (write_enable) begin
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casez (address_bus)
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// VPU lo byte
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8'b0001000: begin
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vpu_write[15:8] <= from_cpu;
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end
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// VPU hi byte
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8'b0001001: begin
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vpu_write[7:0] <= from_cpu;
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end
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// VPU write
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8'b0001010: begin
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vpu_ram[vpu_write] <= from_cpu[7:4];
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vpu_ram[vpu_write+1] <= from_cpu[3:0];
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vpu_write <= vpu_write + 2;
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end
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// VPU move
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8'b0001011: begin
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// sign extend
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vpu_write <= {
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vpu_write[15:8] + { {4{from_cpu[7]}}, from_cpu[7:4] },
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vpu_write[7:0] + { {4{from_cpu[3]}}, from_cpu[3:0] }
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};
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end
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default: ram[address_bus[5:0]] <= from_cpu;
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endcase
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end
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always @(*)
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casez (address_bus)
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// RAM
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8'b00??????: to_cpu = ram[address_bus[5:0]];
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// special read registers
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IN_HPOS: to_cpu = hpos[7:0];
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IN_VPOS: to_cpu = vpos[7:0];
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IN_FLAGS: to_cpu = {3'b0,
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vsync, hsync, vpaddle, hpaddle, display_on};
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IN_VPU: to_cpu = {vpu_ram[vpu_write], vpu_ram[vpu_write+1]};
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// ROM
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8'b1???????: to_cpu = rom[address_bus[7:0] + 128];
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default: ;
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endcase
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(0),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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reg [3:0] vpu_ram[0:65535];
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reg [15:0] vpu_read;
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reg [15:0] vpu_write;
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reg [3:0] rgb;
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always @(posedge clk) begin
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if (!hpos[8] && !vpos[8]) begin
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rgb <= vpu_ram[vpu_read];
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vpu_read <= vpu_read + 1;
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end else begin
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rgb <= 0;
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if (vpos[8])
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vpu_read <= 0;
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end
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end
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\end{lstlisting}
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We also have a simple test program that writes repeated patterns to the VPU:
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\begin{lstlisting}[language=femto8]
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`ifdef EXT_INLINE_ASM
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initial begin
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rom = '{
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__asm
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.arch femto8
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.org 128
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.len 128
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.define VPU_LO 8
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.define VPU_HI 9
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.define VPU_WRITE 10
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.define VPU_MOVE 11
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.define IN_HPOS $40
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.define IN_VPOS $41
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.define IN_FLAGS $42
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.define F_DISPLAY 1
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.define F_HPADDLE 2
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.define F_VPADDLE 4
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.define F_HSYNC 8
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.define F_VSYNC 16
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Start:
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zero A
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sta VPU_LO
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sta VPU_HI
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sta 0
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DisplayLoop:
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zero B
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mov A,[b]
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sta VPU_WRITE
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sta VPU_MOVE
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sta VPU_WRITE
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sta VPU_MOVE
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sta VPU_WRITE
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sta VPU_MOVE
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lda #F_VSYNC
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ldb #IN_FLAGS
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and none,[B]
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bz DisplayLoop
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WaitVsync:
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and none,[B]
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bnz WaitVsync
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zero B
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mov A,[b]
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inc A
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sta 0
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jmp DisplayLoop
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__endasm
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};
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end
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`endif
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