59 lines
1.1 KiB
Verilog
59 lines
1.1 KiB
Verilog
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`include "hvsync_generator.v"
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/*
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Paddle demonstration.
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*/
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module paddles_top(clk, reset, hsync, vsync, hpaddle, vpaddle, rgb);
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input clk, reset;
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input hpaddle, vpaddle;
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output hsync, vsync;
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output [2:0] rgb;
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wire display_on;
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wire [8:0] hpos;
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wire [8:0] vpos;
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// player position (only set at VSYNC)
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reg [7:0] player_x;
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reg [7:0] player_y;
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// paddle position (set continuously during frame)
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reg [7:0] paddle_x;
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reg [7:0] paddle_y;
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// read horizontal paddle
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always @(posedge hpaddle)
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paddle_x <= vpos[7:0];
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// read vertical paddle
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always @(posedge vpaddle)
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paddle_y <= vpos[7:0];
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// update player_x and player_y
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always @(posedge vsync)
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begin
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player_x <= paddle_x;
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player_y <= paddle_y;
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end
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(reset),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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// display paddle positions on screen
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wire h = hpos[7:0] >= paddle_x;
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wire v = vpos[7:0] >= paddle_y;
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assign rgb = {1'b0, display_on && h, display_on && v};
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endmodule
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