43 lines
885 B
Verilog
43 lines
885 B
Verilog
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`include "hvsync_generator.v"
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/*
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Switch test program.
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Player 1 Keys: arrow keys + space + shift
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Player 2 Keys: A/D/W/S + T + R
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*/
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module switches_top(clk, reset, hsync, vsync,
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switches_p1, switches_p2,
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rgb);
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input clk, reset;
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input [7:0] switches_p1;
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input [7:0] switches_p2;
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output hsync, vsync;
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output [2:0] rgb;
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wire display_on;
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wire [8:0] hpos;
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wire [8:0] vpos;
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(reset),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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// select p1 bit based on vertical position
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wire p1gfx = switches_p1[vpos[7:5]];
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// select p2 bit based on horizontal position
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wire p2gfx = switches_p2[hpos[7:5]];
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assign rgb = {1'b0,
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display_on && p1gfx,
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display_on && p2gfx};
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endmodule
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